From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from Sweeper2.alphanetworks.com (sweeper2.alphanetworks.com [210.202.42.140]) by ozlabs.org (Postfix) with ESMTP id 669EDDDE24 for ; Wed, 12 Nov 2008 01:32:03 +1100 (EST) From: "jay_chen" To: Subject: MPC8349 DMA Date: Tue, 11 Nov 2008 22:16:51 +0800 Message-ID: <0697112B46494D3DB284F1EBA6F65D4E@alphajay> MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_011E_01C9444B.34D59BA0" List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , This is a multi-part message in MIME format. ------=_NextPart_000_011E_01C9444B.34D59BA0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii" Hi, I am using 2.6.14.5 and MPC8349. I got some DMA problems with PCI devices. So, I tried to understand the DMA stuff of linux. I have one question about cache coherency. In dma-mapping.h, I found some functions are defined as NULL. For example: #define dma_cache_inv(_start,_size) do { } while (0) #define dma_cache_wback(_start,_size) do { } while (0) #define dma_cache_wback_inv(_start,_size) do { } while (0) #define __dma_alloc_coherent(gfp, size, handle) NULL #define __dma_free_coherent(size, addr) do { } while (0) #define __dma_sync(addr, size, rw) do { } while (0) #define __dma_sync_page(pg, off, sz, rw) do { } while (0) Does this mean that I don't need to take care of cache coherency in MPC83xx platform? So, I could use any range of memory for DMA transferring and the hardware will take care of the cache coherency for me? Thanks a lot. Jay Chen. ------=_NextPart_000_011E_01C9444B.34D59BA0 Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset="us-ascii"

Hi,

I am using 2.6.14.5=20 and MPC8349.

I got some DMA=20 problems with PCI devices.

So, I tried to=20 understand the DMA stuff of linux.

I have one question=20 about cache coherency.

In dma-mapping.h, I=20 found some functions are defined as NULL.

For=20 example:

#define=20 dma_cache_inv(_start,_size) do { } while (0)
#define=20 dma_cache_wback(_start,_size) do { } while (0)
#define=20 dma_cache_wback_inv(_start,_size) do { } while = (0)

#define=20 __dma_alloc_coherent(gfp, size, handle) NULL
#define=20 __dma_free_coherent(size, addr) do { } while (0)
#define=20 __dma_sync(addr, size, rw) do { } while (0)
#define=20 __dma_sync_page(pg, off, sz, rw) do { } while = (0)

Does this mean that I=20 don't need to take care of cache coherency in MPC83xx=20 platform?

So, I could use any=20 range of memory for DMA transferring and the hardware will take care of = the=20 cache coherency for me?

Thanks a=20 lot.

&nbs= p; = ; = =20 Jay Chen.

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