From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xes-inc.com (unknown [24.196.136.110]) by ozlabs.org (Postfix) with ESMTP id 2B2F667A85 for ; Sat, 5 Mar 2005 03:11:17 +1100 (EST) Message-ID: <0bb801c520d1$25c5f070$1500340a@matts> From: "Matthew Starzewski" To: "akash kaul" References: <001201c52091$61bcb130$1b69cb0a@BGCW0166> Date: Fri, 4 Mar 2005 09:45:10 -0600 MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_0BB5_01C5209E.DB247B90" Cc: linuxppc-embedded@ozlabs.org Subject: Re: MCC driver help List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , This is a multi-part message in MIME format. ------=_NextPart_000_0BB5_01C5209E.DB247B90 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Akash, What hardware are you using? I know Extreme Engineering has 8280-capable cards with a Linux MCC driver available. PMC: http://www.xes-inc.com/Products/XPort/XPort2000/XPort2000.html PCI: http://www.xes-inc.com/Products/XPort/XPort2010/XPort2010.html CompactPCI: http://www.xes-inc.com/Products/XPort/XPort2020/XPort2020.html For what it's worth, Matt ----- Original Message -----=20 From: akash kaul=20 To: linuxppc-embedded@ozlabs.org=20 Sent: Friday, March 04, 2005 2:08 AM Subject: MCC driver help =20 =20 Hi All, =20 We are developing MCC driver for MPC8280. We are using TDMD2 for = 2 channels in HDLC mode.=20 =20 Currently we are testing using internal/external loopback setting. = For this we have connected BRG6 Output to CLK19 and TMR3IN (timer3 = input). The TMR3O(timer 3 output) is fed to L1RSYNC. We are receiving = GUN interrupt. In the first interrupt we are receiving IDL interrupt = followwd by GUN interrupt and the driver stops. We have verified the reasons given for this.But not able to = overcome this problem. I have pasted some of the code snippets of my driver which i am = doubtful of. I hope to get some comments from the group on this. =20 Please find below some of the code snippets:=20 =20 /*Configuring SIxMR for TDMD2*/ immap->im_siramctl2.si_dmr =3D 0xA68; /*(SI_M_CRT | = SI_M_SDM_INTERNAL_LOOPBACK | SI_M_SAD_0 | SI_M_CE | SI_M_FE | SI_M_SL | = SI_M_RFSD_2BIT_DELAY);*/ /* SI2 RAM programming*/ immap->im_si2txram[0] =3D ( SIRAM_MCC | (SIRAM_CNT_1<<2) = |SIRAM_RESOL_BYTE| (128<<5)); immap->im_si2txram[1] =3D ( SIRAM_MCC | (SIRAM_CNT_8<<2) | = SIRAM_RESOL_BYTE | SIRAM_ENTRY_LAST | (129<<5)); =20 immap->im_si2rxram[0] =3D ( SIRAM_MCC | (SIRAM_CNT_1<<2) = |SIRAM_RESOL_BYTE| (128<<5)); immap->im_si2rxram[1] =3D ( SIRAM_MCC |(SIRAM_CNT_8<<2) = |SIRAM_RESOL_BYTE| SIRAM_ENTRY_LAST | (129<<5)); /*Clock and BRG6 initialization */ immap->im_cpmtimer.cpmt_tmr3=3D 0x0e; = /*(CPM_TIMER_ICLK|CPM_TIMER_GE|CPM_TIMER_FRR);*/ immap->im_cpmtimer.cpmt_trr3=3D 0x41; /* 63 bits :: Is this = right, I have set it to 63 because my first channel is 1 bit wide and = second channel is 64 bit wide */ immap->im_cpmtimer.cpmt_tgcr2 =3D 0x09 ;=20 immap->im_brgc6 =3D 0x00010000; /* Directly feeding BRG6 with = BRG_CLK which is of 33Mhz in my board*/ =20 /*Port pin configuration*/ immap->im_ioport.iop_psorb |=3D = (TDMD2_L1TXD|TDMD2_L1RXD|TDMD2_L1RSYNC); =20 immap->im_ioport.iop_pdirb &=3D = ~(TDMD2_L1TXD|TDMD2_L1RXD|TDMD2_L1RSYNC); =20 immap->im_ioport.iop_pparb |=3D = (TDMD2_L1TXD|TDMD2_L1RXD|TDMD2_L1RSYNC); =20 =20 immap->im_ioport.iop_psora &=3D ~(TDMD2_CLK19);=20 immap->im_ioport.iop_pdira &=3D ~(TDMD2_CLK19);=20 immap->im_ioport.iop_ppara |=3D (TDMD2_CLK19);=20 =20 immap->im_ioport.iop_psorc &=3D ~(TDMD2_TIN3 | TDMD2_BRGO6 = |TDMD2_TOUT3); immap->im_ioport.iop_pdirc |=3D (TDMD2_BRGO6 | TDMD2_TOUT3);=20 immap->im_ioport.iop_pdirc &=3D ~(TDMD2_TIN3);=20 immap->im_ioport.iop_pparc |=3D (TDMD2_TIN3 | TDMD2_BRGO6 | = TDMD2_TOUT3);=20 =20 immap->im_cpmux.cmx_si2cr |=3D (TDMD2_CLK19_CS); =20 /*Initialize RxBDs.*/ called for two channels =20 for (index =3D 0; index < MAX_NUM_BD; index++) { if( index !=3D (MAX_NUM_BD-1) ) /* If not the last RxBD for = this channel */ { rx_tx_bd->rx_bd[index+offset].cbd_sc =3D 0x9000; /* = Empty, Interrupt */ } else /* if last RxBD for this channel */ { rx_tx_bd->rx_bd[index+offset].cbd_sc =3D 0xB000; /* = Empty, Interrupt,and wrap */ } =20 /* set the CM bit in the RxBDS */ rx_tx_bd->rx_bd[index+offset].cbd_sc |=3D 0x0200; /* set = continuous bit */ =20 /* clear the buffer length */ rx_tx_bd->rx_bd[index+offset].cbd_datlen =3D 0; =20 /* set address to point to proper receive area for this BD = in the bufferpool scheme this program uses */ va_ptr =3D (u32 *)cpm2_hostalloc(MAX_BUF_LEN, 8); rx_tx_bd->rx_bd[index+offset].cbd_bufaddr =3D (uint = )__pa(va_ptr); =20 } /* end for loop initializing RxBDs */ /* Initialize TxBDs and RX BDs for both the channels*/ =20 for ( offset =3D 0, counter =3D 0; counter < NUM_CHANS_PER_TDM;) { /* Initialize TxBDs. */ for (index=3D0; index < MAX_NUM_BD; index++) { if( index !=3D (MAX_NUM_BD-1) ) /* If not the last TxBD for = this channel */ { /* Set Ready bit */ rx_tx_bd->tx_bd[index+offset].cbd_sc =3D 0x8000; =20 /* If this channel is HDLC, also set Last and TC bits */ rx_tx_bd->tx_bd[index+offset].cbd_sc |=3D 0x0C00; } else /* if last TxBD for this channel */ { /* Set Ready, Wrap bits */ rx_tx_bd->tx_bd[index+offset].cbd_sc =3D 0xA000; =20 /* If this channel is HDLC, also set Last and TC bits */ rx_tx_bd->tx_bd[index+offset].cbd_sc |=3D 0x0C00; }; =20 /* set the CM bit in the TxBDS */ rx_tx_bd->tx_bd[index+offset].cbd_sc |=3D 0x0200; /* set = continuous bit */ =20 /* set address to point to proper receive area for this BD = in the bufferpool scheme this program uses */ va_ptr =3D (u32 *)cpm2_hostalloc(MAX_BUF_LEN, 8); memset(va_ptr,(u8)'B', MAX_BUF_LEN); rx_tx_bd->tx_bd[index+offset].cbd_bufaddr =3D (uint = )__pa(va_ptr); /* load the buffer length */ rx_tx_bd->tx_bd[index+offset].cbd_datlen =3D = 54;//MAX_BUF_LEN; }/* end for loop initializing TxBDs */ =20 offset =3D (++ counter * MAX_NUM_BD); } /* End of outer for loop*/ /* MCC Init*/ =20 #define TDM 3 immap->im_mcc2.mcc_mccf =3D TDM | (TDM << 2) | (TDM << 4) | (TDM = << 6); /* Enable TDM2 to use channels 128 to 225 */ =20 /* Clear all the interrupts and enable the required interrupts */ immap->im_mcc2.mcc_mcce =3D (MCC_EM_GOV | MCC_EM_GUN | = MCC_EM_TINT | MCC_EM_TQOV | MCC_EM_RINT3 | MCC_EM_QOV3 | = MCC_EM_RINT2 | MCC_EM_QOV2 |MCC_EM_RINT1 | MCC_EM_QOV1 | = MCC_EM_RINT0 | MCC_EM_QOV0); =20 immap->im_mcc2.mcc_mccm =3D (MCC_EM_GOV | MCC_EM_GUN | = MCC_EM_TINT | MCC_EM_TQOV | MCC_EM_RINT3 | MCC_EM_QOV3 | = MCC_EM_RINT2 | MCC_EM_QOV2 |MCC_EM_RINT1 | MCC_EM_QOV1 | = MCC_EM_RINT0 | MCC_EM_QOV0); Note : Apart from this i am doing global channel parameters, = channel specific parameters and xtra channel parameters. =20 /* Initialising the TX and Rx parameters */ while ((immap->im_cpm.cp_cpcr & CPCR_FLG) !=3D READY_TO_RX_CMD); immap->im_cpm.cp_cpcr =3D CPCR_INIT_TX_RX_ONECHANL | psbc | = (128<<6)| CPCR_FLG; /* ISSUE COMMAND */ while ((immap->im_cpm.cp_cpcr & CPCR_FLG) !=3D READY_TO_RX_CMD); =20 while ((immap->im_cpm.cp_cpcr & CPCR_FLG) !=3D READY_TO_RX_CMD); immap->im_cpm.cp_cpcr =3D CPCR_INIT_TX_RX_ONECHANL | psbc | = (129<<6)| CPCR_FLG; /* ISSUE COMMAND */ while ((immap->im_cpm.cp_cpcr & CPCR_FLG) !=3D READY_TO_RX_CMD); =20 /*Enabling TDMD2 */ immap->im_siramctl2.si_gmr =3D 1 << 3; =20 =20 Any hint would be greatly appreciated. =20 Best Regards, -Akash Kaul -------------------------------------------------------------------------= ----- _______________________________________________ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded ------=_NextPart_000_0BB5_01C5209E.DB247B90 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Akash,
 
What hardware are you using?  I = know Extreme=20 Engineering
has 8280-capable cards with a = Linux MCC driver available.
 
PMC:
h= ttp://www.xes-inc.com/Products/XPort/XPort2000/XPort2000.html<= /DIV>
 
PCI:
h= ttp://www.xes-inc.com/Products/XPort/XPort2010/XPort2010.html<= /DIV>
 
CompactPCI:
h= ttp://www.xes-inc.com/Products/XPort/XPort2020/XPort2020.html<= /DIV>
 
For what it's worth,
Matt
 
----- Original Message -----
From:=20 akash kaul
Sent: Friday, March 04, 2005 = 2:08=20 AM
Subject: MCC driver help

 

 

Hi = All,

 

    We are=20 developing MCC driver for MPC8280. We are using = TDMD2  for=20 2 channels in HDLC mode.

 

    = Currently we=20 are testing using internal/external loopback setting. For this = we have=20 connected BRG6 Output to CLK19 and TMR3IN (timer3 input). The = TMR3O(timer 3=20 output) is fed to L1RSYNC. We are receiving GUN interrupt. In the = first=20 interrupt we are receiving IDL interrupt followwd by = GUN interrupt=20 and the driver stops.

    We have=20 verified the reasons given for this.But not able to overcome this=20 problem.

    I have=20 pasted some of the code snippets of my driver which i am doubtful = of.  I=20 hope to get some comments from the group on=20 this.

 

    = Please find=20 below  some of the code snippets: =

 

   =20 /*Configuring=20 SIxMR for=20 TDMD2*/

    immap->im_siramctl2.si_dmr =3D = 0xA68;  =20 /*(SI_M_CRT | SI_M_SDM_INTERNAL_LOOPBACK | SI_M_SAD_0 | SI_M_CE | = SI_M_FE |=20 SI_M_SL = | SI_M_RFSD_2BIT_DELAY);*/

    /* SI2 RAM=20 = programming*/

    immap->im_si2txram[0]=20 =3D ( SIRAM_MCC | (SIRAM_CNT_1<<2) |SIRAM_RESOL_BYTE|=20 (128<<5));
    immap->im_si2txram[1] =3D ( = SIRAM_MCC=20 | (SIRAM_CNT_8<<2) | SIRAM_RESOL_BYTE | SIRAM_ENTRY_LAST |=20 (129<<5));

 

   =20 immap->im_si2rxram[0] =3D ( SIRAM_MCC | (SIRAM_CNT_1<<2)=20 |SIRAM_RESOL_BYTE| (128<<5));
   =20 immap->im_si2rxram[1] =3D ( SIRAM_MCC |(SIRAM_CNT_8<<2)=20 |SIRAM_RESOL_BYTE| SIRAM_ENTRY_LAST |=20 (129<<5));

   =20 /*Clock and BRG6=20 initialization=20 */

    immap->im_cpmtimer.cpmt_tmr3=3D 0x0e;=20 = /*(CPM_TIMER_ICLK|CPM_TIMER_GE|CPM_TIMER_FRR);*/
   &nb= sp;immap->im_cpmtimer.cpmt_trr3=3D =20 0x41;   /* 63 bits :: Is this right, = I have=20 set it to 63 because=20 my first channel is 1 bit wide and second channel is 64 bit=20 wide */
    immap->im_cpmtimer.cpmt_tgcr2 =3D 0x09=20 ; 
    immap->im_brgc6 =3D = 0x00010000;  /*=20 Directly feeding BRG6 with BRG_CLK which is of 33Mhz in my=20 board*/

 

   =20 /*Port pin=20 = configuration*/

    immap->im_ioport.iop_psorb =20 |=3D=20 = (TDMD2_L1TXD|TDMD2_L1RXD|TDMD2_L1RSYNC);        =20 immap->im_ioport.iop_pdirb  &=3D=20 = ~(TDMD2_L1TXD|TDMD2_L1RXD|TDMD2_L1RSYNC);   =

   =20 immap->im_ioport.iop_pparb  |=3D=20 = (TDMD2_L1TXD|TDMD2_L1RXD|TDMD2_L1RSYNC);    

 

   =20 immap->im_ioport.iop_psora &=3D=20 ~(TDMD2_CLK19); 

   =20 immap->im_ioport.iop_pdira &=3D=20 ~(TDMD2_CLK19); 
    = immap->im_ioport.iop_ppara |=3D=20 (TDMD2_CLK19);

   =20

   =20 immap->im_ioport.iop_psorc  &=3D ~(TDMD2_TIN3 | = TDMD2_BRGO6=20 |TDMD2_TOUT3);

   =20 immap->im_ioport.iop_pdirc  |=3D (TDMD2_BRGO6 |=20 TDMD2_TOUT3); 
    = immap->im_ioport.iop_pdirc =20 &=3D ~(TDMD2_TIN3); 

   =20 immap->im_ioport.iop_pparc  |=3D (TDMD2_TIN3 | TDMD2_BRGO6 |=20 TDMD2_TOUT3);

  

   =20 immap->im_cpmux.cmx_si2cr |=3D=20 (TDMD2_CLK19_CS);

 

   =20 /*Initialize RxBDs.*/  called for two=20 channels

  

      for=20 (index =3D 0; index < MAX_NUM_BD;=20 index++)
      =20 {
          if( index = !=3D=20 (MAX_NUM_BD-1) )  /* If not the last RxBD for this channel=20 */
         =20 = {
           &n= bsp;=20 rx_tx_bd->rx_bd[index+offset].cbd_sc =3D 0x9000; /* Empty, = Interrupt=20 */
         =20 }
          else  = /* if=20 last RxBD for this channel=20 */
         =20 = {
           &n= bsp;=20 rx_tx_bd->rx_bd[index+offset].cbd_sc =3D 0xB000;   /* = Empty,=20 Interrupt,and wrap=20 */
         =20 }

 

         =20 /* set the CM bit in the = RxBDS        =20 */
         =20 rx_tx_bd->rx_bd[index+offset].cbd_sc |=3D 0x0200;   /* = set=20 continuous bit */

 

         =20 /* clear the buffer length=20 */
         =20 rx_tx_bd->rx_bd[index+offset].cbd_datlen =3D=20 0;

 

         =20 /* set address to point to proper receive area = for   this BD in=20 the bufferpool scheme this program uses=20 */
          va_ptr = =3D (u32=20 *)cpm2_hostalloc(MAX_BUF_LEN,=20 8);
         =20 rx_tx_bd->rx_bd[index+offset].cbd_bufaddr =3D (uint=20 )__pa(va_ptr);

 

      =20 } /* end for loop initializing RxBDs = */

/* Initialize TxBDs and = RX BDs for=20 both the=20 = channels*/

 

  for ( offset =3D = 0, counter =3D=20 0; counter < NUM_CHANS_PER_TDM;)
   =20 {
       /* = Initialize=20 TxBDs. */
    &nbs= p; =20 for (index=3D0; index < MAX_NUM_BD;=20 index++)
      =20 {
          if( index = !=3D=20 (MAX_NUM_BD-1) )  /* If not the last TxBD for this channel=20 */
         =20 = {
           &n= bsp;=20 /* Set Ready bit=20 = */
           &= nbsp;=20 rx_tx_bd->tx_bd[index+offset].cbd_sc =3D=20 0x8000;

 

           =  =20 /* If this channel is HDLC, also set Last and TC bits=20 = */
           &= nbsp;=20 rx_tx_bd->tx_bd[index+offset].cbd_sc |=3D=20 0x0C00;
         =20 }
          else  = /* if=20 last TxBD for this channel=20 */
         =20 = {
           &n= bsp;=20 /* Set Ready, Wrap bits=20 = */
           &= nbsp;=20 rx_tx_bd->tx_bd[index+offset].cbd_sc =3D=20 0xA000;

 

           =  =20 /* If this channel is HDLC, also set Last and TC bits=20 = */
           &= nbsp;=20 rx_tx_bd->tx_bd[index+offset].cbd_sc |=3D=20 0x0C00;
         =20 };

 

         =20 /* set the CM bit in the = TxBDS        =20 */
          =20 rx_tx_bd->tx_bd[index+offset].cbd_sc |=3D 0x0200;   /* = set=20 continuous bit */

 

         =20 /* set address to point to proper receive area for this BD in the = bufferpool scheme this program uses=20 */
           = va_ptr =3D=20 (u32 *)cpm2_hostalloc(MAX_BUF_LEN,=20 8);
          =20 memset(va_ptr,(u8)'B',=20 = MAX_BUF_LEN);
         &n= bsp;=20 rx_tx_bd->tx_bd[index+offset].cbd_bufaddr =3D (uint=20 )__pa(va_ptr);


         =20 /* load the buffer length=20 */
          =20 rx_tx_bd->tx_bd[index+offset].cbd_datlen =3D=20 54;//MAX_BUF_LEN;
       }/* end for = loop=20 initializing TxBDs */

 

 offset =3D (++ = counter *=20 MAX_NUM_BD);
} /* End of outer for=20 loop*/

  /* = MCC=20 Init*/

 

   =20 #define TDM    3

   =20 immap->im_mcc2.mcc_mccf =3D TDM | (TDM << 2) | (TDM = << 4) |=20 (TDM << 6); /* Enable TDM2 to use channels 128 to 225=20 */

 

    /* = Clear all=20 the interrupts and enable the required interrupts = */
   =20 immap->im_mcc2.mcc_mcce =3D (MCC_EM_GOV  | MCC_EM_GUN | = MCC_EM_TINT |=20 MCC_EM_TQOV=20 = |
           &n= bsp;           &nb= sp;      =20 MCC_EM_RINT3 | MCC_EM_QOV3 | MCC_EM_RINT2 |=20 = MCC_EM_QOV2
         &nbs= p;            = ;       =20 |MCC_EM_RINT1 | MCC_EM_QOV1 | MCC_EM_RINT0 |=20 MCC_EM_QOV0);

 

   =20 immap->im_mcc2.mcc_mccm =3D (MCC_EM_GOV  | MCC_EM_GUN | = MCC_EM_TINT |=20 MCC_EM_TQOV=20 = |
           &n= bsp;           &nb= sp;      =20 MCC_EM_RINT3 | MCC_EM_QOV3 | MCC_EM_RINT2 |=20 = MCC_EM_QOV2
         &nbs= p;            = ;       =20 |MCC_EM_RINT1 | MCC_EM_QOV1 | MCC_EM_RINT0 |=20 MCC_EM_QOV0);

    Note = : Apart=20 from this i am doing global channel parameters, channel specific = parameters=20 and xtra channel parameters.

 

  /*=20 Initialising the TX and Rx = parameters */

    while=20 ((immap->im_cpm.cp_cpcr & CPCR_FLG) !=3D=20 READY_TO_RX_CMD);

   =20 immap->im_cpm.cp_cpcr =3D CPCR_INIT_TX_RX_ONECHANL | psbc | = (128<<6)|=20 CPCR_FLG;       /* ISSUE COMMAND=20 */

    while = ((immap->im_cpm.cp_cpcr & CPCR_FLG) !=3D=20 READY_TO_RX_CMD);

 

    while = ((immap->im_cpm.cp_cpcr & CPCR_FLG) !=3D=20 READY_TO_RX_CMD);

   =20 immap->im_cpm.cp_cpcr =3D CPCR_INIT_TX_RX_ONECHANL | psbc | = (129<<6)|=20 CPCR_FLG;       /* ISSUE COMMAND=20 */

    while = ((immap->im_cpm.cp_cpcr & CPCR_FLG) !=3D=20 READY_TO_RX_CMD);

 

  /*Enabling=20 = TDMD2 */

    immap->im_siramctl2.si_gmr =3D  1 = <<=20 3;

 

 

Any=20 hint would be greatly appreciated.

 

 Best=20 Regards,


 -Akash=20 Kaul

=

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