* Re: MCC driver help
2005-03-04 8:08 ` MCC driver help akash kaul
@ 2005-03-04 15:45 ` Matthew Starzewski
0 siblings, 0 replies; 2+ messages in thread
From: Matthew Starzewski @ 2005-03-04 15:45 UTC (permalink / raw)
To: akash kaul; +Cc: linuxppc-embedded
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Akash,
What hardware are you using? I know Extreme Engineering
has 8280-capable cards with a Linux MCC driver available.
PMC:
http://www.xes-inc.com/Products/XPort/XPort2000/XPort2000.html
PCI:
http://www.xes-inc.com/Products/XPort/XPort2010/XPort2010.html
CompactPCI:
http://www.xes-inc.com/Products/XPort/XPort2020/XPort2020.html
For what it's worth,
Matt
----- Original Message -----
From: akash kaul
To: linuxppc-embedded@ozlabs.org
Sent: Friday, March 04, 2005 2:08 AM
Subject: MCC driver help
Hi All,
We are developing MCC driver for MPC8280. We are using TDMD2 for 2 channels in HDLC mode.
Currently we are testing using internal/external loopback setting. For this we have connected BRG6 Output to CLK19 and TMR3IN (timer3 input). The TMR3O(timer 3 output) is fed to L1RSYNC. We are receiving GUN interrupt. In the first interrupt we are receiving IDL interrupt followwd by GUN interrupt and the driver stops.
We have verified the reasons given for this.But not able to overcome this problem.
I have pasted some of the code snippets of my driver which i am doubtful of. I hope to get some comments from the group on this.
Please find below some of the code snippets:
/*Configuring SIxMR for TDMD2*/
immap->im_siramctl2.si_dmr = 0xA68; /*(SI_M_CRT | SI_M_SDM_INTERNAL_LOOPBACK | SI_M_SAD_0 | SI_M_CE | SI_M_FE | SI_M_SL | SI_M_RFSD_2BIT_DELAY);*/
/* SI2 RAM programming*/
immap->im_si2txram[0] = ( SIRAM_MCC | (SIRAM_CNT_1<<2) |SIRAM_RESOL_BYTE| (128<<5));
immap->im_si2txram[1] = ( SIRAM_MCC | (SIRAM_CNT_8<<2) | SIRAM_RESOL_BYTE | SIRAM_ENTRY_LAST | (129<<5));
immap->im_si2rxram[0] = ( SIRAM_MCC | (SIRAM_CNT_1<<2) |SIRAM_RESOL_BYTE| (128<<5));
immap->im_si2rxram[1] = ( SIRAM_MCC |(SIRAM_CNT_8<<2) |SIRAM_RESOL_BYTE| SIRAM_ENTRY_LAST | (129<<5));
/*Clock and BRG6 initialization */
immap->im_cpmtimer.cpmt_tmr3= 0x0e; /*(CPM_TIMER_ICLK|CPM_TIMER_GE|CPM_TIMER_FRR);*/
immap->im_cpmtimer.cpmt_trr3= 0x41; /* 63 bits :: Is this right, I have set it to 63 because my first channel is 1 bit wide and second channel is 64 bit wide */
immap->im_cpmtimer.cpmt_tgcr2 = 0x09 ;
immap->im_brgc6 = 0x00010000; /* Directly feeding BRG6 with BRG_CLK which is of 33Mhz in my board*/
/*Port pin configuration*/
immap->im_ioport.iop_psorb |= (TDMD2_L1TXD|TDMD2_L1RXD|TDMD2_L1RSYNC);
immap->im_ioport.iop_pdirb &= ~(TDMD2_L1TXD|TDMD2_L1RXD|TDMD2_L1RSYNC);
immap->im_ioport.iop_pparb |= (TDMD2_L1TXD|TDMD2_L1RXD|TDMD2_L1RSYNC);
immap->im_ioport.iop_psora &= ~(TDMD2_CLK19);
immap->im_ioport.iop_pdira &= ~(TDMD2_CLK19);
immap->im_ioport.iop_ppara |= (TDMD2_CLK19);
immap->im_ioport.iop_psorc &= ~(TDMD2_TIN3 | TDMD2_BRGO6 |TDMD2_TOUT3);
immap->im_ioport.iop_pdirc |= (TDMD2_BRGO6 | TDMD2_TOUT3);
immap->im_ioport.iop_pdirc &= ~(TDMD2_TIN3);
immap->im_ioport.iop_pparc |= (TDMD2_TIN3 | TDMD2_BRGO6 | TDMD2_TOUT3);
immap->im_cpmux.cmx_si2cr |= (TDMD2_CLK19_CS);
/*Initialize RxBDs.*/ called for two channels
for (index = 0; index < MAX_NUM_BD; index++)
{
if( index != (MAX_NUM_BD-1) ) /* If not the last RxBD for this channel */
{
rx_tx_bd->rx_bd[index+offset].cbd_sc = 0x9000; /* Empty, Interrupt */
}
else /* if last RxBD for this channel */
{
rx_tx_bd->rx_bd[index+offset].cbd_sc = 0xB000; /* Empty, Interrupt,and wrap */
}
/* set the CM bit in the RxBDS */
rx_tx_bd->rx_bd[index+offset].cbd_sc |= 0x0200; /* set continuous bit */
/* clear the buffer length */
rx_tx_bd->rx_bd[index+offset].cbd_datlen = 0;
/* set address to point to proper receive area for this BD in the bufferpool scheme this program uses */
va_ptr = (u32 *)cpm2_hostalloc(MAX_BUF_LEN, 8);
rx_tx_bd->rx_bd[index+offset].cbd_bufaddr = (uint )__pa(va_ptr);
} /* end for loop initializing RxBDs */
/* Initialize TxBDs and RX BDs for both the channels*/
for ( offset = 0, counter = 0; counter < NUM_CHANS_PER_TDM;)
{
/* Initialize TxBDs. */
for (index=0; index < MAX_NUM_BD; index++)
{
if( index != (MAX_NUM_BD-1) ) /* If not the last TxBD for this channel */
{
/* Set Ready bit */
rx_tx_bd->tx_bd[index+offset].cbd_sc = 0x8000;
/* If this channel is HDLC, also set Last and TC bits */
rx_tx_bd->tx_bd[index+offset].cbd_sc |= 0x0C00;
}
else /* if last TxBD for this channel */
{
/* Set Ready, Wrap bits */
rx_tx_bd->tx_bd[index+offset].cbd_sc = 0xA000;
/* If this channel is HDLC, also set Last and TC bits */
rx_tx_bd->tx_bd[index+offset].cbd_sc |= 0x0C00;
};
/* set the CM bit in the TxBDS */
rx_tx_bd->tx_bd[index+offset].cbd_sc |= 0x0200; /* set continuous bit */
/* set address to point to proper receive area for this BD in the bufferpool scheme this program uses */
va_ptr = (u32 *)cpm2_hostalloc(MAX_BUF_LEN, 8);
memset(va_ptr,(u8)'B', MAX_BUF_LEN);
rx_tx_bd->tx_bd[index+offset].cbd_bufaddr = (uint )__pa(va_ptr);
/* load the buffer length */
rx_tx_bd->tx_bd[index+offset].cbd_datlen = 54;//MAX_BUF_LEN;
}/* end for loop initializing TxBDs */
offset = (++ counter * MAX_NUM_BD);
} /* End of outer for loop*/
/* MCC Init*/
#define TDM 3
immap->im_mcc2.mcc_mccf = TDM | (TDM << 2) | (TDM << 4) | (TDM << 6); /* Enable TDM2 to use channels 128 to 225 */
/* Clear all the interrupts and enable the required interrupts */
immap->im_mcc2.mcc_mcce = (MCC_EM_GOV | MCC_EM_GUN | MCC_EM_TINT | MCC_EM_TQOV |
MCC_EM_RINT3 | MCC_EM_QOV3 | MCC_EM_RINT2 | MCC_EM_QOV2
|MCC_EM_RINT1 | MCC_EM_QOV1 | MCC_EM_RINT0 | MCC_EM_QOV0);
immap->im_mcc2.mcc_mccm = (MCC_EM_GOV | MCC_EM_GUN | MCC_EM_TINT | MCC_EM_TQOV |
MCC_EM_RINT3 | MCC_EM_QOV3 | MCC_EM_RINT2 | MCC_EM_QOV2
|MCC_EM_RINT1 | MCC_EM_QOV1 | MCC_EM_RINT0 | MCC_EM_QOV0);
Note : Apart from this i am doing global channel parameters, channel specific parameters and xtra channel parameters.
/* Initialising the TX and Rx parameters */
while ((immap->im_cpm.cp_cpcr & CPCR_FLG) != READY_TO_RX_CMD);
immap->im_cpm.cp_cpcr = CPCR_INIT_TX_RX_ONECHANL | psbc | (128<<6)| CPCR_FLG; /* ISSUE COMMAND */
while ((immap->im_cpm.cp_cpcr & CPCR_FLG) != READY_TO_RX_CMD);
while ((immap->im_cpm.cp_cpcr & CPCR_FLG) != READY_TO_RX_CMD);
immap->im_cpm.cp_cpcr = CPCR_INIT_TX_RX_ONECHANL | psbc | (129<<6)| CPCR_FLG; /* ISSUE COMMAND */
while ((immap->im_cpm.cp_cpcr & CPCR_FLG) != READY_TO_RX_CMD);
/*Enabling TDMD2 */
immap->im_siramctl2.si_gmr = 1 << 3;
Any hint would be greatly appreciated.
Best Regards,
-Akash Kaul
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