From: Heiner Kallweit <hkallweit1@gmail.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Madhavan Srinivasan <maddy@linux.ibm.com>,
Michael Ellerman <mpe@ellerman.id.au>,
Nicholas Piggin <npiggin@gmail.com>,
Christophe Leroy <christophe.leroy@csgroup.eu>,
Pantelis Antoniou <pantelis.antoniou@gmail.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>
Subject: Re: [PATCH RFC] powerpc: switch two fixed phy links to full duplex
Date: Fri, 5 Dec 2025 22:16:42 +0100 [thread overview]
Message-ID: <10441fbd-8022-402e-8551-e0f8ec0449f0@gmail.com> (raw)
In-Reply-To: <5d302153-c7f6-48dc-95cc-0dc4f25045c6@lunn.ch>
On 12/5/2025 6:50 PM, Andrew Lunn wrote:
> On Fri, Dec 05, 2025 at 06:21:50PM +0100, Heiner Kallweit wrote:
>> These two fixed links are the only ones in-kernel specifying half duplex.
>> If these could be switched to full duplex, then half duplex handling
>> could be removed from phylib fixed phy, phylink, swphy.
>>
>> The SoC MAC's are capable of full duplex, fs_enet MAC driver is as well.
>> Anything that would keep us from switching to full duplex?
>
> What do we know about the device on the other end of the link? Maybe
> that is what is limiting it to 10Half?
>
I found no hint that anything is connected to this ethernet port on
the two boards. Hard to find any information because the boards are
>15yrs old. Seems this are dummy entries, just to let fs_enet load.
> Andrew
Heiner
prev parent reply other threads:[~2025-12-05 21:16 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-05 17:21 [PATCH RFC] powerpc: switch two fixed phy links to full duplex Heiner Kallweit
2025-12-05 17:50 ` Andrew Lunn
2025-12-05 21:16 ` Heiner Kallweit [this message]
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