From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Muhammad Sarwar <msarwar@mangrovesystems.com>
Cc: Jeff Angielski <jeff@theptrgroup.com>,
linuxppc-dev list <linuxppc-dev@lists.linuxppc.org>
Subject: RE: ppc826x BAD interrupts
Date: Sat, 17 Jan 2004 14:22:13 +1100 [thread overview]
Message-ID: <1074309733.8360.20.camel@gaston> (raw)
In-Reply-To: <8529B5552D4EAA4DAEDF49650C64B2B436E589@tarpon.mangrovesystems.com>
On Sat, 2004-01-17 at 03:29, Muhammad Sarwar wrote:
> This problem was discussed on mailing list before also and you can eliminate this problem by inserting a sync instruction at a certain place in the 8260 interrupt handling code. See, for example, http://www.geocrawler.com/archives/3/8358/2002/11/100/10173445/
>
> Add a __asm__ volatile("sync"); at the end of the m8260_mask_and_ack function in arch/ppc/kernel/ppc8260_pic.c to fix it.
The code looks like crap... do we have any guarantee that those accesses
are done in order and did read the controller ?
I'd rather add eieios and read back the value to enforce ordering...
Ben.
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2004-01-17 3:22 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-01-16 16:29 ppc826x BAD interrupts Muhammad Sarwar
2004-01-16 18:47 ` Jeff Angielski
2004-01-17 3:22 ` Benjamin Herrenschmidt [this message]
-- strict thread matches above, loose matches on Subject: below --
2004-01-16 16:02 Jeff Angielski
2004-01-16 16:35 ` Rob Baxter
2004-01-16 20:18 ` Randy Vinson
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