* [PATCH] fix TLB handling for 8xx on linuxppc-2.5
@ 2004-05-31 14:36 Pantelis Antoniou
2004-05-31 22:00 ` Benjamin Herrenschmidt
2004-06-02 15:13 ` Dan Malek
0 siblings, 2 replies; 6+ messages in thread
From: Pantelis Antoniou @ 2004-05-31 14:36 UTC (permalink / raw)
To: Dan Malek, Tom Rini, Paul Mackerras, Benjamin Herrenschmidt,
Linuxppc-Embedded
[-- Attachment #1: Type: text/plain, Size: 258 bytes --]
Hi
The following patch fixes the problems of 8xx with the latest
linuxppc-2.5 tree.
With it user space progresses properly.
Lots of gray areas remain and MM handling for 8xx is
mighty inefficient IMO.
Dan could you please take a look?
Regards
Pantelis
[-- Attachment #2: 8xx-mm-fix.patch --]
[-- Type: text/x-patch, Size: 5053 bytes --]
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper --exclude=ChangeSet linuxppc_2.5/arch/ppc/kernel/head_8xx.S linuxppc_2.5-intracom/arch/ppc/kernel/head_8xx.S
--- linuxppc_2.5/arch/ppc/kernel/head_8xx.S Mon May 31 10:52:29 2004
+++ linuxppc_2.5-intracom/arch/ppc/kernel/head_8xx.S Mon May 31 17:24:05 2004
@@ -157,6 +157,24 @@
SAVE_2GPRS(7, r11)
/*
+if ((val & (_PAGE_HWWRITE | _PAGE_RW | _PAGE_DIRTY)) == (_PAGE_RW | _PAGE_DIRTY))
+ val |= _PAGE_HWWRITE;
+else if ((val & (_PAGE_HWWRITE | _PAGE_RW | _PAGE_DIRTY)) == _PAGE_HWWRITE)
+ val &= ~_PAGE_HWWRITE;
+*/
+
+#define LAZY_DTLB_FIX \
+ rlwinm r12,r10,0,23,25; \
+ cmpwi r12,0xc0; \
+ bne+ 0f; \
+ ori r10,r10,0x100; \
+ b 1f; \
+ 0: cmpwi r12,0x100; \
+ bne+ 1f; \
+ rlwinm r10,r10,0,24,22; \
+ 1:
+
+/*
* Note: code which follows this uses cr0.eq (set if from kernel),
* r11, r12 (SRR0), and r9 (SRR1).
*
@@ -348,7 +366,6 @@
mtspr MD_TWC, r11 /* Load pte table base address */
mfspr r11, MD_TWC /* ....and get the pte address */
lwz r10, 0(r11) /* Get the pte */
-
ori r10, r10, _PAGE_ACCESSED
stw r10, 0(r11)
@@ -398,6 +415,7 @@
mfcr r10
stw r10, 0(r0)
stw r11, 4(r0)
+ stw r12, 16(r0)
mfspr r10, M_TWB /* Get level 1 table entry address */
/* If we are faulting a kernel address, we have to use the
@@ -440,6 +458,7 @@
mtspr MD_TWC, r11
mfspr r11, MD_TWC /* get the pte address again */
+ LAZY_DTLB_FIX
ori r10, r10, _PAGE_ACCESSED
stw r10, 0(r11)
@@ -463,6 +482,7 @@
lwz r11, 0(r0)
mtcr r11
lwz r11, 4(r0)
+ lwz r12, 16(r0)
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
#endif
@@ -472,6 +492,7 @@
lwz r11, 0(r0)
mtcr r11
lwz r11, 4(r0)
+ lwz r12, 16(r0)
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
#endif
@@ -505,6 +526,7 @@
mfcr r10
stw r10, 0(r0)
stw r11, 4(r0)
+ stw r12, 16(r0)
/* First, make sure this was a store operation.
*/
@@ -574,6 +596,7 @@
*/
ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
mfspr r11, MD_TWC /* Get pte address again */
+ LAZY_DTLB_FIX
stw r10, 0(r11) /* and update pte in table */
/* The Linux PTE won't go exactly into the MMU TLB.
@@ -596,6 +619,7 @@
lwz r11, 0(r0)
mtcr r11
lwz r11, 4(r0)
+ lwz r12, 16(r0)
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
#endif
@@ -605,6 +629,7 @@
lwz r11, 0(r0)
mtcr r11
lwz r11, 4(r0)
+ lwz r12, 16(r0)
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
#endif
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper --exclude=ChangeSet linuxppc_2.5/arch/ppc/kernel/misc.S linuxppc_2.5-intracom/arch/ppc/kernel/misc.S
--- linuxppc_2.5/arch/ppc/kernel/misc.S Mon May 31 10:52:30 2004
+++ linuxppc_2.5-intracom/arch/ppc/kernel/misc.S Mon May 31 17:24:05 2004
@@ -565,10 +565,12 @@
* flush_icache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(flush_icache_range)
+#if !defined(CONFIG_8xx)
mfspr r5,PVR
rlwinm r5,r5,16,16,31
cmpi 0,r5,1
beqlr /* for 601, do nothing */
+#endif
li r5,L1_CACHE_LINE_SIZE-1
andc r3,r3,r5
subf r4,r3,r4
@@ -683,10 +685,12 @@
* void __flush_dcache_icache(void *page)
*/
_GLOBAL(__flush_dcache_icache)
+#if !defined(CONFIG_8xx)
mfspr r5,PVR
rlwinm r5,r5,16,16,31
cmpi 0,r5,1
beqlr /* for 601, do nothing */
+#endif
rlwinm r3,r3,0,0,19 /* Get page base address */
li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */
mtctr r4
@@ -712,10 +716,12 @@
* void __flush_dcache_icache_phys(unsigned long physaddr)
*/
_GLOBAL(__flush_dcache_icache_phys)
+#if !defined(CONFIG_8xx)
mfspr r5,PVR
rlwinm r5,r5,16,16,31
cmpi 0,r5,1
beqlr /* for 601, do nothing */
+#endif
mfmsr r10
rlwinm r0,r10,0,28,26 /* clear DR */
mtmsr r0
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper --exclude=ChangeSet linuxppc_2.5/arch/ppc/mm/init.c linuxppc_2.5-intracom/arch/ppc/mm/init.c
--- linuxppc_2.5/arch/ppc/mm/init.c Mon May 31 10:52:30 2004
+++ linuxppc_2.5-intracom/arch/ppc/mm/init.c Mon May 31 17:24:05 2004
@@ -605,7 +605,6 @@
kunmap(page);
}
-#ifndef update_mmu_cache
/*
* This is called at the end of handling a user page fault, when the
* fault has been handled by updating a PTE in the linux page tables.
@@ -641,6 +640,7 @@
if (!pmd_none(*pmd))
add_hash_page(mm->context, address, pmd_val(*pmd));
}
+#else
+ __tlbia();
#endif
}
-#endif
diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper --exclude=ChangeSet linuxppc_2.5/include/asm-ppc/tlbflush.h linuxppc_2.5-intracom/include/asm-ppc/tlbflush.h
--- linuxppc_2.5/include/asm-ppc/tlbflush.h Mon May 31 10:53:26 2004
+++ linuxppc_2.5-intracom/include/asm-ppc/tlbflush.h Mon May 31 17:24:16 2004
@@ -50,7 +50,8 @@
static inline void flush_tlb_kernel_range(unsigned long start,
unsigned long end)
{ __tlbia(); }
-#define update_mmu_cache(vma, addr, pte) do { } while(0)
+/* #define update_mmu_cache(vma, addr, pte) do { } while(0) */
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
#else /* 6xx, 7xx, 7xxx cpus */
struct mm_struct;
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] fix TLB handling for 8xx on linuxppc-2.5
2004-05-31 14:36 [PATCH] fix TLB handling for 8xx on linuxppc-2.5 Pantelis Antoniou
@ 2004-05-31 22:00 ` Benjamin Herrenschmidt
2004-05-31 22:05 ` Benjamin Herrenschmidt
2004-06-01 6:10 ` Pantelis Antoniou
2004-06-02 15:13 ` Dan Malek
1 sibling, 2 replies; 6+ messages in thread
From: Benjamin Herrenschmidt @ 2004-05-31 22:00 UTC (permalink / raw)
To: Pantelis Antoniou; +Cc: Dan Malek, Tom Rini, Paul Mackerras, Linuxppc-Embedded
On Tue, 2004-06-01 at 00:36, Pantelis Antoniou wrote:
> Hi
>
> The following patch fixes the problems of 8xx with the latest
> linuxppc-2.5 tree.
>
> With it user space progresses properly.
> Lots of gray areas remain and MM handling for 8xx is
> mighty inefficient IMO.
>
> Dan could you please take a look?
Ok, looks a bit weird on the edges.
>
> Pantelis
>
>
> ______________________________________________________________________
> diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper --exclude=ChangeSet linuxppc_2.5/arch/ppc/kernel/head_8xx.S linuxppc_2.5-intracom/arch/ppc/kernel/head_8xx.S
> --- linuxppc_2.5/arch/ppc/kernel/head_8xx.S Mon May 31 10:52:29 2004
> +++ linuxppc_2.5-intracom/arch/ppc/kernel/head_8xx.S Mon May 31 17:24:05 2004
> @@ -157,6 +157,24 @@
> SAVE_2GPRS(7, r11)
>
> /*
> +if ((val & (_PAGE_HWWRITE | _PAGE_RW | _PAGE_DIRTY)) == (_PAGE_RW | _PAGE_DIRTY))
> + val |= _PAGE_HWWRITE;
> +else if ((val & (_PAGE_HWWRITE | _PAGE_RW | _PAGE_DIRTY)) == _PAGE_HWWRITE)
> + val &= ~_PAGE_HWWRITE;
> +*/
I don't like the above. Things should be dealt with differently.
The TLB handler itself should only care about _setting_ _PAGE_HWWRITE I
think when it's missing (oh, and dirty of course). The clearing should
be done on a per-PTE basis in ptep_get_and_clear_*, ptep_clear_*, etc...
along with the necessary TLB invalidate (hrm... can we invalidate
selectively instead of the whole thing ?)
The tlbia in update_mmu_cache() doesn't look good. More like a
workaround for breakage in the implementation.
Paul, any comment ?
Ben.
> +#define LAZY_DTLB_FIX \
> + rlwinm r12,r10,0,23,25; \
> + cmpwi r12,0xc0; \
> + bne+ 0f; \
> + ori r10,r10,0x100; \
> + b 1f; \
> + 0: cmpwi r12,0x100; \
> + bne+ 1f; \
> + rlwinm r10,r10,0,24,22; \
> + 1:
> +
> +/*
> * Note: code which follows this uses cr0.eq (set if from kernel),
> * r11, r12 (SRR0), and r9 (SRR1).
> *
> @@ -348,7 +366,6 @@
> mtspr MD_TWC, r11 /* Load pte table base address */
> mfspr r11, MD_TWC /* ....and get the pte address */
> lwz r10, 0(r11) /* Get the pte */
> -
> ori r10, r10, _PAGE_ACCESSED
> stw r10, 0(r11)
>
> @@ -398,6 +415,7 @@
> mfcr r10
> stw r10, 0(r0)
> stw r11, 4(r0)
> + stw r12, 16(r0)
> mfspr r10, M_TWB /* Get level 1 table entry address */
>
> /* If we are faulting a kernel address, we have to use the
> @@ -440,6 +458,7 @@
> mtspr MD_TWC, r11
>
> mfspr r11, MD_TWC /* get the pte address again */
> + LAZY_DTLB_FIX
> ori r10, r10, _PAGE_ACCESSED
> stw r10, 0(r11)
>
> @@ -463,6 +482,7 @@
> lwz r11, 0(r0)
> mtcr r11
> lwz r11, 4(r0)
> + lwz r12, 16(r0)
> #ifdef CONFIG_8xx_CPU6
> lwz r3, 8(r0)
> #endif
> @@ -472,6 +492,7 @@
> lwz r11, 0(r0)
> mtcr r11
> lwz r11, 4(r0)
> + lwz r12, 16(r0)
> #ifdef CONFIG_8xx_CPU6
> lwz r3, 8(r0)
> #endif
> @@ -505,6 +526,7 @@
> mfcr r10
> stw r10, 0(r0)
> stw r11, 4(r0)
> + stw r12, 16(r0)
>
> /* First, make sure this was a store operation.
> */
> @@ -574,6 +596,7 @@
> */
> ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
> mfspr r11, MD_TWC /* Get pte address again */
> + LAZY_DTLB_FIX
> stw r10, 0(r11) /* and update pte in table */
>
> /* The Linux PTE won't go exactly into the MMU TLB.
> @@ -596,6 +619,7 @@
> lwz r11, 0(r0)
> mtcr r11
> lwz r11, 4(r0)
> + lwz r12, 16(r0)
> #ifdef CONFIG_8xx_CPU6
> lwz r3, 8(r0)
> #endif
> @@ -605,6 +629,7 @@
> lwz r11, 0(r0)
> mtcr r11
> lwz r11, 4(r0)
> + lwz r12, 16(r0)
> #ifdef CONFIG_8xx_CPU6
> lwz r3, 8(r0)
> #endif
> diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper --exclude=ChangeSet linuxppc_2.5/arch/ppc/kernel/misc.S linuxppc_2.5-intracom/arch/ppc/kernel/misc.S
> --- linuxppc_2.5/arch/ppc/kernel/misc.S Mon May 31 10:52:30 2004
> +++ linuxppc_2.5-intracom/arch/ppc/kernel/misc.S Mon May 31 17:24:05 2004
> @@ -565,10 +565,12 @@
> * flush_icache_range(unsigned long start, unsigned long stop)
> */
> _GLOBAL(flush_icache_range)
> +#if !defined(CONFIG_8xx)
> mfspr r5,PVR
> rlwinm r5,r5,16,16,31
> cmpi 0,r5,1
> beqlr /* for 601, do nothing */
> +#endif
> li r5,L1_CACHE_LINE_SIZE-1
> andc r3,r3,r5
> subf r4,r3,r4
> @@ -683,10 +685,12 @@
> * void __flush_dcache_icache(void *page)
> */
> _GLOBAL(__flush_dcache_icache)
> +#if !defined(CONFIG_8xx)
> mfspr r5,PVR
> rlwinm r5,r5,16,16,31
> cmpi 0,r5,1
> beqlr /* for 601, do nothing */
> +#endif
> rlwinm r3,r3,0,0,19 /* Get page base address */
> li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */
> mtctr r4
> @@ -712,10 +716,12 @@
> * void __flush_dcache_icache_phys(unsigned long physaddr)
> */
> _GLOBAL(__flush_dcache_icache_phys)
> +#if !defined(CONFIG_8xx)
> mfspr r5,PVR
> rlwinm r5,r5,16,16,31
> cmpi 0,r5,1
> beqlr /* for 601, do nothing */
> +#endif
> mfmsr r10
> rlwinm r0,r10,0,28,26 /* clear DR */
> mtmsr r0
> diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper --exclude=ChangeSet linuxppc_2.5/arch/ppc/mm/init.c linuxppc_2.5-intracom/arch/ppc/mm/init.c
> --- linuxppc_2.5/arch/ppc/mm/init.c Mon May 31 10:52:30 2004
> +++ linuxppc_2.5-intracom/arch/ppc/mm/init.c Mon May 31 17:24:05 2004
> @@ -605,7 +605,6 @@
> kunmap(page);
> }
>
> -#ifndef update_mmu_cache
> /*
> * This is called at the end of handling a user page fault, when the
> * fault has been handled by updating a PTE in the linux page tables.
> @@ -641,6 +640,7 @@
> if (!pmd_none(*pmd))
> add_hash_page(mm->context, address, pmd_val(*pmd));
> }
> +#else
> + __tlbia();
> #endif
> }
> -#endif
> diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper --exclude=ChangeSet linuxppc_2.5/include/asm-ppc/tlbflush.h linuxppc_2.5-intracom/include/asm-ppc/tlbflush.h
> --- linuxppc_2.5/include/asm-ppc/tlbflush.h Mon May 31 10:53:26 2004
> +++ linuxppc_2.5-intracom/include/asm-ppc/tlbflush.h Mon May 31 17:24:16 2004
> @@ -50,7 +50,8 @@
> static inline void flush_tlb_kernel_range(unsigned long start,
> unsigned long end)
> { __tlbia(); }
> -#define update_mmu_cache(vma, addr, pte) do { } while(0)
> +/* #define update_mmu_cache(vma, addr, pte) do { } while(0) */
> +extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
>
> #else /* 6xx, 7xx, 7xxx cpus */
> struct mm_struct;
--
Benjamin Herrenschmidt <benh@kernel.crashing.org>
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] fix TLB handling for 8xx on linuxppc-2.5
2004-05-31 22:00 ` Benjamin Herrenschmidt
@ 2004-05-31 22:05 ` Benjamin Herrenschmidt
2004-06-01 6:10 ` Pantelis Antoniou
1 sibling, 0 replies; 6+ messages in thread
From: Benjamin Herrenschmidt @ 2004-05-31 22:05 UTC (permalink / raw)
To: Pantelis Antoniou; +Cc: Dan Malek, Tom Rini, Paul Mackerras, Linuxppc-Embedded
> I don't like the above. Things should be dealt with differently.
>
> The TLB handler itself should only care about _setting_ _PAGE_HWWRITE I
> think when it's missing (oh, and dirty of course). The clearing should
> be done on a per-PTE basis in ptep_get_and_clear_*, ptep_clear_*, etc...
> along with the necessary TLB invalidate (hrm... can we invalidate
> selectively instead of the whole thing ?)
Actually... I think the various flush_tlb_* calls should be enough on
those CPUs anyway...
> The tlbia in update_mmu_cache() doesn't look good. More like a
> workaround for breakage in the implementation.
>
> Paul, any comment ?
>
> Ben.
>
> > +#define LAZY_DTLB_FIX \
> > + rlwinm r12,r10,0,23,25; \
> > + cmpwi r12,0xc0; \
> > + bne+ 0f; \
> > + ori r10,r10,0x100; \
> > + b 1f; \
> > + 0: cmpwi r12,0x100; \
> > + bne+ 1f; \
> > + rlwinm r10,r10,0,24,22; \
> > + 1:
> > +
> > +/*
> > * Note: code which follows this uses cr0.eq (set if from kernel),
> > * r11, r12 (SRR0), and r9 (SRR1).
> > *
> > @@ -348,7 +366,6 @@
> > mtspr MD_TWC, r11 /* Load pte table base address */
> > mfspr r11, MD_TWC /* ....and get the pte address */
> > lwz r10, 0(r11) /* Get the pte */
> > -
> > ori r10, r10, _PAGE_ACCESSED
> > stw r10, 0(r11)
> >
> > @@ -398,6 +415,7 @@
> > mfcr r10
> > stw r10, 0(r0)
> > stw r11, 4(r0)
> > + stw r12, 16(r0)
> > mfspr r10, M_TWB /* Get level 1 table entry address */
> >
> > /* If we are faulting a kernel address, we have to use the
> > @@ -440,6 +458,7 @@
> > mtspr MD_TWC, r11
> >
> > mfspr r11, MD_TWC /* get the pte address again */
> > + LAZY_DTLB_FIX
> > ori r10, r10, _PAGE_ACCESSED
> > stw r10, 0(r11)
> >
> > @@ -463,6 +482,7 @@
> > lwz r11, 0(r0)
> > mtcr r11
> > lwz r11, 4(r0)
> > + lwz r12, 16(r0)
> > #ifdef CONFIG_8xx_CPU6
> > lwz r3, 8(r0)
> > #endif
> > @@ -472,6 +492,7 @@
> > lwz r11, 0(r0)
> > mtcr r11
> > lwz r11, 4(r0)
> > + lwz r12, 16(r0)
> > #ifdef CONFIG_8xx_CPU6
> > lwz r3, 8(r0)
> > #endif
> > @@ -505,6 +526,7 @@
> > mfcr r10
> > stw r10, 0(r0)
> > stw r11, 4(r0)
> > + stw r12, 16(r0)
> >
> > /* First, make sure this was a store operation.
> > */
> > @@ -574,6 +596,7 @@
> > */
> > ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
> > mfspr r11, MD_TWC /* Get pte address again */
> > + LAZY_DTLB_FIX
> > stw r10, 0(r11) /* and update pte in table */
> >
> > /* The Linux PTE won't go exactly into the MMU TLB.
> > @@ -596,6 +619,7 @@
> > lwz r11, 0(r0)
> > mtcr r11
> > lwz r11, 4(r0)
> > + lwz r12, 16(r0)
> > #ifdef CONFIG_8xx_CPU6
> > lwz r3, 8(r0)
> > #endif
> > @@ -605,6 +629,7 @@
> > lwz r11, 0(r0)
> > mtcr r11
> > lwz r11, 4(r0)
> > + lwz r12, 16(r0)
> > #ifdef CONFIG_8xx_CPU6
> > lwz r3, 8(r0)
> > #endif
> > diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper --exclude=ChangeSet linuxppc_2.5/arch/ppc/kernel/misc.S linuxppc_2.5-intracom/arch/ppc/kernel/misc.S
> > --- linuxppc_2.5/arch/ppc/kernel/misc.S Mon May 31 10:52:30 2004
> > +++ linuxppc_2.5-intracom/arch/ppc/kernel/misc.S Mon May 31 17:24:05 2004
> > @@ -565,10 +565,12 @@
> > * flush_icache_range(unsigned long start, unsigned long stop)
> > */
> > _GLOBAL(flush_icache_range)
> > +#if !defined(CONFIG_8xx)
> > mfspr r5,PVR
> > rlwinm r5,r5,16,16,31
> > cmpi 0,r5,1
> > beqlr /* for 601, do nothing */
> > +#endif
> > li r5,L1_CACHE_LINE_SIZE-1
> > andc r3,r3,r5
> > subf r4,r3,r4
> > @@ -683,10 +685,12 @@
> > * void __flush_dcache_icache(void *page)
> > */
> > _GLOBAL(__flush_dcache_icache)
> > +#if !defined(CONFIG_8xx)
> > mfspr r5,PVR
> > rlwinm r5,r5,16,16,31
> > cmpi 0,r5,1
> > beqlr /* for 601, do nothing */
> > +#endif
> > rlwinm r3,r3,0,0,19 /* Get page base address */
> > li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */
> > mtctr r4
> > @@ -712,10 +716,12 @@
> > * void __flush_dcache_icache_phys(unsigned long physaddr)
> > */
> > _GLOBAL(__flush_dcache_icache_phys)
> > +#if !defined(CONFIG_8xx)
> > mfspr r5,PVR
> > rlwinm r5,r5,16,16,31
> > cmpi 0,r5,1
> > beqlr /* for 601, do nothing */
> > +#endif
> > mfmsr r10
> > rlwinm r0,r10,0,28,26 /* clear DR */
> > mtmsr r0
> > diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper --exclude=ChangeSet linuxppc_2.5/arch/ppc/mm/init.c linuxppc_2.5-intracom/arch/ppc/mm/init.c
> > --- linuxppc_2.5/arch/ppc/mm/init.c Mon May 31 10:52:30 2004
> > +++ linuxppc_2.5-intracom/arch/ppc/mm/init.c Mon May 31 17:24:05 2004
> > @@ -605,7 +605,6 @@
> > kunmap(page);
> > }
> >
> > -#ifndef update_mmu_cache
> > /*
> > * This is called at the end of handling a user page fault, when the
> > * fault has been handled by updating a PTE in the linux page tables.
> > @@ -641,6 +640,7 @@
> > if (!pmd_none(*pmd))
> > add_hash_page(mm->context, address, pmd_val(*pmd));
> > }
> > +#else
> > + __tlbia();
> > #endif
> > }
> > -#endif
> > diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper --exclude=ChangeSet linuxppc_2.5/include/asm-ppc/tlbflush.h linuxppc_2.5-intracom/include/asm-ppc/tlbflush.h
> > --- linuxppc_2.5/include/asm-ppc/tlbflush.h Mon May 31 10:53:26 2004
> > +++ linuxppc_2.5-intracom/include/asm-ppc/tlbflush.h Mon May 31 17:24:16 2004
> > @@ -50,7 +50,8 @@
> > static inline void flush_tlb_kernel_range(unsigned long start,
> > unsigned long end)
> > { __tlbia(); }
> > -#define update_mmu_cache(vma, addr, pte) do { } while(0)
> > +/* #define update_mmu_cache(vma, addr, pte) do { } while(0) */
> > +extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
> >
> > #else /* 6xx, 7xx, 7xxx cpus */
> > struct mm_struct;
--
Benjamin Herrenschmidt <benh@kernel.crashing.org>
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] fix TLB handling for 8xx on linuxppc-2.5
2004-05-31 22:00 ` Benjamin Herrenschmidt
2004-05-31 22:05 ` Benjamin Herrenschmidt
@ 2004-06-01 6:10 ` Pantelis Antoniou
1 sibling, 0 replies; 6+ messages in thread
From: Pantelis Antoniou @ 2004-06-01 6:10 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Dan Malek, Tom Rini, Paul Mackerras, Linuxppc-Embedded
Benjamin Herrenschmidt wrote:
>On Tue, 2004-06-01 at 00:36, Pantelis Antoniou wrote:
>
>>Hi
>>
>>The following patch fixes the problems of 8xx with the latest
>>linuxppc-2.5 tree.
>>
>>With it user space progresses properly.
>>Lots of gray areas remain and MM handling for 8xx is
>>mighty inefficient IMO.
>>
>>Dan could you please take a look?
>>
>
>Ok, looks a bit weird on the edges.
>
>
I agree :)
>>Pantelis
>>
>>
>>______________________________________________________________________
>>diff -Nur --exclude=RCS --exclude=CVS --exclude=SCCS --exclude=BitKeeper --exclude=ChangeSet linuxppc_2.5/arch/ppc/kernel/head_8xx.S linuxppc_2.5-intracom/arch/ppc/kernel/head_8xx.S
>>--- linuxppc_2.5/arch/ppc/kernel/head_8xx.S Mon May 31 10:52:29 2004
>>+++ linuxppc_2.5-intracom/arch/ppc/kernel/head_8xx.S Mon May 31 17:24:05 2004
>>@@ -157,6 +157,24 @@
>> SAVE_2GPRS(7, r11)
>>
>> /*
>>+if ((val & (_PAGE_HWWRITE | _PAGE_RW | _PAGE_DIRTY)) == (_PAGE_RW | _PAGE_DIRTY))
>>+ val |= _PAGE_HWWRITE;
>>+else if ((val & (_PAGE_HWWRITE | _PAGE_RW | _PAGE_DIRTY)) == _PAGE_HWWRITE)
>>+ val &= ~_PAGE_HWWRITE;
>>+*/
>>
>
>I don't like the above. Things should be dealt with differently.
>
>The TLB handler itself should only care about _setting_ _PAGE_HWWRITE I
>think when it's missing (oh, and dirty of course). The clearing should
>be done on a per-PTE basis in ptep_get_and_clear_*, ptep_clear_*, etc...
>along with the necessary TLB invalidate (hrm... can we invalidate
>selectively instead of the whole thing ?)
>
Just setting HWWRITE is simple.
>
>The tlbia in update_mmu_cache() doesn't look good. More like a
>workaround for breakage in the implementation.
>
It is :)
When I tried a selective TLB invalidate it crashed
in a spectacular way.
That lazy TLB stuff just gave the mm system a good shake and
it came apart.
>
>Paul, any comment ?
>
>Ben.
>
>
Regards
Pantelis
P.S.
Perusing the headers I came across a comment that said swap is
broken on 8xx. For some reason I need to fix it.
Where can I go about looking?
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] fix TLB handling for 8xx on linuxppc-2.5
2004-05-31 14:36 [PATCH] fix TLB handling for 8xx on linuxppc-2.5 Pantelis Antoniou
2004-05-31 22:00 ` Benjamin Herrenschmidt
@ 2004-06-02 15:13 ` Dan Malek
1 sibling, 0 replies; 6+ messages in thread
From: Dan Malek @ 2004-06-02 15:13 UTC (permalink / raw)
To: Pantelis Antoniou
Cc: Benjamin Herrenschmidt, Tom Rini, Paul Mackerras,
Linuxppc-Embedded
On May 31, 2004, at 10:36 AM, Pantelis Antoniou wrote:
> +#define LAZY_DTLB_FIX \
> + rlwinm r12,r10,0,23,25; \
> + cmpwi r12,0xc0; \
> + bne+ 0f; \
> + ori r10,r10,0x100; \
> + b 1f; \
> + 0: cmpwi r12,0x100; \
> + bne+ 1f; \
> + rlwinm r10,r10,0,24,22; \
> + 1:
> +
This shouldn't be necessary. The TLB handler manages dirty/used
flags already. There is absolutely no need for testing/branching like
this in the TLB handlers. Simply getting the exception and the flow
through the handler will imply the states that need to be cleared or
set.
I'll look into this further.
Thanks.
-- Dan
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 6+ messages in thread
[parent not found: <20040601070415.E13F6C109F@atlas.denx.de>]
* Re: [PATCH] fix TLB handling for 8xx on linuxppc-2.5
[not found] <20040601070415.E13F6C109F@atlas.denx.de>
@ 2004-06-01 7:04 ` Pantelis Antoniou
0 siblings, 0 replies; 6+ messages in thread
From: Pantelis Antoniou @ 2004-06-01 7:04 UTC (permalink / raw)
To: Wolfgang Denk; +Cc: Linuxppc-Embedded
Wolfgang Denk wrote:
>In message <40BC1DBF.6050108@intracom.gr> you wrote:
>
>>Perusing the headers I came across a comment that said swap is
>>broken on 8xx. For some reason I need to fix it.
>>Where can I go about looking?
>>
>
>If a 2.4 kernel is good enough:
>
:)
Thanks
>
>Index: include/asm-ppc/pgtable.h
>===================================================================
>RCS file: /cvsroot/linuxppc_2_4_devel/include/asm-ppc/pgtable.h,v
>retrieving revision 1.6
>retrieving revision 1.7
>diff -u -r1.6 -r1.7
>--- include/asm-ppc/pgtable.h 11 Mar 2003 19:53:02 -0000 1.6
>+++ include/asm-ppc/pgtable.h 24 Aug 2003 13:58:59 -0000 1.7
>@@ -686,11 +686,11 @@
> * must not include the _PAGE_PRESENT bit, or the _PAGE_HASHPTE bit
> * (if used). -- paulus
> */
>-#define SWP_TYPE(entry) ((entry).val & 0x3f)
>-#define SWP_OFFSET(entry) ((entry).val >> 6)
>-#define SWP_ENTRY(type, offset) ((swp_entry_t) { (type) | ((offset) << 6) })
>-#define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 })
>-#define swp_entry_to_pte(x) ((pte_t) { (x).val << 2 })
>+#define SWP_TYPE(entry) (((entry).val >> 1) & 0x3f)
>+#define SWP_OFFSET(entry) ((entry).val >> 8)
>+#define SWP_ENTRY(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
>+#define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) & ~0x81 })
>+#define swp_entry_to_pte(x) ((pte_t) { (x).val })
>
> /* CONFIG_APUS */
> /* For virtual address to physical address conversion */
>
>Best regards,
>
>Wolfgang Denk
>
>
Regards
Pantelis
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2004-06-02 15:13 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2004-05-31 14:36 [PATCH] fix TLB handling for 8xx on linuxppc-2.5 Pantelis Antoniou
2004-05-31 22:00 ` Benjamin Herrenschmidt
2004-05-31 22:05 ` Benjamin Herrenschmidt
2004-06-01 6:10 ` Pantelis Antoniou
2004-06-02 15:13 ` Dan Malek
[not found] <20040601070415.E13F6C109F@atlas.denx.de>
2004-06-01 7:04 ` Pantelis Antoniou
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