From mboxrd@z Thu Jan  1 00:00:00 1970
Subject: Re: [PATCH] Workaround for 745x data corruption bug
From: Adrian Cox <adrian@humboldt.co.uk>
To: "Mark A. Greer" <mgreer@mvista.com>
Cc: Brian Waite <linwoes@gmail.com>, linuxppc-dev@lists.linuxppc.org
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Date: Wed, 04 Aug 2004 21:39:24 +0100
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On Wed, 2004-08-04 at 18:55, Mark A. Greer wrote:
> 1) M=1 is only necessary in an SMP environment (or for the 745x erratum).

And the reason we have to turn it on for the MPC10x bridges is that they
contain their own cache. Even though it only has two cache lines, it has
to be treated as a second processor for coherence purposes.

- Adrian Cox
Humboldt Solutions Ltd.


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