From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Sven Luther <sven.luther@wanadoo.fr>
Cc: linuxppc-dev list <linuxppc-dev@ozlabs.org>
Subject: Re: status of the G4 l2 cache flush and MSR errate patch
Date: Thu, 13 Jan 2005 01:33:05 +0100 [thread overview]
Message-ID: <1105576385.6021.2.camel@gaston> (raw)
In-Reply-To: <20050109123515.GC17561@pegasos>
> Mmm, well, i am not really the author of this one. Jacob Pan from freescale is
> the author, so we should change this, will do. So this should show :
>
> ## DP: Patch author: Pan Jacob-r7aahq <Jacob.Pan@freescale.com>
> > ## DP: Upstream status: under review by benh.
>
> The patch does two things. Use hardware assist for cache flush, which seems to
> be ok on 744x processors, but broken on earlier G4s and G3s. And add a printk
> in case of some exception, so the user knows about it instead of it being
> silently discarded.
The HW assist isn't completely ok neither... it should be enough for
enabling the cache at boot though. I've been banging my head lately
trying to get a properly working & reliable cache flush mecanism for use
on the Mac laptops since we need that for cpufreq and sleep on various
models, but what I have right now is just a "works most of the time"
kind of implementation.
> I was under the impression that benh said that the patch was ok, but not
> really relevant, since it applies to code travel cases which either are not
> really used in the common case, or result in a dying of the kernel anyway.
> Don't remember all the details though. They do respond to some G4 processor
> errata's though.
I'll have a look again. Just back from vacation, leave me a coupe of
days to catch up with everything and I'll take care of those.
Ben.
prev parent reply other threads:[~2005-01-13 0:33 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-01-09 11:57 status of the G4 l2 cache flush and MSR errate patch Christoph Hellwig
2005-01-09 12:35 ` Sven Luther
2005-01-13 0:33 ` Benjamin Herrenschmidt [this message]
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