#### Auto-generated patch ####
Date:        Tue, 22 Mar 2005 15:23:34 -0500
Maintainer:  Jason McMullan <jmcmullan@timesys.com>
Summary:     Freescale CPM2 device I/O processor, on MPC8xx and MPC8xxx CPUs
Description: Freescale CPM2 device I/O processor, on MPC8xx and MPC8xxx CPUs
###############################

Index of changes:

 arch/ppc/platforms/85xx/mpc8560_ads.c |    4 -
 arch/ppc/syslib/cpm2_common.c         |    4 -
 arch/ppc/syslib/cpm2_pic.c            |   69 ++++++++++++++++++----
 arch/ppc/syslib/cpm2_pic.h            |    3 
 arch/ppc/syslib/m8260_setup.c         |    5 -
 include/asm-ppc/cpm2.h                |   23 ++++++-
 include/asm-ppc/irq.h                 |  105 +++++++++++++++++-----------------
 7 files changed, 138 insertions(+), 75 deletions(-)


--- linux-orig/arch/ppc/platforms/85xx/mpc8560_ads.c
+++ linux/arch/ppc/platforms/85xx/mpc8560_ads.c
@@ -135,7 +135,6 @@
 static void __init
 mpc8560_ads_init_IRQ(void)
 {
-	int i;
 	volatile cpm2_map_t *immap = cpm2_immr;
 
 	/* Setup OpenPIC */
@@ -145,8 +144,7 @@
 	immap->im_intctl.ic_simrh = 0x0;
 	immap->im_intctl.ic_simrl = 0x0;
 
-	for (i = CPM_IRQ_OFFSET; i < (NR_CPM_INTS + CPM_IRQ_OFFSET); i++)
-		irq_desc[i].handler = &cpm2_pic;
+        cpm2_init_IRQ();
 
 	/* Initialize the default interrupt mapping priorities,
 	 * in case the boot rom changed something on us.
--- linux-orig/arch/ppc/syslib/cpm2_common.c
+++ linux/arch/ppc/syslib/cpm2_common.c
@@ -32,12 +32,12 @@
 #include <asm/rheap.h>
 
 static void cpm2_dpinit(void);
-cpm_cpm2_t	*cpmp;		/* Pointer to comm processor space */
+volatile cpm_cpm2_t     *cpmp;          /* Pointer to comm processor space */
 
 /* We allocate this here because it is used almost exclusively for
  * the communication processor devices.
  */
-cpm2_map_t *cpm2_immr;
+volatile cpm2_map_t *cpm2_immr;
 
 #define CPM_MAP_SIZE	(0x40000)	/* 256k - the PQ3 reserve this amount
 					   of space for CPM as it is larger
--- linux-orig/arch/ppc/syslib/cpm2_pic.c
+++ linux/arch/ppc/syslib/cpm2_pic.c
@@ -100,20 +100,29 @@
 	}
 }
 
-struct hw_interrupt_type cpm2_pic = {
-	" CPM2 SIU  ",
-	NULL,
-	NULL,
-	cpm2_unmask_irq,
-	cpm2_mask_irq,
-	cpm2_mask_and_ack,
-	cpm2_end_irq,
-	0
+static unsigned int cpm2_startup_irq(unsigned int irq)
+{
+	cpm2_unmask_irq(irq);
+	return 0;
+}
+
+static void cpm2_shutdown_irq(unsigned int irq)
+{
+	cpm2_mask_irq(irq);
+}
+
+
+static struct hw_interrupt_type cpm2_pic = {
+	.typename = "CPM2 SIU",
+	.startup = cpm2_startup_irq,
+	.shutdown = cpm2_shutdown_irq,
+	.enable = cpm2_unmask_irq,
+	.disable = cpm2_mask_irq,
+	.ack = cpm2_mask_and_ack,
+	.end = cpm2_end_irq,
 };
 
-
-int
-cpm2_get_irq(struct pt_regs *regs)
+int cpm2_get_irq(struct pt_regs *regs)
 {
 	int irq;
         unsigned long bits;
@@ -125,5 +134,39 @@
 
 	if (irq == 0)
 		return(-1);
-	return irq;
+	return irq+CPM_IRQ_OFFSET;
+}
+
+#ifndef SA_NOTHREAD
+#define SA_NOTHREAD 0
+#endif
+
+void cpm2_init_IRQ(void)
+{
+	int i;
+
+	/* Clear the CPM IRQ controller, in case it has any bits set
+	 * from the bootloader
+	 */
+
+	/* Mask out everything */
+	cpm2_immr->im_intctl.ic_simrh = 0x00000000;
+	cpm2_immr->im_intctl.ic_simrl = 0x00000000;
+	wmb();
+
+	/* Ack everything */
+	cpm2_immr->im_intctl.ic_sipnrh = 0xffffffff;
+	cpm2_immr->im_intctl.ic_sipnrl = 0xffffffff;
+	wmb();
+
+	/* Dummy read of the vector */
+	i = cpm2_immr->im_intctl.ic_sivec;
+	rmb();
+
+	/* Enable chaining to OpenPIC, and make everything level
+	 */
+	for (i = 0; i < NR_CPM_INTS; i++) {
+		irq_desc[i+CPM_IRQ_OFFSET].handler = &cpm2_pic;
+		irq_desc[i+CPM_IRQ_OFFSET].status |= IRQ_LEVEL;
+	}
 }
--- linux-orig/arch/ppc/syslib/cpm2_pic.h
+++ linux/arch/ppc/syslib/cpm2_pic.h
@@ -1,7 +1,8 @@
 #ifndef _PPC_KERNEL_CPM2_H
 #define _PPC_KERNEL_CPM2_H
 
-extern struct hw_interrupt_type cpm2_pic;
 extern int cpm2_get_irq(struct pt_regs *regs);
 
+extern void cpm2_init_IRQ(void);
+
 #endif /* _PPC_KERNEL_CPM2_H */
--- linux-orig/arch/ppc/syslib/m8260_setup.c
+++ linux/arch/ppc/syslib/m8260_setup.c
@@ -168,10 +168,7 @@
 static void __init
 m8260_init_IRQ(void)
 {
-	int i;
-
-        for ( i = 0 ; i < NR_SIU_INTS ; i++ )
-                irq_desc[i].handler = &cpm2_pic;
+	cpm2_init_IRQ();
 
 	/* Initialize the default interrupt mapping priorities,
 	 * in case the boot rom changed something on us.
--- linux-orig/include/asm-ppc/cpm2.h
+++ linux/include/asm-ppc/cpm2.h
@@ -69,13 +69,14 @@
 #define CPM_CR_INIT_TX		((ushort)0x0002)
 #define CPM_CR_HUNT_MODE	((ushort)0x0003)
 #define CPM_CR_STOP_TX		((ushort)0x0004)
+#define CPM_CR_GRA_STOP_TX      ((ushort)0x0005)
 #define CPM_CR_RESTART_TX	((ushort)0x0006)
 #define CPM_CR_SET_GADDR	((ushort)0x0008)
 #define CPM_CR_START_IDMA	((ushort)0x0009)
 #define CPM_CR_STOP_IDMA	((ushort)0x000b)
 
 #define mk_cr_cmd(PG, SBC, MCN, OP) \
-	((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
+	(((PG) << 26) | ((SBC) << 21) | ((MCN) << 6) | (OP))
 
 /* Dual Port RAM addresses.  The first 16K is available for almost
  * any CPM use, so we put the BDs there.  The first 128 bytes are
@@ -107,7 +108,7 @@
 /* Export the base address of the communication processor registers
  * and dual port ram.
  */
-extern		cpm_cpm2_t	*cpmp;	 /* Pointer to comm processor */
+extern volatile	cpm_cpm2_t	*cpmp;	 /* Pointer to comm processor */
 extern uint cpm_dpalloc(uint size, uint align);
 extern int cpm_dpfree(uint offset);
 extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align);
@@ -115,7 +116,24 @@
 extern void *cpm_dpram_addr(uint offset);
 extern void cpm_setbrg(uint brg, uint rate);
 extern void cpm2_fastbrg(uint brg, uint rate, int div16);
+extern void cpm2_reset(void);
+
+#ifdef CONFIG_CPM2
+#define CPM_CP_FCC(line, mcn)	mk_cr_cmd(CPM_CR_FCC1_PAGE+(line),CPM_CR_FCC1_SBLOCK+(line), mcn, 0)
+#define CPM_CP_SCC(line)	mk_cr_cmd(CPM_CR_SCC1_PAGE+(line),CPM_CR_SCC1_SBLOCK+(line), 0, 0)
+#define CPM_CP_SMC(line)	mk_cr_cmd(CPM_CR_SMC1_PAGE+(line),CPM_CR_SMC1_SBLOCK+(line), 0, 0)
+#define CPM_CP_I2C		mk_cr_cmd(CPM_CR_I2C_PAGE,CPM_CR_I2C_SBLOCK, 0, 0)
 
+static inline void cpm_cp_command(uint32_t id, int op)
+{
+	cpmp->cp_cpcr = id | op | CPM_CR_FLG;
+
+	while (cpmp->cp_cpcr & CPM_CR_FLG);
+}
+#else
+#error Please define cpm_cp_command and the CPM_CP_* ids you will need.
+#endif
+
 /* Buffer descriptors used by many of the CPM protocols.
 */
 typedef struct cpm_buf_desc {
@@ -135,6 +153,7 @@
 #define BD_SC_BR	((ushort)0x0020)	/* Break received */
 #define BD_SC_FR	((ushort)0x0010)	/* Framing error */
 #define BD_SC_PR	((ushort)0x0008)	/* Parity error */
+#define BD_SC_NAK	((ushort)0x0004)	/* NAK - did not respond */
 #define BD_SC_OV	((ushort)0x0002)	/* Overrun */
 #define BD_SC_CD	((ushort)0x0001)	/* ?? */
 
--- linux-orig/include/asm-ppc/irq.h
+++ linux/include/asm-ppc/irq.h
@@ -257,57 +257,62 @@
  * (Document errata updates have fixed this...make sure you have up to
  * date processor documentation -- Dan).
  */
-#define NR_SIU_INTS	64
+
+#ifndef CPM_IRQ_OFFSET
+#define CPM_IRQ_OFFSET	0
+#endif
+
+#define NR_CPM_INTS	64
 
-#define	SIU_INT_ERROR		((uint)0x00)
-#define	SIU_INT_I2C		((uint)0x01)
-#define	SIU_INT_SPI		((uint)0x02)
-#define	SIU_INT_RISC		((uint)0x03)
-#define	SIU_INT_SMC1		((uint)0x04)
-#define	SIU_INT_SMC2		((uint)0x05)
-#define	SIU_INT_IDMA1		((uint)0x06)
-#define	SIU_INT_IDMA2		((uint)0x07)
-#define	SIU_INT_IDMA3		((uint)0x08)
-#define	SIU_INT_IDMA4		((uint)0x09)
-#define	SIU_INT_SDMA		((uint)0x0a)
-#define	SIU_INT_TIMER1		((uint)0x0c)
-#define	SIU_INT_TIMER2		((uint)0x0d)
-#define	SIU_INT_TIMER3		((uint)0x0e)
-#define	SIU_INT_TIMER4		((uint)0x0f)
-#define	SIU_INT_TMCNT		((uint)0x10)
-#define	SIU_INT_PIT		((uint)0x11)
-#define	SIU_INT_IRQ1		((uint)0x13)
-#define	SIU_INT_IRQ2		((uint)0x14)
-#define	SIU_INT_IRQ3		((uint)0x15)
-#define	SIU_INT_IRQ4		((uint)0x16)
-#define	SIU_INT_IRQ5		((uint)0x17)
-#define	SIU_INT_IRQ6		((uint)0x18)
-#define	SIU_INT_IRQ7		((uint)0x19)
-#define	SIU_INT_FCC1		((uint)0x20)
-#define	SIU_INT_FCC2		((uint)0x21)
-#define	SIU_INT_FCC3		((uint)0x22)
-#define	SIU_INT_MCC1		((uint)0x24)
-#define	SIU_INT_MCC2		((uint)0x25)
-#define	SIU_INT_SCC1		((uint)0x28)
-#define	SIU_INT_SCC2		((uint)0x29)
-#define	SIU_INT_SCC3		((uint)0x2a)
-#define	SIU_INT_SCC4		((uint)0x2b)
-#define	SIU_INT_PC15		((uint)0x30)
-#define	SIU_INT_PC14		((uint)0x31)
-#define	SIU_INT_PC13		((uint)0x32)
-#define	SIU_INT_PC12		((uint)0x33)
-#define	SIU_INT_PC11		((uint)0x34)
-#define	SIU_INT_PC10		((uint)0x35)
-#define	SIU_INT_PC9		((uint)0x36)
-#define	SIU_INT_PC8		((uint)0x37)
-#define	SIU_INT_PC7		((uint)0x38)
-#define	SIU_INT_PC6		((uint)0x39)
-#define	SIU_INT_PC5		((uint)0x3a)
-#define	SIU_INT_PC4		((uint)0x3b)
-#define	SIU_INT_PC3		((uint)0x3c)
-#define	SIU_INT_PC2		((uint)0x3d)
-#define	SIU_INT_PC1		((uint)0x3e)
-#define	SIU_INT_PC0		((uint)0x3f)
+#define	SIU_INT_ERROR		((uint)0x00 + CPM_IRQ_OFFSET)
+#define	SIU_INT_I2C		((uint)0x01 + CPM_IRQ_OFFSET)
+#define	SIU_INT_SPI		((uint)0x02 + CPM_IRQ_OFFSET)
+#define	SIU_INT_RISC		((uint)0x03 + CPM_IRQ_OFFSET)
+#define	SIU_INT_SMC1		((uint)0x04 + CPM_IRQ_OFFSET)
+#define	SIU_INT_SMC2		((uint)0x05 + CPM_IRQ_OFFSET)
+#define	SIU_INT_IDMA1		((uint)0x06 + CPM_IRQ_OFFSET)
+#define	SIU_INT_IDMA2		((uint)0x07 + CPM_IRQ_OFFSET)
+#define	SIU_INT_IDMA3		((uint)0x08 + CPM_IRQ_OFFSET)
+#define	SIU_INT_IDMA4		((uint)0x09 + CPM_IRQ_OFFSET)
+#define	SIU_INT_SDMA		((uint)0x0a + CPM_IRQ_OFFSET)
+#define	SIU_INT_TIMER1		((uint)0x0c + CPM_IRQ_OFFSET)
+#define	SIU_INT_TIMER2		((uint)0x0d + CPM_IRQ_OFFSET)
+#define	SIU_INT_TIMER3		((uint)0x0e + CPM_IRQ_OFFSET)
+#define	SIU_INT_TIMER4		((uint)0x0f + CPM_IRQ_OFFSET)
+#define	SIU_INT_TMCNT		((uint)0x10 + CPM_IRQ_OFFSET)
+#define	SIU_INT_PIT		((uint)0x11 + CPM_IRQ_OFFSET)
+#define	SIU_INT_IRQ1		((uint)0x13 + CPM_IRQ_OFFSET)
+#define	SIU_INT_IRQ2		((uint)0x14 + CPM_IRQ_OFFSET)
+#define	SIU_INT_IRQ3		((uint)0x15 + CPM_IRQ_OFFSET)
+#define	SIU_INT_IRQ4		((uint)0x16 + CPM_IRQ_OFFSET)
+#define	SIU_INT_IRQ5		((uint)0x17 + CPM_IRQ_OFFSET)
+#define	SIU_INT_IRQ6		((uint)0x18 + CPM_IRQ_OFFSET)
+#define	SIU_INT_IRQ7		((uint)0x19 + CPM_IRQ_OFFSET)
+#define	SIU_INT_FCC1		((uint)0x20 + CPM_IRQ_OFFSET)
+#define	SIU_INT_FCC2		((uint)0x21 + CPM_IRQ_OFFSET)
+#define	SIU_INT_FCC3		((uint)0x22 + CPM_IRQ_OFFSET)
+#define	SIU_INT_MCC1		((uint)0x24 + CPM_IRQ_OFFSET)
+#define	SIU_INT_MCC2		((uint)0x25 + CPM_IRQ_OFFSET)
+#define	SIU_INT_SCC1		((uint)0x28 + CPM_IRQ_OFFSET)
+#define	SIU_INT_SCC2		((uint)0x29 + CPM_IRQ_OFFSET)
+#define	SIU_INT_SCC3		((uint)0x2a + CPM_IRQ_OFFSET)
+#define	SIU_INT_SCC4		((uint)0x2b + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC15		((uint)0x30 + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC14		((uint)0x31 + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC13		((uint)0x32 + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC12		((uint)0x33 + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC11		((uint)0x34 + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC10		((uint)0x35 + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC9		((uint)0x36 + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC8		((uint)0x37 + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC7		((uint)0x38 + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC6		((uint)0x39 + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC5		((uint)0x3a + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC4		((uint)0x3b + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC3		((uint)0x3c + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC2		((uint)0x3d + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC1		((uint)0x3e + CPM_IRQ_OFFSET)
+#define	SIU_INT_PC0		((uint)0x3f + CPM_IRQ_OFFSET)
 
 #endif /* CONFIG_8260 */