From: Jason McMullan <jason.mcmullan@timesys.com>
To: linuxppc-embedded <linuxppc-embedded@ozlabs.org>
Subject: [PATCH] MPC85xx CDS - Time Of Day, Cache settings, CPM IRQs
Date: Tue, 22 Mar 2005 15:47:44 -0500 [thread overview]
Message-ID: <1111524464.2987.69.camel@ad.doubleclick.net> (raw)
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Some minor fixes for:
MPC85xx CDS Time of Day Clock
/proc/cpuinfo shows cache settings
CPM IRQs are allocated more sanely.
--
Jason McMullan <jason.mcmullan@timesys.com>
TimeSys Corporation
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#### Auto-generated patch ####
Date: Tue, 22 Mar 2005 15:44:01 -0500
Maintainer: Jason McMullan <jmcmullan@timesys.com>
Summary: Freescale MPC85xx CDS series eval boards
###############################
--- linux-orig/arch/ppc/platforms/85xx/Kconfig
+++ linux/arch/ppc/platforms/85xx/Kconfig
@@ -22,9 +22,10 @@
This option enables support for the MPC 8540 ADS evaluation board.
config MPC8555_CDS
- bool "Freescale MPC8555 CDS"
+ bool "Freescale MPC8555/MPC8541 CDS"
help
- This option enablese support for the MPC8555 CDS evaluation board.
+ This option enables support for the MPC8555/MPC8541 CDS
+ evaluation boards.
config MPC8560_ADS
bool "Freescale MPC8560 ADS"
--- linux-orig/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
+++ linux/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
@@ -39,6 +39,7 @@
#include <asm/page.h>
#include <asm/atomic.h>
#include <asm/time.h>
+#include <asm/todc.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/prom.h>
@@ -63,6 +64,10 @@
unsigned long isa_mem_base = 0;
#endif
+#ifdef CONFIG_CPM2
+extern void cpm2_reset(void);
+#endif
+
extern unsigned long total_memory; /* in mm/init */
unsigned char __res[sizeof (bd_t)];
@@ -158,31 +163,27 @@
/* Display the amount of memory */
seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+ /* Display the cache settings */
+ seq_printf(m, "L1 D-cache\t: %s\n",(mfspr(SPRN_L1CSR0)&1) ? "on" : "off");
+ seq_printf(m, "L1 I-cache\t: %s\n",(mfspr(SPRN_L1CSR1)&1) ? "on" : "off");
+ {
+ struct ccsr_l2cache *l2cache;
+ l2cache = ioremap(CCSRBAR+0x20000, sizeof(struct ccsr_l2cache));
+
+ seq_printf(m, "L2 cache\t: %s\n",(l2cache->l2ctl & 0x80000000) ? "on" : "off");
+ iounmap(l2cache);
+ }
+ seq_printf(m, "BPU cache\t: %s\n",(mfspr(SPRN_BUCSR)&1) ? "on" : "off");
+
return 0;
}
-#ifdef CONFIG_CPM2
-static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
-{
- while((irq = cpm2_get_irq(regs)) >= 0)
- __do_IRQ(irq, regs);
-}
-
-static struct irqaction cpm2_irqaction = {
- .handler = cpm2_cascade,
- .flags = SA_INTERRUPT,
- .mask = CPU_MASK_NONE,
- .name = "cpm2_cascade",
-};
-#endif /* CONFIG_CPM2 */
-
void __init
mpc85xx_cds_init_IRQ(void)
{
bd_t *binfo = (bd_t *) __res;
#ifdef CONFIG_CPM2
volatile cpm2_map_t *immap = cpm2_immr;
- int i;
#endif
/* Determine the Physical Address of the OpenPIC regs */
@@ -202,12 +203,7 @@
openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
#ifdef CONFIG_CPM2
- /* disable all CPM interupts */
- immap->im_intctl.ic_simrh = 0x0;
- immap->im_intctl.ic_simrl = 0x0;
-
- for (i = CPM_IRQ_OFFSET; i < (NR_CPM_INTS + CPM_IRQ_OFFSET); i++)
- irq_desc[i].handler = &cpm2_pic;
+ cpm2_init_IRQ();
/* Initialize the default interrupt mapping priorities,
* in case the boot rom changed something on us.
@@ -216,7 +212,7 @@
immap->im_intctl.ic_scprrh = 0x05309770;
immap->im_intctl.ic_scprrl = 0x05309770;
- setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
+ openpic_hookup_cascade(MPC85xx_IRQ_CPM, "CPM Cascade", cpm2_get_irq);
#endif
return;
@@ -303,6 +299,8 @@
}
#endif /* CONFIG_PCI */
+TODC_ALLOC();
+
/* ************************************************************************
*
* Setup the architecture
@@ -328,6 +326,13 @@
cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
+ /* Setup TODC access */
+ TODC_INIT(TODC_TYPE_DS1743,
+ 0,
+ 0,
+ ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE),
+ 8);
+
/* Set loops_per_jiffy to a half-way reasonable value,
for use until calibrate_delay gets called. */
loops_per_jiffy = freq / HZ;
@@ -364,7 +369,6 @@
pdata->phy_reg_addr += binfo->bi_immr_base;
memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
-
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
@@ -452,11 +456,15 @@
ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
- ppc_md.time_init = NULL;
- ppc_md.set_rtc_time = NULL;
- ppc_md.get_rtc_time = NULL;
ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
+ ppc_md.time_init = todc_time_init;
+ ppc_md.set_rtc_time = todc_set_rtc_time;
+ ppc_md.get_rtc_time = todc_get_rtc_time;
+
+ ppc_md.nvram_read_val = todc_direct_read_val;
+ ppc_md.nvram_write_val = todc_direct_write_val;
+
#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
ppc_md.progress = gen550_progress;
#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
--- linux-orig/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
+++ linux/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
@@ -33,6 +33,10 @@
#define CM_CSR (1)
#define CM_RST (2)
+/* CDS NVRAM/RTC */
+#define CDS_RTC_ADDR (0xf8000000)
+#define CDS_RTC_SIZE (8 * 1024)
+
/* PCI config */
#define PCI1_CFG_ADDR_OFFSET (0x8000)
#define PCI1_CFG_DATA_OFFSET (0x8004)
--- linux-orig/arch/ppc/syslib/Makefile
+++ linux/arch/ppc/syslib/Makefile
@@ -98,5 +98,6 @@
ppc_sys.o
ifeq ($(CONFIG_85xx),y)
obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o
+obj-$(CONFIG_MPC8555_CDS) += todc_time.o
endif
obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o
--- linux-orig/include/asm-ppc/immap_85xx.h
+++ linux/include/asm-ppc/immap_85xx.h
@@ -122,5 +122,49 @@
char res13[61916];
} ccsr_guts_t;
+/* L2 Cache Registers(0x2_0000-0x2_1000) */
+
+typedef struct ccsr_l2cache {
+ uint32_t l2ctl; /* 0x.0000 - L2 configuration register 0 */
+ uint8_t res1[12];
+ uint32_t l2cewar0; /* 0x.0010 - L2 cache external write address register 0 */
+ uint8_t res2[4];
+ uint32_t l2cewcr0; /* 0x.0018 - L2 cache external write control register 0 */
+ uint8_t res3[4];
+ uint32_t l2cewar1; /* 0x.0020 - L2 cache external write address register 1 */
+ uint8_t res4[4];
+ uint32_t l2cewcr1; /* 0x.0028 - L2 cache external write control register 1 */
+ uint8_t res5[4];
+ uint32_t l2cewar2; /* 0x.0030 - L2 cache external write address register 2 */
+ uint8_t res6[4];
+ uint32_t l2cewcr2; /* 0x.0038 - L2 cache external write control register 2 */
+ uint8_t res7[4];
+ uint32_t l2cewar3; /* 0x.0040 - L2 cache external write address register 3 */
+ uint8_t res8[4];
+ uint32_t l2cewcr3; /* 0x.0048 - L2 cache external write control register 3 */
+ uint8_t res9[180];
+ uint32_t l2srbar0; /* 0x.0100 - L2 memory-mapped SRAM base address register 0 */
+ uint8_t res10[4];
+ uint32_t l2srbar1; /* 0x.0108 - L2 memory-mapped SRAM base address register 1 */
+ uint8_t res11[3316];
+ uint32_t l2errinjhi; /* 0x.0e00 - L2 error injection mask high register */
+ uint32_t l2errinjlo; /* 0x.0e04 - L2 error injection mask low register */
+ uint32_t l2errinjctl; /* 0x.0e08 - L2 error injection tag/ECC control register */
+ uint8_t res12[20];
+ uint32_t l2captdatahi; /* 0x.0e20 - L2 error data high capture register */
+ uint32_t l2captdatalo; /* 0x.0e24 - L2 error data low capture register */
+ uint32_t l2captecc; /* 0x.0e28 - L2 error ECC capture register */
+ uint8_t res13[20];
+ uint32_t l2errdet; /* 0x.0e40 - L2 error detect register */
+ uint32_t l2errdis; /* 0x.0e44 - L2 error disable register */
+ uint32_t l2errinten; /* 0x.0e48 - L2 error interrupt enable register */
+ uint32_t l2errattr; /* 0x.0e4c - L2 error attributes capture register */
+ uint32_t l2erraddr; /* 0x.0e50 - L2 error address capture register */
+ uint8_t res14[4];
+ uint32_t l2errctl; /* 0x.0e58 - L2 error control register */
+ uint8_t res15[420];
+} ccsr_l2cache_t;
+
+
#endif /* __ASM_IMMAP_85XX_H__ */
#endif /* __KERNEL__ */
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next reply other threads:[~2005-03-22 20:47 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-03-22 20:47 Jason McMullan [this message]
2005-03-22 22:56 ` [PATCH] MPC85xx CDS - Time Of Day, Cache settings, CPM IRQs Kumar Gala
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