* [PATCH 00/15] powerpc: move some header files
@ 2006-04-05 5:10 sfr
2006-04-05 5:10 ` [PATCH 01/15] powerpc: move asm/hignmem.h sfr
` (15 more replies)
0 siblings, 16 replies; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
This patch set moves sufficient include files from include/asm-ppc
to include/asm-powerpc to allow us to remove the include hack in the
arch/powerpc/Makefile.
b/arch/powerpc/Makefile | 21 ++------------
b/include/asm-powerpc/amigappc.h | 9 ++----
b/include/asm-powerpc/bootinfo.h | 8 ++---
b/include/asm-powerpc/highmem.h | 11 +++----
b/include/asm-powerpc/hydra.h | 8 ++---
b/include/asm-powerpc/mpc83xx.h | 7 ++--
b/include/asm-powerpc/mpc85xx.h | 9 ++----
b/include/asm-powerpc/mpc8xx.h | 10 +++---
b/include/asm-powerpc/ocp.h | 7 ++--
b/include/asm-powerpc/ocp_ids.h | 6 ++--
b/include/asm-powerpc/open_pic.h | 10 +++---
b/include/asm-powerpc/pnp.h | 8 ++---
b/include/asm-powerpc/reg_booke.h | 55 +++++++++++++++++++------------------- b/include/asm-powerpc/residual.h | 6 ++--
b/include/asm-powerpc/suspend.h | 17 +++++++++++
include/asm-ppc/suspend.h | 12 --------
16 files changed, 95 insertions(+), 109 deletions(-)
Cheers,
Stephen Rothwell <sfr@canb.auug.org.au>
P.S. these are available in my private git tree if you want them.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 01/15] powerpc: move asm/hignmem.h
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 5:10 ` [PATCH 02/15] powerpc: move asm/suspend.h sfr
` (14 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
From: Stephen Rothwell <sfr@canb.auug.org.au>
Files in arch/powerpc now depend on asm/highmem.h, so move
it to include/asm-powerpc/
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/highmem.h | 136 +++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/highmem.h | 137 -----------------------------------------
2 files changed, 136 insertions(+), 137 deletions(-)
create mode 100644 include/asm-powerpc/highmem.h
delete mode 100644 include/asm-ppc/highmem.h
50bea8557eb3c7ac43a21d7e5990e2f61cf4caed
diff --git a/include/asm-powerpc/highmem.h b/include/asm-powerpc/highmem.h
new file mode 100644
index 0000000..c2357ba
--- /dev/null
+++ b/include/asm-powerpc/highmem.h
@@ -0,0 +1,136 @@
+#ifndef _ASM_POWERPC_HIGHMEM_H
+#define _ASM_POWERPC_HIGHMEM_H
+/*
+ * highmem.h: virtual kernel memory mappings for high memory
+ *
+ * PowerPC version, stolen from the i386 version.
+ *
+ * Used in CONFIG_HIGHMEM systems for memory pages which
+ * are not addressable by direct kernel virtual addresses.
+ *
+ * Copyright (C) 1999 Gerhard Wichert, Siemens AG
+ * Gerhard.Wichert@pdb.siemens.de
+ *
+ *
+ * Redesigned the x86 32-bit VM architecture to deal with
+ * up to 16 Terrabyte physical memory. With current x86 CPUs
+ * we now support up to 64 Gigabytes physical RAM.
+ *
+ * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <asm/kmap_types.h>
+#include <asm/tlbflush.h>
+#include <asm/page.h>
+
+/* undef for production */
+#define HIGHMEM_DEBUG 1
+
+extern pte_t *kmap_pte;
+extern pgprot_t kmap_prot;
+extern pte_t *pkmap_page_table;
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.
+ */
+#define PKMAP_BASE CONFIG_HIGHMEM_START
+#define LAST_PKMAP (1 << PTE_SHIFT)
+#define LAST_PKMAP_MASK (LAST_PKMAP-1)
+#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+
+#define KMAP_FIX_BEGIN (PKMAP_BASE + 0x00400000UL)
+
+extern void *kmap_high(struct page *page);
+extern void kunmap_high(struct page *page);
+
+static inline void *kmap(struct page *page)
+{
+ might_sleep();
+ if (!PageHighMem(page))
+ return page_address(page);
+ return kmap_high(page);
+}
+
+static inline void kunmap(struct page *page)
+{
+ BUG_ON(in_interrupt());
+ if (!PageHighMem(page))
+ return;
+ kunmap_high(page);
+}
+
+/*
+ * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
+ * gives a more generic (and caching) interface. But kmap_atomic can
+ * be used in IRQ contexts, so in some (very limited) cases we need
+ * it.
+ */
+static inline void *kmap_atomic(struct page *page, enum km_type type)
+{
+ unsigned int idx;
+ unsigned long vaddr;
+
+ /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
+ inc_preempt_count();
+ if (!PageHighMem(page))
+ return page_address(page);
+
+ idx = type + KM_TYPE_NR*smp_processor_id();
+ vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE;
+#ifdef HIGHMEM_DEBUG
+ BUG_ON(!pte_none(*(kmap_pte+idx)));
+#endif
+ set_pte_at(&init_mm, vaddr, kmap_pte+idx, mk_pte(page, kmap_prot));
+ flush_tlb_page(NULL, vaddr);
+
+ return (void*) vaddr;
+}
+
+static inline void kunmap_atomic(void *kvaddr, enum km_type type)
+{
+#ifdef HIGHMEM_DEBUG
+ unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
+ unsigned int idx = type + KM_TYPE_NR*smp_processor_id();
+
+ if (vaddr < KMAP_FIX_BEGIN) { // FIXME
+ dec_preempt_count();
+ preempt_check_resched();
+ return;
+ }
+
+ BUG_ON(vaddr != KMAP_FIX_BEGIN + idx * PAGE_SIZE);
+
+ /*
+ * force other mappings to Oops if they'll try to access
+ * this pte without first remap it
+ */
+ pte_clear(&init_mm, vaddr, kmap_pte+idx);
+ flush_tlb_page(NULL, vaddr);
+#endif
+ dec_preempt_count();
+ preempt_check_resched();
+}
+
+static inline struct page *kmap_atomic_to_page(void *ptr)
+{
+ unsigned long idx, vaddr = (unsigned long) ptr;
+
+ if (vaddr < KMAP_FIX_BEGIN)
+ return virt_to_page(ptr);
+
+ idx = (vaddr - KMAP_FIX_BEGIN) >> PAGE_SHIFT;
+ return pte_page(kmap_pte[idx]);
+}
+
+#define flush_cache_kmaps() flush_cache_all()
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_POWERPC_HIGHMEM_H */
diff --git a/include/asm-ppc/highmem.h b/include/asm-ppc/highmem.h
deleted file mode 100644
index 1d2c4ef..0000000
--- a/include/asm-ppc/highmem.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * highmem.h: virtual kernel memory mappings for high memory
- *
- * PowerPC version, stolen from the i386 version.
- *
- * Used in CONFIG_HIGHMEM systems for memory pages which
- * are not addressable by direct kernel virtual addresses.
- *
- * Copyright (C) 1999 Gerhard Wichert, Siemens AG
- * Gerhard.Wichert@pdb.siemens.de
- *
- *
- * Redesigned the x86 32-bit VM architecture to deal with
- * up to 16 Terrabyte physical memory. With current x86 CPUs
- * we now support up to 64 Gigabytes physical RAM.
- *
- * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
- */
-
-#ifndef _ASM_HIGHMEM_H
-#define _ASM_HIGHMEM_H
-
-#ifdef __KERNEL__
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <asm/kmap_types.h>
-#include <asm/tlbflush.h>
-#include <asm/page.h>
-
-/* undef for production */
-#define HIGHMEM_DEBUG 1
-
-extern pte_t *kmap_pte;
-extern pgprot_t kmap_prot;
-extern pte_t *pkmap_page_table;
-
-/*
- * Right now we initialize only a single pte table. It can be extended
- * easily, subsequent pte tables have to be allocated in one physical
- * chunk of RAM.
- */
-#define PKMAP_BASE CONFIG_HIGHMEM_START
-#define LAST_PKMAP (1 << PTE_SHIFT)
-#define LAST_PKMAP_MASK (LAST_PKMAP-1)
-#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT)
-#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
-
-#define KMAP_FIX_BEGIN (PKMAP_BASE + 0x00400000UL)
-
-extern void *kmap_high(struct page *page);
-extern void kunmap_high(struct page *page);
-
-static inline void *kmap(struct page *page)
-{
- might_sleep();
- if (!PageHighMem(page))
- return page_address(page);
- return kmap_high(page);
-}
-
-static inline void kunmap(struct page *page)
-{
- BUG_ON(in_interrupt());
- if (!PageHighMem(page))
- return;
- kunmap_high(page);
-}
-
-/*
- * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
- * gives a more generic (and caching) interface. But kmap_atomic can
- * be used in IRQ contexts, so in some (very limited) cases we need
- * it.
- */
-static inline void *kmap_atomic(struct page *page, enum km_type type)
-{
- unsigned int idx;
- unsigned long vaddr;
-
- /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
- inc_preempt_count();
- if (!PageHighMem(page))
- return page_address(page);
-
- idx = type + KM_TYPE_NR*smp_processor_id();
- vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE;
-#ifdef HIGHMEM_DEBUG
- BUG_ON(!pte_none(*(kmap_pte+idx)));
-#endif
- set_pte_at(&init_mm, vaddr, kmap_pte+idx, mk_pte(page, kmap_prot));
- flush_tlb_page(NULL, vaddr);
-
- return (void*) vaddr;
-}
-
-static inline void kunmap_atomic(void *kvaddr, enum km_type type)
-{
-#ifdef HIGHMEM_DEBUG
- unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
- unsigned int idx = type + KM_TYPE_NR*smp_processor_id();
-
- if (vaddr < KMAP_FIX_BEGIN) { // FIXME
- dec_preempt_count();
- preempt_check_resched();
- return;
- }
-
- BUG_ON(vaddr != KMAP_FIX_BEGIN + idx * PAGE_SIZE);
-
- /*
- * force other mappings to Oops if they'll try to access
- * this pte without first remap it
- */
- pte_clear(&init_mm, vaddr, kmap_pte+idx);
- flush_tlb_page(NULL, vaddr);
-#endif
- dec_preempt_count();
- preempt_check_resched();
-}
-
-static inline struct page *kmap_atomic_to_page(void *ptr)
-{
- unsigned long idx, vaddr = (unsigned long) ptr;
-
- if (vaddr < KMAP_FIX_BEGIN)
- return virt_to_page(ptr);
-
- idx = (vaddr - KMAP_FIX_BEGIN) >> PAGE_SHIFT;
- return pte_page(kmap_pte[idx]);
-}
-
-#define flush_cache_kmaps() flush_cache_all()
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_HIGHMEM_H */
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 02/15] powerpc: move asm/suspend.h
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
2006-04-05 5:10 ` [PATCH 01/15] powerpc: move asm/hignmem.h sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 5:10 ` [PATCH 03/15] powerpc: move asm/mpc8xx.h sfr
` (13 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since files in arch/powerpc now depend on asm/suspend.h,
move it to include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/suspend.h | 17 +++++++++++++++++
include/asm-ppc/suspend.h | 12 ------------
2 files changed, 17 insertions(+), 12 deletions(-)
create mode 100644 include/asm-powerpc/suspend.h
delete mode 100644 include/asm-ppc/suspend.h
8d1f48e5eb94865c139b9c0ffd51ad50f991a1e6
diff --git a/include/asm-powerpc/suspend.h b/include/asm-powerpc/suspend.h
new file mode 100644
index 0000000..39fb2cd
--- /dev/null
+++ b/include/asm-powerpc/suspend.h
@@ -0,0 +1,17 @@
+#ifndef _ASM_POWERPC_SUSPEND_H
+#define _ASM_POWERPC_SUSPEND_H
+
+static inline int arch_prepare_suspend(void)
+{
+ return 0;
+}
+
+static inline void save_processor_state(void)
+{
+}
+
+static inline void restore_processor_state(void)
+{
+}
+
+#endif /* _ASM_POWERPC_SUSPEND_H */
diff --git a/include/asm-ppc/suspend.h b/include/asm-ppc/suspend.h
deleted file mode 100644
index 3df9f32..0000000
--- a/include/asm-ppc/suspend.h
+++ /dev/null
@@ -1,12 +0,0 @@
-static inline int arch_prepare_suspend(void)
-{
- return 0;
-}
-
-static inline void save_processor_state(void)
-{
-}
-
-static inline void restore_processor_state(void)
-{
-}
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 03/15] powerpc: move asm/mpc8xx.h
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
2006-04-05 5:10 ` [PATCH 01/15] powerpc: move asm/hignmem.h sfr
2006-04-05 5:10 ` [PATCH 02/15] powerpc: move asm/suspend.h sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 5:10 ` [PATCH 04/15] powerpc: move asm/bootinfo.h sfr
` (12 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since files in arch/powerpc now depend on asm/mpc8xx.h,
move it to include/asm_powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/mpc8xx.h | 126 ++++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/mpc8xx.h | 126 ------------------------------------------
2 files changed, 126 insertions(+), 126 deletions(-)
create mode 100644 include/asm-powerpc/mpc8xx.h
delete mode 100644 include/asm-ppc/mpc8xx.h
f42aaf39f24784b0beecc91de6dc78f600d3b8cd
diff --git a/include/asm-powerpc/mpc8xx.h b/include/asm-powerpc/mpc8xx.h
new file mode 100644
index 0000000..db027e7
--- /dev/null
+++ b/include/asm-powerpc/mpc8xx.h
@@ -0,0 +1,126 @@
+#ifndef _ASM_POWERPC_MPC8XX_H
+#define _ASM_POWERPC_MPC8XX_H
+
+/* This is the single file included by all MPC8xx build options.
+ * Since there are many different boards and no standard configuration,
+ * we have a unique include file for each. Rather than change every
+ * file that has to include MPC8xx configuration, they all include
+ * this one and the configuration switching is done here.
+ */
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_8xx
+
+#ifdef CONFIG_MBX
+#include <platforms/mbx.h>
+#endif
+
+#ifdef CONFIG_FADS
+#include <platforms/fads.h>
+#endif
+
+#ifdef CONFIG_RPXLITE
+#include <platforms/rpxlite.h>
+#endif
+
+#ifdef CONFIG_BSEIP
+#include <platforms/bseip.h>
+#endif
+
+#ifdef CONFIG_RPXCLASSIC
+#include <platforms/rpxclassic.h>
+#endif
+
+#if defined(CONFIG_TQM8xxL)
+#include <platforms/tqm8xx.h>
+#endif
+
+#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
+#include <platforms/ivms8.h>
+#endif
+
+#if defined(CONFIG_HERMES_PRO)
+#include <platforms/hermes.h>
+#endif
+
+#if defined(CONFIG_IP860)
+#include <platforms/ip860.h>
+#endif
+
+#if defined(CONFIG_LWMON)
+#include <platforms/lwmon.h>
+#endif
+
+#if defined(CONFIG_PCU_E)
+#include <platforms/pcu_e.h>
+#endif
+
+#if defined(CONFIG_CCM)
+#include <platforms/ccm.h>
+#endif
+
+#if defined(CONFIG_LANTEC)
+#include <platforms/lantec.h>
+#endif
+
+#if defined(CONFIG_MPC885ADS)
+#include <platforms/mpc885ads.h>
+#endif
+
+/* Currently, all 8xx boards that support a processor to PCI/ISA bridge
+ * use the same memory map.
+ */
+#if 0
+#if defined(CONFIG_PCI) && defined(PCI_ISA_IO_ADDR)
+#define _IO_BASE PCI_ISA_IO_ADDR
+#define _ISA_MEM_BASE PCI_ISA_MEM_ADDR
+#define PCI_DRAM_OFFSET 0x80000000
+#else
+#define _IO_BASE 0
+#define _ISA_MEM_BASE 0
+#define PCI_DRAM_OFFSET 0
+#endif
+#else
+#if !defined(_IO_BASE) /* defined in board specific header */
+#define _IO_BASE 0
+#endif
+#define _ISA_MEM_BASE 0
+#define PCI_DRAM_OFFSET 0
+#endif
+
+#ifndef __ASSEMBLY__
+/* The "residual" data board information structure the boot loader
+ * hands to us.
+ */
+extern unsigned char __res[];
+
+struct pt_regs;
+
+enum ppc_sys_devices {
+ MPC8xx_CPM_FEC1,
+ MPC8xx_CPM_FEC2,
+ MPC8xx_CPM_I2C,
+ MPC8xx_CPM_SCC1,
+ MPC8xx_CPM_SCC2,
+ MPC8xx_CPM_SCC3,
+ MPC8xx_CPM_SCC4,
+ MPC8xx_CPM_SPI,
+ MPC8xx_CPM_MCC1,
+ MPC8xx_CPM_MCC2,
+ MPC8xx_CPM_SMC1,
+ MPC8xx_CPM_SMC2,
+ MPC8xx_CPM_USB,
+ NUM_PPC_SYS_DEVS,
+};
+
+#define PPC_PIN_SIZE (24 * 1024 * 1024) /* 24Mbytes of data pinned */
+
+#ifndef BOARD_CHIP_NAME
+#define BOARD_CHIP_NAME ""
+#endif
+
+#endif /* !__ASSEMBLY__ */
+#endif /* CONFIG_8xx */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_MPC8XX_H */
diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h
deleted file mode 100644
index 3515a7f..0000000
--- a/include/asm-ppc/mpc8xx.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* This is the single file included by all MPC8xx build options.
- * Since there are many different boards and no standard configuration,
- * we have a unique include file for each. Rather than change every
- * file that has to include MPC8xx configuration, they all include
- * this one and the configuration switching is done here.
- */
-#ifdef __KERNEL__
-#ifndef __CONFIG_8xx_DEFS
-#define __CONFIG_8xx_DEFS
-
-#include <linux/config.h>
-
-#ifdef CONFIG_8xx
-
-#ifdef CONFIG_MBX
-#include <platforms/mbx.h>
-#endif
-
-#ifdef CONFIG_FADS
-#include <platforms/fads.h>
-#endif
-
-#ifdef CONFIG_RPXLITE
-#include <platforms/rpxlite.h>
-#endif
-
-#ifdef CONFIG_BSEIP
-#include <platforms/bseip.h>
-#endif
-
-#ifdef CONFIG_RPXCLASSIC
-#include <platforms/rpxclassic.h>
-#endif
-
-#if defined(CONFIG_TQM8xxL)
-#include <platforms/tqm8xx.h>
-#endif
-
-#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
-#include <platforms/ivms8.h>
-#endif
-
-#if defined(CONFIG_HERMES_PRO)
-#include <platforms/hermes.h>
-#endif
-
-#if defined(CONFIG_IP860)
-#include <platforms/ip860.h>
-#endif
-
-#if defined(CONFIG_LWMON)
-#include <platforms/lwmon.h>
-#endif
-
-#if defined(CONFIG_PCU_E)
-#include <platforms/pcu_e.h>
-#endif
-
-#if defined(CONFIG_CCM)
-#include <platforms/ccm.h>
-#endif
-
-#if defined(CONFIG_LANTEC)
-#include <platforms/lantec.h>
-#endif
-
-#if defined(CONFIG_MPC885ADS)
-#include <platforms/mpc885ads.h>
-#endif
-
-/* Currently, all 8xx boards that support a processor to PCI/ISA bridge
- * use the same memory map.
- */
-#if 0
-#if defined(CONFIG_PCI) && defined(PCI_ISA_IO_ADDR)
-#define _IO_BASE PCI_ISA_IO_ADDR
-#define _ISA_MEM_BASE PCI_ISA_MEM_ADDR
-#define PCI_DRAM_OFFSET 0x80000000
-#else
-#define _IO_BASE 0
-#define _ISA_MEM_BASE 0
-#define PCI_DRAM_OFFSET 0
-#endif
-#else
-#if !defined(_IO_BASE) /* defined in board specific header */
-#define _IO_BASE 0
-#endif
-#define _ISA_MEM_BASE 0
-#define PCI_DRAM_OFFSET 0
-#endif
-
-#ifndef __ASSEMBLY__
-/* The "residual" data board information structure the boot loader
- * hands to us.
- */
-extern unsigned char __res[];
-
-struct pt_regs;
-
-enum ppc_sys_devices {
- MPC8xx_CPM_FEC1,
- MPC8xx_CPM_FEC2,
- MPC8xx_CPM_I2C,
- MPC8xx_CPM_SCC1,
- MPC8xx_CPM_SCC2,
- MPC8xx_CPM_SCC3,
- MPC8xx_CPM_SCC4,
- MPC8xx_CPM_SPI,
- MPC8xx_CPM_MCC1,
- MPC8xx_CPM_MCC2,
- MPC8xx_CPM_SMC1,
- MPC8xx_CPM_SMC2,
- MPC8xx_CPM_USB,
- NUM_PPC_SYS_DEVS,
-};
-
-#define PPC_PIN_SIZE (24 * 1024 * 1024) /* 24Mbytes of data pinned */
-
-#ifndef BOARD_CHIP_NAME
-#define BOARD_CHIP_NAME ""
-#endif
-
-#endif /* !__ASSEMBLY__ */
-#endif /* CONFIG_8xx */
-#endif /* __CONFIG_8xx_DEFS */
-#endif /* __KERNEL__ */
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 04/15] powerpc: move asm/bootinfo.h
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
` (2 preceding siblings ...)
2006-04-05 5:10 ` [PATCH 03/15] powerpc: move asm/mpc8xx.h sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 14:05 ` Kumar Gala
2006-04-05 5:10 ` [PATCH 05/15] powerpc: move asm/residual.h sfr
` (11 subsequent siblings)
15 siblings, 1 reply; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since files in arch/powerpc now depend on asm/bootinfo.h,
move it to include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/bootinfo.h | 52 ++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/bootinfo.h | 52 ----------------------------------------
2 files changed, 52 insertions(+), 52 deletions(-)
create mode 100644 include/asm-powerpc/bootinfo.h
delete mode 100644 include/asm-ppc/bootinfo.h
355987a8cf0cf4b644e83b8268a9a34cf4524ee0
diff --git a/include/asm-powerpc/bootinfo.h b/include/asm-powerpc/bootinfo.h
new file mode 100644
index 0000000..231c534
--- /dev/null
+++ b/include/asm-powerpc/bootinfo.h
@@ -0,0 +1,52 @@
+#ifndef _ASM_POWERPC_BOOTINFO_H
+#define _ASM_POWERPC_BOOTINFO_H
+
+/*
+ * Non-machine dependent bootinfo structure. Basic idea
+ * borrowed from the m68k.
+ *
+ * Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org>
+ */
+
+#ifdef __KERNEL__
+
+#include <asm/page.h>
+
+#if defined(CONFIG_APUS) && !defined(__BOOTER__)
+#include <asm-m68k/bootinfo.h>
+#else
+
+struct bi_record {
+ unsigned long tag; /* tag ID */
+ unsigned long size; /* size of record (in bytes) */
+ unsigned long data[0]; /* data */
+};
+
+#define BI_FIRST 0x1010 /* first record - marker */
+#define BI_LAST 0x1011 /* last record - marker */
+#define BI_CMD_LINE 0x1012
+#define BI_BOOTLOADER_ID 0x1013
+#define BI_INITRD 0x1014
+#define BI_SYSMAP 0x1015
+#define BI_MACHTYPE 0x1016
+#define BI_MEMSIZE 0x1017
+#define BI_BOARD_INFO 0x1018
+
+extern struct bi_record *find_bootinfo(void);
+extern void bootinfo_init(struct bi_record *rec);
+extern void bootinfo_append(unsigned long tag, unsigned long size, void * data);
+extern void parse_bootinfo(struct bi_record *rec);
+extern unsigned long boot_mem_size;
+
+static inline struct bi_record *
+bootinfo_addr(unsigned long offset)
+{
+
+ return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1,
+ (1 << 20));
+}
+#endif /* CONFIG_APUS */
+
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_BOOTINFO_H */
diff --git a/include/asm-ppc/bootinfo.h b/include/asm-ppc/bootinfo.h
deleted file mode 100644
index 93d955c..0000000
--- a/include/asm-ppc/bootinfo.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Non-machine dependent bootinfo structure. Basic idea
- * borrowed from the m68k.
- *
- * Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org>
- */
-
-#ifdef __KERNEL__
-#ifndef _PPC_BOOTINFO_H
-#define _PPC_BOOTINFO_H
-
-#include <linux/config.h>
-#include <asm/page.h>
-
-#if defined(CONFIG_APUS) && !defined(__BOOTER__)
-#include <asm-m68k/bootinfo.h>
-#else
-
-struct bi_record {
- unsigned long tag; /* tag ID */
- unsigned long size; /* size of record (in bytes) */
- unsigned long data[0]; /* data */
-};
-
-#define BI_FIRST 0x1010 /* first record - marker */
-#define BI_LAST 0x1011 /* last record - marker */
-#define BI_CMD_LINE 0x1012
-#define BI_BOOTLOADER_ID 0x1013
-#define BI_INITRD 0x1014
-#define BI_SYSMAP 0x1015
-#define BI_MACHTYPE 0x1016
-#define BI_MEMSIZE 0x1017
-#define BI_BOARD_INFO 0x1018
-
-extern struct bi_record *find_bootinfo(void);
-extern void bootinfo_init(struct bi_record *rec);
-extern void bootinfo_append(unsigned long tag, unsigned long size, void * data);
-extern void parse_bootinfo(struct bi_record *rec);
-extern unsigned long boot_mem_size;
-
-static inline struct bi_record *
-bootinfo_addr(unsigned long offset)
-{
-
- return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1,
- (1 << 20));
-}
-#endif /* CONFIG_APUS */
-
-
-#endif /* _PPC_BOOTINFO_H */
-#endif /* __KERNEL__ */
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 05/15] powerpc: move asm/residual.h
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
` (3 preceding siblings ...)
2006-04-05 5:10 ` [PATCH 04/15] powerpc: move asm/bootinfo.h sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 5:10 ` [PATCH 06/15] powerpc: moce asm/pnp.h sfr
` (10 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since files in arch/powerpc now depend on asm/residual.h,
move it to include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/residual.h | 350 ++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/residual.h | 350 ----------------------------------------
2 files changed, 350 insertions(+), 350 deletions(-)
create mode 100644 include/asm-powerpc/residual.h
delete mode 100644 include/asm-ppc/residual.h
ef99b7d67ed186a6e524c1bdb41d3617b187deee
diff --git a/include/asm-powerpc/residual.h b/include/asm-powerpc/residual.h
new file mode 100644
index 0000000..c851b22
--- /dev/null
+++ b/include/asm-powerpc/residual.h
@@ -0,0 +1,350 @@
+#ifndef _ASM_POWERPC_RESIDUAL_H
+#define _ASM_POWERPC_RESIDUAL_H
+/* 7/18/95 */
+/*----------------------------------------------------------------------------*/
+/* Residual Data header definitions and prototypes */
+/*----------------------------------------------------------------------------*/
+
+/* Structure map for RESIDUAL on PowerPC Reference Platform */
+/* residual.h - Residual data structure passed in r3. */
+/* Load point passed in r4 to boot image. */
+/* For enum's: if given in hex then they are bit significant, */
+/* i.e. only one bit is on for each enum */
+/* Reserved fields must be filled with zeros. */
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+#define MAX_CPUS 32 /* These should be set to the maximum */
+#define MAX_MEMS 64 /* number possible for this system. */
+#define MAX_DEVICES 256 /* Changing these will change the */
+#define AVE_PNP_SIZE 32 /* structure, hence the version of */
+#define MAX_MEM_SEGS 64 /* this header file. */
+
+/*----------------------------------------------------------------------------*/
+/* Public structures... */
+/*----------------------------------------------------------------------------*/
+
+#include <asm/pnp.h>
+
+typedef enum _L1CACHE_TYPE {
+ NoneCAC = 0,
+ SplitCAC = 1,
+ CombinedCAC = 2
+ } L1CACHE_TYPE;
+
+typedef enum _TLB_TYPE {
+ NoneTLB = 0,
+ SplitTLB = 1,
+ CombinedTLB = 2
+ } TLB_TYPE;
+
+typedef enum _FIRMWARE_SUPPORT {
+ Conventional = 0x01,
+ OpenFirmware = 0x02,
+ Diagnostics = 0x04,
+ LowDebug = 0x08,
+ Multiboot = 0x10,
+ LowClient = 0x20,
+ Hex41 = 0x40,
+ FAT = 0x80,
+ ISO9660 = 0x0100,
+ SCSI_InitiatorID_Override = 0x0200,
+ Tape_Boot = 0x0400,
+ FW_Boot_Path = 0x0800
+ } FIRMWARE_SUPPORT;
+
+typedef enum _FIRMWARE_SUPPLIERS {
+ IBMFirmware = 0x00,
+ MotoFirmware = 0x01, /* 7/18/95 */
+ FirmWorks = 0x02, /* 10/5/95 */
+ Bull = 0x03, /* 04/03/96 */
+ } FIRMWARE_SUPPLIERS;
+
+typedef enum _ENDIAN_SWITCH_METHODS {
+ UsePort92 = 0x01,
+ UsePCIConfigA8 = 0x02,
+ UseFF001030 = 0x03,
+ } ENDIAN_SWITCH_METHODS;
+
+typedef enum _SPREAD_IO_METHODS {
+ UsePort850 = 0x00,
+/*UsePCIConfigA8 = 0x02,*/
+ } SPREAD_IO_METHODS;
+
+typedef struct _VPD {
+
+ /* Box dependent stuff */
+ unsigned char PrintableModel[32]; /* Null terminated string.
+ Must be of the form:
+ vvv,<20h>,<model designation>,<0x0>
+ where vvv is the vendor ID
+ e.g. IBM PPS MODEL 6015<0x0> */
+ unsigned char Serial[16]; /* 12/94:
+ Serial Number; must be of the form:
+ vvv<serial number> where vvv is the
+ vendor ID.
+ e.g. IBM60151234567<20h><20h> */
+ unsigned char Reserved[48];
+ unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */
+ unsigned long FirmwareSupports; /* See FirmwareSupport enum */
+ unsigned long NvramSize; /* Size of nvram in bytes */
+ unsigned long NumSIMMSlots;
+ unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */
+ unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */
+ unsigned long SmpIar;
+ unsigned long RAMErrLogOffset; /* Heap offset to error log */
+ unsigned long Reserved5;
+ unsigned long Reserved6;
+ unsigned long ProcessorHz; /* Processor clock frequency in Hertz */
+ unsigned long ProcessorBusHz; /* Processor bus clock frequency */
+ unsigned long Reserved7;
+ unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */
+ unsigned long WordWidth; /* Word width in bits */
+ unsigned long PageSize; /* Page size in bytes */
+ unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache
+ for which coherency is maintained;
+ normally <= CacheLineSize. */
+ unsigned long GranuleSize; /* Unit of lock allocation to avoid */
+ /* false sharing of locks. */
+
+ /* L1 Cache variables */
+ unsigned long CacheSize; /* L1 Cache size in KB. This is the */
+ /* total size of the L1, whether */
+ /* combined or split */
+ unsigned long CacheAttrib; /* L1CACHE_TYPE */
+ unsigned long CacheAssoc; /* L1 Cache associativity. Use this
+ for combined cache. If split, put
+ zeros here. */
+ unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use
+ for combined cache. If split, put
+ zeros here. */
+ /* For split L1 Cache: (= combined if combined cache) */
+ unsigned long I_CacheSize;
+ unsigned long I_CacheAssoc;
+ unsigned long I_CacheLineSize;
+ unsigned long D_CacheSize;
+ unsigned long D_CacheAssoc;
+ unsigned long D_CacheLineSize;
+
+ /* Translation Lookaside Buffer variables */
+ unsigned long TLBSize; /* Total number of TLBs on the system */
+ unsigned long TLBAttrib; /* Combined I+D or split TLB */
+ unsigned long TLBAssoc; /* TLB Associativity. Use this for
+ combined TLB. If split, put zeros
+ here. */
+ /* For split TLB: (= combined if combined TLB) */
+ unsigned long I_TLBSize;
+ unsigned long I_TLBAssoc;
+ unsigned long D_TLBSize;
+ unsigned long D_TLBAssoc;
+
+ unsigned long ExtendedVPD; /* Offset to extended VPD area;
+ null if unused */
+ } VPD;
+
+typedef enum _DEVICE_FLAGS {
+ Enabled = 0x4000, /* 1 - PCI device is enabled */
+ Integrated = 0x2000,
+ Failed = 0x1000, /* 1 - device failed POST code tests */
+ Static = 0x0800, /* 0 - dynamically configurable
+ 1 - static */
+ Dock = 0x0400, /* 0 - not a docking station device
+ 1 - is a docking station device */
+ Boot = 0x0200, /* 0 - device cannot be used for BOOT
+ 1 - can be a BOOT device */
+ Configurable = 0x0100, /* 1 - device is configurable */
+ Disableable = 0x80, /* 1 - device can be disabled */
+ PowerManaged = 0x40, /* 0 - not managed; 1 - managed */
+ ReadOnly = 0x20, /* 1 - device is read only */
+ Removable = 0x10, /* 1 - device is removable */
+ ConsoleIn = 0x08,
+ ConsoleOut = 0x04,
+ Input = 0x02,
+ Output = 0x01
+ } DEVICE_FLAGS;
+
+typedef enum _BUS_ID {
+ ISADEVICE = 0x01,
+ EISADEVICE = 0x02,
+ PCIDEVICE = 0x04,
+ PCMCIADEVICE = 0x08,
+ PNPISADEVICE = 0x10,
+ MCADEVICE = 0x20,
+ MXDEVICE = 0x40, /* Devices on mezzanine bus */
+ PROCESSORDEVICE = 0x80, /* Devices on processor bus */
+ VMEDEVICE = 0x100,
+ } BUS_ID;
+
+typedef struct _DEVICE_ID {
+ unsigned long BusId; /* See BUS_ID enum above */
+ unsigned long DevId; /* Big Endian format */
+ unsigned long SerialNum; /* For multiple usage of a single
+ DevId */
+ unsigned long Flags; /* See DEVICE_FLAGS enum above */
+ unsigned char BaseType; /* See pnp.h for bit definitions */
+ unsigned char SubType; /* See pnp.h for bit definitions */
+ unsigned char Interface; /* See pnp.h for bit definitions */
+ unsigned char Spare;
+ } DEVICE_ID;
+
+typedef union _BUS_ACCESS {
+ struct _PnPAccess{
+ unsigned char CSN;
+ unsigned char LogicalDevNumber;
+ unsigned short ReadDataPort;
+ } PnPAccess;
+ struct _ISAAccess{
+ unsigned char SlotNumber; /* ISA Slot Number generally not
+ available; 0 if unknown */
+ unsigned char LogicalDevNumber;
+ unsigned short ISAReserved;
+ } ISAAccess;
+ struct _MCAAccess{
+ unsigned char SlotNumber;
+ unsigned char LogicalDevNumber;
+ unsigned short MCAReserved;
+ } MCAAccess;
+ struct _PCMCIAAccess{
+ unsigned char SlotNumber;
+ unsigned char LogicalDevNumber;
+ unsigned short PCMCIAReserved;
+ } PCMCIAAccess;
+ struct _EISAAccess{
+ unsigned char SlotNumber;
+ unsigned char FunctionNumber;
+ unsigned short EISAReserved;
+ } EISAAccess;
+ struct _PCIAccess{
+ unsigned char BusNumber;
+ unsigned char DevFuncNumber;
+ unsigned short PCIReserved;
+ } PCIAccess;
+ struct _ProcBusAccess{
+ unsigned char BusNumber;
+ unsigned char BUID;
+ unsigned short ProcBusReserved;
+ } ProcBusAccess;
+ } BUS_ACCESS;
+
+/* Per logical device information */
+typedef struct _PPC_DEVICE {
+ DEVICE_ID DeviceId;
+ BUS_ACCESS BusAccess;
+
+ /* The following three are offsets into the DevicePnPHeap */
+ /* All are in PnP compressed format */
+ unsigned long AllocatedOffset; /* Allocated resource description */
+ unsigned long PossibleOffset; /* Possible resource description */
+ unsigned long CompatibleOffset; /* Compatible device identifiers */
+ } PPC_DEVICE;
+
+typedef enum _CPU_STATE {
+ CPU_GOOD = 0, /* CPU is present, and active */
+ CPU_GOOD_FW = 1, /* CPU is present, and in firmware */
+ CPU_OFF = 2, /* CPU is present, but inactive */
+ CPU_FAILED = 3, /* CPU is present, but failed POST */
+ CPU_NOT_PRESENT = 255 /* CPU not present */
+ } CPU_STATE;
+
+typedef struct _PPC_CPU {
+ unsigned long CpuType; /* Result of mfspr from Processor
+ Version Register (PVR).
+ PVR(0-15) = Version (e.g. 601)
+ PVR(16-31 = EC Level */
+ unsigned char CpuNumber; /* CPU Number for this processor */
+ unsigned char CpuState; /* CPU State, see CPU_STATE enum */
+ unsigned short Reserved;
+ } PPC_CPU;
+
+typedef struct _PPC_MEM {
+ unsigned long SIMMSize; /* 0 - absent or bad
+ 8M, 32M (in MB) */
+ } PPC_MEM;
+
+typedef enum _MEM_USAGE {
+ Other = 0x8000,
+ ResumeBlock = 0x4000, /* for use by power management */
+ SystemROM = 0x2000, /* Flash memory (populated) */
+ UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */
+ IOMemory = 0x0800,
+ SystemIO = 0x0400,
+ SystemRegs = 0x0200,
+ PCIAddr = 0x0100,
+ PCIConfig = 0x80,
+ ISAAddr = 0x40,
+ Unpopulated = 0x20, /* Unpopulated part of System Memory */
+ Free = 0x10, /* Free part of System Memory */
+ BootImage = 0x08, /* BootImage part of System Memory */
+ FirmwareCode = 0x04, /* FirmwareCode part of System Memory */
+ FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */
+ FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/
+ } MEM_USAGE;
+
+typedef struct _MEM_MAP {
+ unsigned long Usage; /* See MEM_USAGE above */
+ unsigned long BasePage; /* Page number measured in 4KB pages */
+ unsigned long PageCount; /* Page count measured in 4KB pages */
+ } MEM_MAP;
+
+typedef struct _RESIDUAL {
+ unsigned long ResidualLength; /* Length of Residual */
+ unsigned char Version; /* of this data structure */
+ unsigned char Revision; /* of this data structure */
+ unsigned short EC; /* of this data structure */
+ /* VPD */
+ VPD VitalProductData;
+ /* CPU */
+ unsigned short MaxNumCpus; /* Max CPUs in this system */
+ unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */
+ /* that there are unpopulated or */
+ /* otherwise unusable cpu locations */
+ PPC_CPU Cpus[MAX_CPUS];
+ /* Memory */
+ unsigned long TotalMemory; /* Total amount of memory installed */
+ unsigned long GoodMemory; /* Total amount of good memory */
+ unsigned long ActualNumMemSegs;
+ MEM_MAP Segs[MAX_MEM_SEGS];
+ unsigned long ActualNumMemories;
+ PPC_MEM Memories[MAX_MEMS];
+ /* Devices */
+ unsigned long ActualNumDevices;
+ PPC_DEVICE Devices[MAX_DEVICES];
+ unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE];
+ } RESIDUAL;
+
+
+/*
+ * Forward declaration - we can't include <linux/pci.h> because it
+ * breaks the boot loader
+ */
+struct pci_dev;
+
+extern RESIDUAL *res;
+extern void print_residual_device_info(void);
+extern PPC_DEVICE *residual_find_device(unsigned long BusMask,
+ unsigned char * DevID, int BaseType,
+ int SubType, int Interface, int n);
+extern int residual_pcidev_irq(struct pci_dev *dev);
+extern void residual_irq_mask(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
+extern unsigned int residual_isapic_addr(void);
+extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag,
+ int n);
+extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p,
+ unsigned packet_type,
+ int n);
+extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p,
+ unsigned packet_type,
+ int n);
+
+#ifdef CONFIG_PREP_RESIDUAL
+#define have_residual_data (res && res->ResidualLength)
+#else
+#define have_residual_data 0
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_RESIDUAL_H */
diff --git a/include/asm-ppc/residual.h b/include/asm-ppc/residual.h
deleted file mode 100644
index 934810d..0000000
--- a/include/asm-ppc/residual.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/* 7/18/95 */
-/*----------------------------------------------------------------------------*/
-/* Residual Data header definitions and prototypes */
-/*----------------------------------------------------------------------------*/
-
-/* Structure map for RESIDUAL on PowerPC Reference Platform */
-/* residual.h - Residual data structure passed in r3. */
-/* Load point passed in r4 to boot image. */
-/* For enum's: if given in hex then they are bit significant, */
-/* i.e. only one bit is on for each enum */
-/* Reserved fields must be filled with zeros. */
-
-#ifdef __KERNEL__
-#ifndef _RESIDUAL_
-#define _RESIDUAL_
-
-#ifndef __ASSEMBLY__
-
-#define MAX_CPUS 32 /* These should be set to the maximum */
-#define MAX_MEMS 64 /* number possible for this system. */
-#define MAX_DEVICES 256 /* Changing these will change the */
-#define AVE_PNP_SIZE 32 /* structure, hence the version of */
-#define MAX_MEM_SEGS 64 /* this header file. */
-
-/*----------------------------------------------------------------------------*/
-/* Public structures... */
-/*----------------------------------------------------------------------------*/
-
-#include <asm/pnp.h>
-
-typedef enum _L1CACHE_TYPE {
- NoneCAC = 0,
- SplitCAC = 1,
- CombinedCAC = 2
- } L1CACHE_TYPE;
-
-typedef enum _TLB_TYPE {
- NoneTLB = 0,
- SplitTLB = 1,
- CombinedTLB = 2
- } TLB_TYPE;
-
-typedef enum _FIRMWARE_SUPPORT {
- Conventional = 0x01,
- OpenFirmware = 0x02,
- Diagnostics = 0x04,
- LowDebug = 0x08,
- Multiboot = 0x10,
- LowClient = 0x20,
- Hex41 = 0x40,
- FAT = 0x80,
- ISO9660 = 0x0100,
- SCSI_InitiatorID_Override = 0x0200,
- Tape_Boot = 0x0400,
- FW_Boot_Path = 0x0800
- } FIRMWARE_SUPPORT;
-
-typedef enum _FIRMWARE_SUPPLIERS {
- IBMFirmware = 0x00,
- MotoFirmware = 0x01, /* 7/18/95 */
- FirmWorks = 0x02, /* 10/5/95 */
- Bull = 0x03, /* 04/03/96 */
- } FIRMWARE_SUPPLIERS;
-
-typedef enum _ENDIAN_SWITCH_METHODS {
- UsePort92 = 0x01,
- UsePCIConfigA8 = 0x02,
- UseFF001030 = 0x03,
- } ENDIAN_SWITCH_METHODS;
-
-typedef enum _SPREAD_IO_METHODS {
- UsePort850 = 0x00,
-/*UsePCIConfigA8 = 0x02,*/
- } SPREAD_IO_METHODS;
-
-typedef struct _VPD {
-
- /* Box dependent stuff */
- unsigned char PrintableModel[32]; /* Null terminated string.
- Must be of the form:
- vvv,<20h>,<model designation>,<0x0>
- where vvv is the vendor ID
- e.g. IBM PPS MODEL 6015<0x0> */
- unsigned char Serial[16]; /* 12/94:
- Serial Number; must be of the form:
- vvv<serial number> where vvv is the
- vendor ID.
- e.g. IBM60151234567<20h><20h> */
- unsigned char Reserved[48];
- unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */
- unsigned long FirmwareSupports; /* See FirmwareSupport enum */
- unsigned long NvramSize; /* Size of nvram in bytes */
- unsigned long NumSIMMSlots;
- unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */
- unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */
- unsigned long SmpIar;
- unsigned long RAMErrLogOffset; /* Heap offset to error log */
- unsigned long Reserved5;
- unsigned long Reserved6;
- unsigned long ProcessorHz; /* Processor clock frequency in Hertz */
- unsigned long ProcessorBusHz; /* Processor bus clock frequency */
- unsigned long Reserved7;
- unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */
- unsigned long WordWidth; /* Word width in bits */
- unsigned long PageSize; /* Page size in bytes */
- unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache
- for which coherency is maintained;
- normally <= CacheLineSize. */
- unsigned long GranuleSize; /* Unit of lock allocation to avoid */
- /* false sharing of locks. */
-
- /* L1 Cache variables */
- unsigned long CacheSize; /* L1 Cache size in KB. This is the */
- /* total size of the L1, whether */
- /* combined or split */
- unsigned long CacheAttrib; /* L1CACHE_TYPE */
- unsigned long CacheAssoc; /* L1 Cache associativity. Use this
- for combined cache. If split, put
- zeros here. */
- unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use
- for combined cache. If split, put
- zeros here. */
- /* For split L1 Cache: (= combined if combined cache) */
- unsigned long I_CacheSize;
- unsigned long I_CacheAssoc;
- unsigned long I_CacheLineSize;
- unsigned long D_CacheSize;
- unsigned long D_CacheAssoc;
- unsigned long D_CacheLineSize;
-
- /* Translation Lookaside Buffer variables */
- unsigned long TLBSize; /* Total number of TLBs on the system */
- unsigned long TLBAttrib; /* Combined I+D or split TLB */
- unsigned long TLBAssoc; /* TLB Associativity. Use this for
- combined TLB. If split, put zeros
- here. */
- /* For split TLB: (= combined if combined TLB) */
- unsigned long I_TLBSize;
- unsigned long I_TLBAssoc;
- unsigned long D_TLBSize;
- unsigned long D_TLBAssoc;
-
- unsigned long ExtendedVPD; /* Offset to extended VPD area;
- null if unused */
- } VPD;
-
-typedef enum _DEVICE_FLAGS {
- Enabled = 0x4000, /* 1 - PCI device is enabled */
- Integrated = 0x2000,
- Failed = 0x1000, /* 1 - device failed POST code tests */
- Static = 0x0800, /* 0 - dynamically configurable
- 1 - static */
- Dock = 0x0400, /* 0 - not a docking station device
- 1 - is a docking station device */
- Boot = 0x0200, /* 0 - device cannot be used for BOOT
- 1 - can be a BOOT device */
- Configurable = 0x0100, /* 1 - device is configurable */
- Disableable = 0x80, /* 1 - device can be disabled */
- PowerManaged = 0x40, /* 0 - not managed; 1 - managed */
- ReadOnly = 0x20, /* 1 - device is read only */
- Removable = 0x10, /* 1 - device is removable */
- ConsoleIn = 0x08,
- ConsoleOut = 0x04,
- Input = 0x02,
- Output = 0x01
- } DEVICE_FLAGS;
-
-typedef enum _BUS_ID {
- ISADEVICE = 0x01,
- EISADEVICE = 0x02,
- PCIDEVICE = 0x04,
- PCMCIADEVICE = 0x08,
- PNPISADEVICE = 0x10,
- MCADEVICE = 0x20,
- MXDEVICE = 0x40, /* Devices on mezzanine bus */
- PROCESSORDEVICE = 0x80, /* Devices on processor bus */
- VMEDEVICE = 0x100,
- } BUS_ID;
-
-typedef struct _DEVICE_ID {
- unsigned long BusId; /* See BUS_ID enum above */
- unsigned long DevId; /* Big Endian format */
- unsigned long SerialNum; /* For multiple usage of a single
- DevId */
- unsigned long Flags; /* See DEVICE_FLAGS enum above */
- unsigned char BaseType; /* See pnp.h for bit definitions */
- unsigned char SubType; /* See pnp.h for bit definitions */
- unsigned char Interface; /* See pnp.h for bit definitions */
- unsigned char Spare;
- } DEVICE_ID;
-
-typedef union _BUS_ACCESS {
- struct _PnPAccess{
- unsigned char CSN;
- unsigned char LogicalDevNumber;
- unsigned short ReadDataPort;
- } PnPAccess;
- struct _ISAAccess{
- unsigned char SlotNumber; /* ISA Slot Number generally not
- available; 0 if unknown */
- unsigned char LogicalDevNumber;
- unsigned short ISAReserved;
- } ISAAccess;
- struct _MCAAccess{
- unsigned char SlotNumber;
- unsigned char LogicalDevNumber;
- unsigned short MCAReserved;
- } MCAAccess;
- struct _PCMCIAAccess{
- unsigned char SlotNumber;
- unsigned char LogicalDevNumber;
- unsigned short PCMCIAReserved;
- } PCMCIAAccess;
- struct _EISAAccess{
- unsigned char SlotNumber;
- unsigned char FunctionNumber;
- unsigned short EISAReserved;
- } EISAAccess;
- struct _PCIAccess{
- unsigned char BusNumber;
- unsigned char DevFuncNumber;
- unsigned short PCIReserved;
- } PCIAccess;
- struct _ProcBusAccess{
- unsigned char BusNumber;
- unsigned char BUID;
- unsigned short ProcBusReserved;
- } ProcBusAccess;
- } BUS_ACCESS;
-
-/* Per logical device information */
-typedef struct _PPC_DEVICE {
- DEVICE_ID DeviceId;
- BUS_ACCESS BusAccess;
-
- /* The following three are offsets into the DevicePnPHeap */
- /* All are in PnP compressed format */
- unsigned long AllocatedOffset; /* Allocated resource description */
- unsigned long PossibleOffset; /* Possible resource description */
- unsigned long CompatibleOffset; /* Compatible device identifiers */
- } PPC_DEVICE;
-
-typedef enum _CPU_STATE {
- CPU_GOOD = 0, /* CPU is present, and active */
- CPU_GOOD_FW = 1, /* CPU is present, and in firmware */
- CPU_OFF = 2, /* CPU is present, but inactive */
- CPU_FAILED = 3, /* CPU is present, but failed POST */
- CPU_NOT_PRESENT = 255 /* CPU not present */
- } CPU_STATE;
-
-typedef struct _PPC_CPU {
- unsigned long CpuType; /* Result of mfspr from Processor
- Version Register (PVR).
- PVR(0-15) = Version (e.g. 601)
- PVR(16-31 = EC Level */
- unsigned char CpuNumber; /* CPU Number for this processor */
- unsigned char CpuState; /* CPU State, see CPU_STATE enum */
- unsigned short Reserved;
- } PPC_CPU;
-
-typedef struct _PPC_MEM {
- unsigned long SIMMSize; /* 0 - absent or bad
- 8M, 32M (in MB) */
- } PPC_MEM;
-
-typedef enum _MEM_USAGE {
- Other = 0x8000,
- ResumeBlock = 0x4000, /* for use by power management */
- SystemROM = 0x2000, /* Flash memory (populated) */
- UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */
- IOMemory = 0x0800,
- SystemIO = 0x0400,
- SystemRegs = 0x0200,
- PCIAddr = 0x0100,
- PCIConfig = 0x80,
- ISAAddr = 0x40,
- Unpopulated = 0x20, /* Unpopulated part of System Memory */
- Free = 0x10, /* Free part of System Memory */
- BootImage = 0x08, /* BootImage part of System Memory */
- FirmwareCode = 0x04, /* FirmwareCode part of System Memory */
- FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */
- FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/
- } MEM_USAGE;
-
-typedef struct _MEM_MAP {
- unsigned long Usage; /* See MEM_USAGE above */
- unsigned long BasePage; /* Page number measured in 4KB pages */
- unsigned long PageCount; /* Page count measured in 4KB pages */
- } MEM_MAP;
-
-typedef struct _RESIDUAL {
- unsigned long ResidualLength; /* Length of Residual */
- unsigned char Version; /* of this data structure */
- unsigned char Revision; /* of this data structure */
- unsigned short EC; /* of this data structure */
- /* VPD */
- VPD VitalProductData;
- /* CPU */
- unsigned short MaxNumCpus; /* Max CPUs in this system */
- unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */
- /* that there are unpopulated or */
- /* otherwise unusable cpu locations */
- PPC_CPU Cpus[MAX_CPUS];
- /* Memory */
- unsigned long TotalMemory; /* Total amount of memory installed */
- unsigned long GoodMemory; /* Total amount of good memory */
- unsigned long ActualNumMemSegs;
- MEM_MAP Segs[MAX_MEM_SEGS];
- unsigned long ActualNumMemories;
- PPC_MEM Memories[MAX_MEMS];
- /* Devices */
- unsigned long ActualNumDevices;
- PPC_DEVICE Devices[MAX_DEVICES];
- unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE];
- } RESIDUAL;
-
-
-/*
- * Forward declaration - we can't include <linux/pci.h> because it
- * breaks the boot loader
- */
-struct pci_dev;
-
-extern RESIDUAL *res;
-extern void print_residual_device_info(void);
-extern PPC_DEVICE *residual_find_device(unsigned long BusMask,
- unsigned char * DevID, int BaseType,
- int SubType, int Interface, int n);
-extern int residual_pcidev_irq(struct pci_dev *dev);
-extern void residual_irq_mask(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
-extern unsigned int residual_isapic_addr(void);
-extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag,
- int n);
-extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p,
- unsigned packet_type,
- int n);
-extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p,
- unsigned packet_type,
- int n);
-
-#ifdef CONFIG_PREP_RESIDUAL
-#define have_residual_data (res && res->ResidualLength)
-#else
-#define have_residual_data 0
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* ndef _RESIDUAL_ */
-
-#endif /* __KERNEL__ */
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 06/15] powerpc: moce asm/pnp.h
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
` (4 preceding siblings ...)
2006-04-05 5:10 ` [PATCH 05/15] powerpc: move asm/residual.h sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 5:10 ` [PATCH 07/15] powerpc: move asm/amigappc.h sfr
` (9 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since files built from a ARCH=powerpc build now depend on
asm/pnp.h, move it to asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/pnp.h | 645 +++++++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/pnp.h | 645 ---------------------------------------------
2 files changed, 645 insertions(+), 645 deletions(-)
create mode 100644 include/asm-powerpc/pnp.h
delete mode 100644 include/asm-ppc/pnp.h
21facc8a4f9edba1d9d82a681017e74ca17db93b
diff --git a/include/asm-powerpc/pnp.h b/include/asm-powerpc/pnp.h
new file mode 100644
index 0000000..704a369
--- /dev/null
+++ b/include/asm-powerpc/pnp.h
@@ -0,0 +1,645 @@
+#ifndef _ASM_POWERPC_PNP_H
+#define _ASM_POWERPC_PNP_H
+/* 11/02/95 */
+/*----------------------------------------------------------------------------*/
+/* Plug and Play header definitions */
+/*----------------------------------------------------------------------------*/
+
+/* Structure map for PnP on PowerPC Reference Platform */
+/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */
+/* (or later versions) is available on Compuserve in the PLUGPLAY area. */
+/* This code has extensions to that specification, namely new short and */
+/* long tag types for platform dependent information */
+
+/* Warning: LE notation used throughout this file */
+
+/* For enum's: if given in hex then they are bit significant, i.e. */
+/* only one bit is on for each enum */
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+#define MAX_MEM_REGISTERS 9
+#define MAX_IO_PORTS 20
+#define MAX_IRQS 7
+/*#define MAX_DMA_CHANNELS 7*/
+
+/* Interrupt controllers */
+
+#define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */
+#define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */
+#define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */
+#define PNPinterrupt3 "PNP0003" /* APIC */
+#define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */
+
+/* Timers */
+
+#define PNPtimer0 "PNP0100" /* AT Timer */
+#define PNPtimer1 "PNP0101" /* EISA Timer */
+#define PNPtimer2 "PNP0102" /* MCA Timer */
+
+/* DMA controllers */
+
+#define PNPdma0 "PNP0200" /* AT DMA Controller */
+#define PNPdma1 "PNP0201" /* EISA DMA Controller */
+#define PNPdma2 "PNP0202" /* MCA DMA Controller */
+
+/* start of August 15, 1994 additions */
+/* CMOS */
+#define PNPCMOS "IBM0009" /* CMOS */
+
+/* L2 Cache */
+#define PNPL2 "IBM0007" /* L2 Cache */
+
+/* NVRAM */
+#define PNPNVRAM "IBM0008" /* NVRAM */
+
+/* Power Management */
+#define PNPPM "IBM0005" /* Power Management */
+/* end of August 15, 1994 additions */
+
+/* Keyboards */
+
+#define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */
+#define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */
+#define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */
+#define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */
+#define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */
+#define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */
+#define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */
+#define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */
+
+/* Parallel port controllers */
+
+#define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */
+#define PNPparallel1 "PNP0401" /* ECP Parallel Port */
+#define PNPepp "IBM001C" /* EPP Parallel Port */
+
+/* Serial port controllers */
+
+#define PNPserial0 "PNP0500" /* Standard PC Serial port */
+#define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */
+
+/* Disk controllers */
+
+#define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */
+#define PNPdisk1 "PNP0601" /* Plus Hardcard II */
+#define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */
+
+/* Diskette controllers */
+
+#define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */
+
+/* Display controllers */
+
+#define PNPdisplay0 "PNP0900" /* VGA Compatible */
+#define PNPdisplay1 "PNP0901" /* Video Seven VGA */
+#define PNPdisplay2 "PNP0902" /* 8514/A Compatible */
+#define PNPdisplay3 "PNP0903" /* Trident VGA */
+#define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */
+#define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */
+#define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */
+#define PNPdisplay7 "PNP0907" /* Western Digital VGA */
+#define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */
+#define PNPdisplay9 "PNP0909" /* S3 */
+#define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */
+#define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */
+#define PNPdisplayC "PNP090C" /* XGA Compatible */
+#define PNPdisplayD "PNP090D" /* ATI VGA Wonder */
+#define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */
+#define PNPdisplayF "PNP090F" /* Oak Technology VGA */
+
+/* Peripheral busses */
+
+#define PNPbuses0 "PNP0A00" /* ISA Bus */
+#define PNPbuses1 "PNP0A01" /* EISA Bus */
+#define PNPbuses2 "PNP0A02" /* MCA Bus */
+#define PNPbuses3 "PNP0A03" /* PCI Bus */
+#define PNPbuses4 "PNP0A04" /* VESA/VL Bus */
+
+/* RTC, BIOS, planar devices */
+
+#define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */
+#define PNPrtc0 "PNP0B00" /* AT RTC */
+#define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */
+#define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */
+#define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */
+#define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */
+
+/* PCMCIA controller */
+
+#define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */
+
+/* Mice */
+
+#define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */
+#define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */
+#define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */
+#define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */
+#define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */
+#define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */
+#define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */
+#define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */
+#define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */
+#define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */
+#define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */
+#define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */
+
+/* Modems */
+
+#define PNPmodem0 "PNP9000" /* Specific IDs TBD */
+
+/* Network controllers */
+
+#define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */
+#define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */
+#define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */
+#define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */
+#define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */
+#define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */
+#define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */
+#define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */
+
+/* SCSI controllers */
+
+#define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */
+#define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */
+#define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/
+#define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */
+#define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */
+#define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */
+#define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */
+
+/* Sound/Video, Multimedia */
+
+#define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */
+#define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */
+#define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */
+#define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */
+#define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */
+#define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */
+#define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */
+#define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */
+
+/* Operator Panel */
+#define PNPopctl "IBM000B" /* Operator's panel */
+
+/* Service Processor */
+#define PNPsp "IBM0011" /* IBM Service Processor */
+#define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */
+#define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */
+
+/* Memory Controller */
+#define PNPmemctl "IBM000A" /* Memory controller */
+
+/* Graphics Assist */
+#define PNPg_assist "IBM0014" /* Graphics Assist */
+
+/* Miscellaneous Device Controllers */
+#define PNPtablet "IBM0019" /* IBM Tablet Controller */
+
+/* PNP Packet Handles */
+
+#define S1_Packet 0x0A /* Version resource */
+#define S2_Packet 0x15 /* Logical DEVID (without flags) */
+#define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */
+#define S3_Packet 0x1C /* Compatible device ID */
+#define S4_Packet 0x22 /* IRQ resource (without flags) */
+#define S4_Packet_flags 0x23 /* IRQ resource (with flags) */
+#define S5_Packet 0x2A /* DMA resource */
+#define S6_Packet 0x30 /* Depend funct start (w/o priority) */
+#define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */
+#define S7_Packet 0x38 /* Depend funct end */
+#define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */
+#define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */
+#define S14_Packet 0x71 /* Vendor defined */
+#define S15_Packet 0x78 /* End of resource (w/o checksum) */
+#define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */
+#define L1_Packet 0x81 /* Memory range */
+#define L1_Shadow 0x20 /* Memory is shadowable */
+#define L1_32bit_mem 0x18 /* 32-bit memory only */
+#define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */
+#define L1_Decode_Hi 0x04 /* decode supports high address */
+#define L1_Cache 0x02 /* read cacheable, write-through */
+#define L1_Writeable 0x01 /* Memory is writeable */
+#define L2_Packet 0x82 /* ANSI ID string */
+#define L3_Packet 0x83 /* Unicode ID string */
+#define L4_Packet 0x84 /* Vendor defined */
+#define L5_Packet 0x85 /* Large I/O */
+#define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */
+#define END_TAG 0x78 /* End of resource */
+#define DF_START_TAG 0x30 /* Dependent function start */
+#define DF_START_TAG_priority 0x31 /* Dependent function start */
+#define DF_END_TAG 0x38 /* Dependent function end */
+#define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */
+
+/* Device Base Type Codes */
+
+typedef enum _PnP_BASE_TYPE {
+ Reserved = 0,
+ MassStorageDevice = 1,
+ NetworkInterfaceController = 2,
+ DisplayController = 3,
+ MultimediaController = 4,
+ MemoryController = 5,
+ BridgeController = 6,
+ CommunicationsDevice = 7,
+ SystemPeripheral = 8,
+ InputDevice = 9,
+ ServiceProcessor = 0x0A, /* 11/2/95 */
+ } PnP_BASE_TYPE;
+
+/* Device Sub Type Codes */
+
+typedef enum _PnP_SUB_TYPE {
+ SCSIController = 0,
+ IDEController = 1,
+ FloppyController = 2,
+ IPIController = 3,
+ OtherMassStorageController = 0x80,
+
+ EthernetController = 0,
+ TokenRingController = 1,
+ FDDIController = 2,
+ OtherNetworkController = 0x80,
+
+ VGAController= 0,
+ SVGAController= 1,
+ XGAController= 2,
+ OtherDisplayController = 0x80,
+
+ VideoController = 0,
+ AudioController = 1,
+ OtherMultimediaController = 0x80,
+
+ RAM = 0,
+ FLASH = 1,
+ OtherMemoryDevice = 0x80,
+
+ HostProcessorBridge = 0,
+ ISABridge = 1,
+ EISABridge = 2,
+ MicroChannelBridge = 3,
+ PCIBridge = 4,
+ PCMCIABridge = 5,
+ VMEBridge = 6,
+ OtherBridgeDevice = 0x80,
+
+ RS232Device = 0,
+ ATCompatibleParallelPort = 1,
+ OtherCommunicationsDevice = 0x80,
+
+ ProgrammableInterruptController = 0,
+ DMAController = 1,
+ SystemTimer = 2,
+ RealTimeClock = 3,
+ L2Cache = 4,
+ NVRAM = 5,
+ PowerManagement = 6,
+ CMOS = 7,
+ OperatorPanel = 8,
+ ServiceProcessorClass1 = 9,
+ ServiceProcessorClass2 = 0xA,
+ ServiceProcessorClass3 = 0xB,
+ GraphicAssist = 0xC,
+ SystemPlanar = 0xF, /* 10/5/95 */
+ OtherSystemPeripheral = 0x80,
+
+ KeyboardController = 0,
+ Digitizer = 1,
+ MouseController = 2,
+ TabletController = 3, /* 10/27/95 */
+ OtherInputController = 0x80,
+
+ GeneralMemoryController = 0,
+ } PnP_SUB_TYPE;
+
+/* Device Interface Type Codes */
+
+typedef enum _PnP_INTERFACE {
+ General = 0,
+ GeneralSCSI = 0,
+ GeneralIDE = 0,
+ ATACompatible = 1,
+
+ GeneralFloppy = 0,
+ Compatible765 = 1,
+ NS398_Floppy = 2, /* NS Super I/O wired to use index
+ register at port 398 and data
+ register at port 399 */
+ NS26E_Floppy = 3, /* Ports 26E and 26F */
+ NS15C_Floppy = 4, /* Ports 15C and 15D */
+ NS2E_Floppy = 5, /* Ports 2E and 2F */
+ CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */
+
+ GeneralIPI = 0,
+
+ GeneralEther = 0,
+ GeneralToken = 0,
+ GeneralFDDI = 0,
+
+ GeneralVGA = 0,
+ GeneralSVGA = 0,
+ GeneralXGA = 0,
+
+ GeneralVideo = 0,
+ GeneralAudio = 0,
+ CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */
+
+ GeneralRAM = 0,
+ GeneralFLASH = 0,
+ PCIMemoryController = 0, /* PCI Config Method */
+ RS6KMemoryController = 1, /* RS6K Config Method */
+
+ GeneralHostBridge = 0,
+ GeneralISABridge = 0,
+ GeneralEISABridge = 0,
+ GeneralMCABridge = 0,
+ GeneralPCIBridge = 0,
+ PCIBridgeDirect = 0,
+ PCIBridgeIndirect = 1,
+ PCIBridgeRS6K = 2,
+ GeneralPCMCIABridge = 0,
+ GeneralVMEBridge = 0,
+
+ GeneralRS232 = 0,
+ COMx = 1,
+ Compatible16450 = 2,
+ Compatible16550 = 3,
+ NS398SerPort = 4, /* NS Super I/O wired to use index
+ register at port 398 and data
+ register at port 399 */
+ NS26ESerPort = 5, /* Ports 26E and 26F */
+ NS15CSerPort = 6, /* Ports 15C and 15D */
+ NS2ESerPort = 7, /* Ports 2E and 2F */
+
+ GeneralParPort = 0,
+ LPTx = 1,
+ NS398ParPort = 2, /* NS Super I/O wired to use index
+ register at port 398 and data
+ register at port 399 */
+ NS26EParPort = 3, /* Ports 26E and 26F */
+ NS15CParPort = 4, /* Ports 15C and 15D */
+ NS2EParPort = 5, /* Ports 2E and 2F */
+
+ GeneralPIC = 0,
+ ISA_PIC = 1,
+ EISA_PIC = 2,
+ MPIC = 3,
+ RS6K_PIC = 4,
+
+ GeneralDMA = 0,
+ ISA_DMA = 1,
+ EISA_DMA = 2,
+
+ GeneralTimer = 0,
+ ISA_Timer = 1,
+ EISA_Timer = 2,
+ GeneralRTC = 0,
+ ISA_RTC = 1,
+
+ StoreThruOnly = 1,
+ StoreInEnabled = 2,
+ RS6KL2Cache = 3,
+
+ IndirectNVRAM = 0, /* Indirectly addressed */
+ DirectNVRAM = 1, /* Memory Mapped */
+ IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */
+
+ GeneralPowerManagement = 0,
+ EPOWPowerManagement = 1,
+ PowerControl = 2, // d1378
+
+ GeneralCMOS = 0,
+
+ GeneralOPPanel = 0,
+ HarddiskLight = 1,
+ CDROMLight = 2,
+ PowerLight = 3,
+ KeyLock = 4,
+ ANDisplay = 5, /* AlphaNumeric Display */
+ SystemStatusLED = 6, /* 3 digit 7 segment LED */
+ CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */
+
+ GeneralServiceProcessor = 0,
+
+ TransferData = 1,
+ IGMC32 = 2,
+ IGMC64 = 3,
+
+ GeneralSystemPlanar = 0, /* 10/5/95 */
+
+ } PnP_INTERFACE;
+
+/* PnP resources */
+
+/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */
+
+typedef struct _SERIAL_ID {
+ unsigned char VendorID0; /* Bit(7)=0 */
+ /* Bits(6:2)=1st character in */
+ /* compressed ASCII */
+ /* Bits(1:0)=2nd character in */
+ /* compressed ASCII bits(4:3) */
+ unsigned char VendorID1; /* Bits(7:5)=2nd character in */
+ /* compressed ASCII bits(2:0) */
+ /* Bits(4:0)=3rd character in */
+ /* compressed ASCII */
+ unsigned char VendorID2; /* Product number - vendor assigned */
+ unsigned char VendorID3; /* Product number - vendor assigned */
+
+/* Serial number is to provide uniqueness if more than one board of same */
+/* type is in system. Must be "FFFFFFFF" if feature not supported. */
+
+ unsigned char Serial0; /* Unique serial number bits (7:0) */
+ unsigned char Serial1; /* Unique serial number bits (15:8) */
+ unsigned char Serial2; /* Unique serial number bits (23:16) */
+ unsigned char Serial3; /* Unique serial number bits (31:24) */
+ unsigned char Checksum;
+ } SERIAL_ID;
+
+typedef enum _PnPItemName {
+ Unused = 0,
+ PnPVersion = 1,
+ LogicalDevice = 2,
+ CompatibleDevice = 3,
+ IRQFormat = 4,
+ DMAFormat = 5,
+ StartDepFunc = 6,
+ EndDepFunc = 7,
+ IOPort = 8,
+ FixedIOPort = 9,
+ Res1 = 10,
+ Res2 = 11,
+ Res3 = 12,
+ SmallVendorItem = 14,
+ EndTag = 15,
+ MemoryRange = 1,
+ ANSIIdentifier = 2,
+ UnicodeIdentifier = 3,
+ LargeVendorItem = 4,
+ MemoryRange32 = 5,
+ MemoryRangeFixed32 = 6,
+ } PnPItemName;
+
+/* Define a bunch of access functions for the bits in the tag field */
+
+/* Tag type - 0 = small; 1 = large */
+#define tag_type(t) (((t) & 0x80)>>7)
+#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7))
+
+/* Small item name is 4 bits - one of PnPItemName enum above */
+#define tag_small_item_name(t) (((t) & 0x78)>>3)
+#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3))
+
+/* Small item count is 3 bits - count of further bytes in packet */
+#define tag_small_count(t) ((t) & 0x07)
+#define set_tag_count(t,v) (t = (t & 0x78) | (v))
+
+/* Large item name is 7 bits - one of PnPItemName enum above */
+#define tag_large_item_name(t) ((t) & 0x7f)
+#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v))
+
+/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */
+
+typedef union _PnP_TAG_PACKET {
+ struct _S1_Pack{ /* VERSION PACKET */
+ unsigned char Tag; /* small tag = 0x0a */
+ unsigned char Version[2]; /* PnP version, Vendor version */
+ } S1_Pack;
+
+ struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */
+ unsigned char Tag; /* small tag = 0x15 or 0x16 */
+ unsigned char DevId[4]; /* Logical device id */
+ unsigned char Flags[2]; /* bit(0) boot device; */
+ /* bit(7:1) cmd in range x31-x37 */
+ /* bit(7:0) cmd in range x28-x3f (opt)*/
+ } S2_Pack;
+
+ struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */
+ unsigned char Tag; /* small tag = 0x1c */
+ unsigned char CompatId[4]; /* Compatible device id */
+ } S3_Pack;
+
+ struct _S4_Pack{ /* IRQ PACKET */
+ unsigned char Tag; /* small tag = 0x22 or 0x23 */
+ unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */
+ /* bit(0) is IRQ8 ... */
+ unsigned char IRQInfo; /* optional; assume bit(0)=1; else */
+ /* bit(0) - high true edge sensitive */
+ /* bit(1) - low true edge sensitive */
+ /* bit(2) - high true level sensitive*/
+ /* bit(3) - low true level sensitive */
+ /* bit(7:4) - must be 0 */
+ } S4_Pack;
+
+ struct _S5_Pack{ /* DMA PACKET */
+ unsigned char Tag; /* small tag = 0x2a */
+ unsigned char DMAMask; /* bit(0) is channel 0 ... */
+ unsigned char DMAInfo;
+ } S5_Pack;
+
+ struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */
+ unsigned char Tag; /* small tag = 0x30 or 0x31 */
+ unsigned char Priority; /* Optional; if missing then x01; else*/
+ /* x00 = best possible */
+ /* x01 = acceptible */
+ /* x02 = sub-optimal but functional */
+ } S6_Pack;
+
+ struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */
+ unsigned char Tag; /* small tag = 0x38 */
+ } S7_Pack;
+
+ struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */
+ unsigned char Tag; /* small tag x47 */
+ unsigned char IOInfo; /* x0 = decode only bits(9:0); */
+#define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */
+ unsigned char RangeMin[2]; /* Min base address */
+ unsigned char RangeMax[2]; /* Max base address */
+ unsigned char IOAlign; /* base alignmt, incr in 1B blocks */
+ unsigned char IONum; /* number of contiguous I/O ports */
+ } S8_Pack;
+
+ struct _S9_Pack{ /* FIXED I/O PORT PACKET */
+ unsigned char Tag; /* small tag = 0x4b */
+ unsigned char Range[2]; /* base address 10 bits */
+ unsigned char IONum; /* number of contiguous I/O ports */
+ } S9_Pack;
+
+ struct _S14_Pack{ /* VENDOR DEFINED PACKET */
+ unsigned char Tag; /* small tag = 0x7m m = 1-7 */
+ union _S14_Data{
+ unsigned char Data[7]; /* Vendor defined */
+ struct _S14_PPCPack{ /* Pr*p s14 pack */
+ unsigned char Type; /* 00=non-IBM */
+ unsigned char PPCData[6]; /* Vendor defined */
+ } S14_PPCPack;
+ } S14_Data;
+ } S14_Pack;
+
+ struct _S15_Pack{ /* END PACKET */
+ unsigned char Tag; /* small tag = 0x78 or 0x79 */
+ unsigned char Check; /* optional - checksum */
+ } S15_Pack;
+
+ struct _L1_Pack{ /* MEMORY RANGE PACKET */
+ unsigned char Tag; /* large tag = 0x81 */
+ unsigned char Count0; /* x09 */
+ unsigned char Count1; /* x00 */
+ unsigned char Data[9]; /* a variable array of bytes, */
+ /* count in tag */
+ } L1_Pack;
+
+ struct _L2_Pack{ /* ANSI ID STRING PACKET */
+ unsigned char Tag; /* large tag = 0x82 */
+ unsigned char Count0; /* Length of string */
+ unsigned char Count1;
+ unsigned char Identifier[1]; /* a variable array of bytes, */
+ /* count in tag */
+ } L2_Pack;
+
+ struct _L3_Pack{ /* UNICODE ID STRING PACKET */
+ unsigned char Tag; /* large tag = 0x83 */
+ unsigned char Count0; /* Length + 2 of string */
+ unsigned char Count1;
+ unsigned char Country0; /* TBD */
+ unsigned char Country1; /* TBD */
+ unsigned char Identifier[1]; /* a variable array of bytes, */
+ /* count in tag */
+ } L3_Pack;
+
+ struct _L4_Pack{ /* VENDOR DEFINED PACKET */
+ unsigned char Tag; /* large tag = 0x84 */
+ unsigned char Count0;
+ unsigned char Count1;
+ union _L4_Data{
+ unsigned char Data[1]; /* a variable array of bytes, */
+ /* count in tag */
+ struct _L4_PPCPack{ /* Pr*p L4 packet */
+ unsigned char Type; /* 00=non-IBM */
+ unsigned char PPCData[1]; /* a variable array of bytes, */
+ /* count in tag */
+ } L4_PPCPack;
+ } L4_Data;
+ } L4_Pack;
+
+ struct _L5_Pack{
+ unsigned char Tag; /* large tag = 0x85 */
+ unsigned char Count0; /* Count = 17 */
+ unsigned char Count1;
+ unsigned char Data[17];
+ } L5_Pack;
+
+ struct _L6_Pack{
+ unsigned char Tag; /* large tag = 0x86 */
+ unsigned char Count0; /* Count = 9 */
+ unsigned char Count1;
+ unsigned char Data[9];
+ } L6_Pack;
+
+ } PnP_TAG_PACKET;
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* ASM_POWERPC_PNP_H */
diff --git a/include/asm-ppc/pnp.h b/include/asm-ppc/pnp.h
deleted file mode 100644
index 6f6760b..0000000
--- a/include/asm-ppc/pnp.h
+++ /dev/null
@@ -1,645 +0,0 @@
-#ifdef __KERNEL__
-/* 11/02/95 */
-/*----------------------------------------------------------------------------*/
-/* Plug and Play header definitions */
-/*----------------------------------------------------------------------------*/
-
-/* Structure map for PnP on PowerPC Reference Platform */
-/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */
-/* (or later versions) is available on Compuserve in the PLUGPLAY area. */
-/* This code has extensions to that specification, namely new short and */
-/* long tag types for platform dependent information */
-
-/* Warning: LE notation used throughout this file */
-
-/* For enum's: if given in hex then they are bit significant, i.e. */
-/* only one bit is on for each enum */
-
-#ifndef _PNP_
-#define _PNP_
-
-#ifndef __ASSEMBLY__
-#define MAX_MEM_REGISTERS 9
-#define MAX_IO_PORTS 20
-#define MAX_IRQS 7
-/*#define MAX_DMA_CHANNELS 7*/
-
-/* Interrupt controllers */
-
-#define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */
-#define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */
-#define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */
-#define PNPinterrupt3 "PNP0003" /* APIC */
-#define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */
-
-/* Timers */
-
-#define PNPtimer0 "PNP0100" /* AT Timer */
-#define PNPtimer1 "PNP0101" /* EISA Timer */
-#define PNPtimer2 "PNP0102" /* MCA Timer */
-
-/* DMA controllers */
-
-#define PNPdma0 "PNP0200" /* AT DMA Controller */
-#define PNPdma1 "PNP0201" /* EISA DMA Controller */
-#define PNPdma2 "PNP0202" /* MCA DMA Controller */
-
-/* start of August 15, 1994 additions */
-/* CMOS */
-#define PNPCMOS "IBM0009" /* CMOS */
-
-/* L2 Cache */
-#define PNPL2 "IBM0007" /* L2 Cache */
-
-/* NVRAM */
-#define PNPNVRAM "IBM0008" /* NVRAM */
-
-/* Power Management */
-#define PNPPM "IBM0005" /* Power Management */
-/* end of August 15, 1994 additions */
-
-/* Keyboards */
-
-#define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */
-#define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */
-#define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */
-#define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */
-#define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */
-#define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */
-#define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */
-#define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */
-
-/* Parallel port controllers */
-
-#define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */
-#define PNPparallel1 "PNP0401" /* ECP Parallel Port */
-#define PNPepp "IBM001C" /* EPP Parallel Port */
-
-/* Serial port controllers */
-
-#define PNPserial0 "PNP0500" /* Standard PC Serial port */
-#define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */
-
-/* Disk controllers */
-
-#define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */
-#define PNPdisk1 "PNP0601" /* Plus Hardcard II */
-#define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */
-
-/* Diskette controllers */
-
-#define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */
-
-/* Display controllers */
-
-#define PNPdisplay0 "PNP0900" /* VGA Compatible */
-#define PNPdisplay1 "PNP0901" /* Video Seven VGA */
-#define PNPdisplay2 "PNP0902" /* 8514/A Compatible */
-#define PNPdisplay3 "PNP0903" /* Trident VGA */
-#define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */
-#define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */
-#define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */
-#define PNPdisplay7 "PNP0907" /* Western Digital VGA */
-#define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */
-#define PNPdisplay9 "PNP0909" /* S3 */
-#define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */
-#define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */
-#define PNPdisplayC "PNP090C" /* XGA Compatible */
-#define PNPdisplayD "PNP090D" /* ATI VGA Wonder */
-#define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */
-#define PNPdisplayF "PNP090F" /* Oak Technology VGA */
-
-/* Peripheral busses */
-
-#define PNPbuses0 "PNP0A00" /* ISA Bus */
-#define PNPbuses1 "PNP0A01" /* EISA Bus */
-#define PNPbuses2 "PNP0A02" /* MCA Bus */
-#define PNPbuses3 "PNP0A03" /* PCI Bus */
-#define PNPbuses4 "PNP0A04" /* VESA/VL Bus */
-
-/* RTC, BIOS, planar devices */
-
-#define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */
-#define PNPrtc0 "PNP0B00" /* AT RTC */
-#define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */
-#define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */
-#define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */
-#define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */
-
-/* PCMCIA controller */
-
-#define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */
-
-/* Mice */
-
-#define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */
-#define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */
-#define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */
-#define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */
-#define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */
-#define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */
-#define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */
-#define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */
-#define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */
-#define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */
-#define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */
-#define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */
-
-/* Modems */
-
-#define PNPmodem0 "PNP9000" /* Specific IDs TBD */
-
-/* Network controllers */
-
-#define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */
-#define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */
-#define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */
-#define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */
-#define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */
-#define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */
-#define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */
-#define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */
-
-/* SCSI controllers */
-
-#define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */
-#define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */
-#define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/
-#define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */
-#define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */
-#define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */
-#define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */
-
-/* Sound/Video, Multimedia */
-
-#define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */
-#define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */
-#define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */
-#define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */
-#define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */
-#define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */
-#define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */
-#define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */
-
-/* Operator Panel */
-#define PNPopctl "IBM000B" /* Operator's panel */
-
-/* Service Processor */
-#define PNPsp "IBM0011" /* IBM Service Processor */
-#define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */
-#define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */
-
-/* Memory Controller */
-#define PNPmemctl "IBM000A" /* Memory controller */
-
-/* Graphics Assist */
-#define PNPg_assist "IBM0014" /* Graphics Assist */
-
-/* Miscellaneous Device Controllers */
-#define PNPtablet "IBM0019" /* IBM Tablet Controller */
-
-/* PNP Packet Handles */
-
-#define S1_Packet 0x0A /* Version resource */
-#define S2_Packet 0x15 /* Logical DEVID (without flags) */
-#define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */
-#define S3_Packet 0x1C /* Compatible device ID */
-#define S4_Packet 0x22 /* IRQ resource (without flags) */
-#define S4_Packet_flags 0x23 /* IRQ resource (with flags) */
-#define S5_Packet 0x2A /* DMA resource */
-#define S6_Packet 0x30 /* Depend funct start (w/o priority) */
-#define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */
-#define S7_Packet 0x38 /* Depend funct end */
-#define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */
-#define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */
-#define S14_Packet 0x71 /* Vendor defined */
-#define S15_Packet 0x78 /* End of resource (w/o checksum) */
-#define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */
-#define L1_Packet 0x81 /* Memory range */
-#define L1_Shadow 0x20 /* Memory is shadowable */
-#define L1_32bit_mem 0x18 /* 32-bit memory only */
-#define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */
-#define L1_Decode_Hi 0x04 /* decode supports high address */
-#define L1_Cache 0x02 /* read cacheable, write-through */
-#define L1_Writeable 0x01 /* Memory is writeable */
-#define L2_Packet 0x82 /* ANSI ID string */
-#define L3_Packet 0x83 /* Unicode ID string */
-#define L4_Packet 0x84 /* Vendor defined */
-#define L5_Packet 0x85 /* Large I/O */
-#define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */
-#define END_TAG 0x78 /* End of resource */
-#define DF_START_TAG 0x30 /* Dependent function start */
-#define DF_START_TAG_priority 0x31 /* Dependent function start */
-#define DF_END_TAG 0x38 /* Dependent function end */
-#define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */
-
-/* Device Base Type Codes */
-
-typedef enum _PnP_BASE_TYPE {
- Reserved = 0,
- MassStorageDevice = 1,
- NetworkInterfaceController = 2,
- DisplayController = 3,
- MultimediaController = 4,
- MemoryController = 5,
- BridgeController = 6,
- CommunicationsDevice = 7,
- SystemPeripheral = 8,
- InputDevice = 9,
- ServiceProcessor = 0x0A, /* 11/2/95 */
- } PnP_BASE_TYPE;
-
-/* Device Sub Type Codes */
-
-typedef enum _PnP_SUB_TYPE {
- SCSIController = 0,
- IDEController = 1,
- FloppyController = 2,
- IPIController = 3,
- OtherMassStorageController = 0x80,
-
- EthernetController = 0,
- TokenRingController = 1,
- FDDIController = 2,
- OtherNetworkController = 0x80,
-
- VGAController= 0,
- SVGAController= 1,
- XGAController= 2,
- OtherDisplayController = 0x80,
-
- VideoController = 0,
- AudioController = 1,
- OtherMultimediaController = 0x80,
-
- RAM = 0,
- FLASH = 1,
- OtherMemoryDevice = 0x80,
-
- HostProcessorBridge = 0,
- ISABridge = 1,
- EISABridge = 2,
- MicroChannelBridge = 3,
- PCIBridge = 4,
- PCMCIABridge = 5,
- VMEBridge = 6,
- OtherBridgeDevice = 0x80,
-
- RS232Device = 0,
- ATCompatibleParallelPort = 1,
- OtherCommunicationsDevice = 0x80,
-
- ProgrammableInterruptController = 0,
- DMAController = 1,
- SystemTimer = 2,
- RealTimeClock = 3,
- L2Cache = 4,
- NVRAM = 5,
- PowerManagement = 6,
- CMOS = 7,
- OperatorPanel = 8,
- ServiceProcessorClass1 = 9,
- ServiceProcessorClass2 = 0xA,
- ServiceProcessorClass3 = 0xB,
- GraphicAssist = 0xC,
- SystemPlanar = 0xF, /* 10/5/95 */
- OtherSystemPeripheral = 0x80,
-
- KeyboardController = 0,
- Digitizer = 1,
- MouseController = 2,
- TabletController = 3, /* 10/27/95 */
- OtherInputController = 0x80,
-
- GeneralMemoryController = 0,
- } PnP_SUB_TYPE;
-
-/* Device Interface Type Codes */
-
-typedef enum _PnP_INTERFACE {
- General = 0,
- GeneralSCSI = 0,
- GeneralIDE = 0,
- ATACompatible = 1,
-
- GeneralFloppy = 0,
- Compatible765 = 1,
- NS398_Floppy = 2, /* NS Super I/O wired to use index
- register at port 398 and data
- register at port 399 */
- NS26E_Floppy = 3, /* Ports 26E and 26F */
- NS15C_Floppy = 4, /* Ports 15C and 15D */
- NS2E_Floppy = 5, /* Ports 2E and 2F */
- CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */
-
- GeneralIPI = 0,
-
- GeneralEther = 0,
- GeneralToken = 0,
- GeneralFDDI = 0,
-
- GeneralVGA = 0,
- GeneralSVGA = 0,
- GeneralXGA = 0,
-
- GeneralVideo = 0,
- GeneralAudio = 0,
- CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */
-
- GeneralRAM = 0,
- GeneralFLASH = 0,
- PCIMemoryController = 0, /* PCI Config Method */
- RS6KMemoryController = 1, /* RS6K Config Method */
-
- GeneralHostBridge = 0,
- GeneralISABridge = 0,
- GeneralEISABridge = 0,
- GeneralMCABridge = 0,
- GeneralPCIBridge = 0,
- PCIBridgeDirect = 0,
- PCIBridgeIndirect = 1,
- PCIBridgeRS6K = 2,
- GeneralPCMCIABridge = 0,
- GeneralVMEBridge = 0,
-
- GeneralRS232 = 0,
- COMx = 1,
- Compatible16450 = 2,
- Compatible16550 = 3,
- NS398SerPort = 4, /* NS Super I/O wired to use index
- register at port 398 and data
- register at port 399 */
- NS26ESerPort = 5, /* Ports 26E and 26F */
- NS15CSerPort = 6, /* Ports 15C and 15D */
- NS2ESerPort = 7, /* Ports 2E and 2F */
-
- GeneralParPort = 0,
- LPTx = 1,
- NS398ParPort = 2, /* NS Super I/O wired to use index
- register at port 398 and data
- register at port 399 */
- NS26EParPort = 3, /* Ports 26E and 26F */
- NS15CParPort = 4, /* Ports 15C and 15D */
- NS2EParPort = 5, /* Ports 2E and 2F */
-
- GeneralPIC = 0,
- ISA_PIC = 1,
- EISA_PIC = 2,
- MPIC = 3,
- RS6K_PIC = 4,
-
- GeneralDMA = 0,
- ISA_DMA = 1,
- EISA_DMA = 2,
-
- GeneralTimer = 0,
- ISA_Timer = 1,
- EISA_Timer = 2,
- GeneralRTC = 0,
- ISA_RTC = 1,
-
- StoreThruOnly = 1,
- StoreInEnabled = 2,
- RS6KL2Cache = 3,
-
- IndirectNVRAM = 0, /* Indirectly addressed */
- DirectNVRAM = 1, /* Memory Mapped */
- IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */
-
- GeneralPowerManagement = 0,
- EPOWPowerManagement = 1,
- PowerControl = 2, // d1378
-
- GeneralCMOS = 0,
-
- GeneralOPPanel = 0,
- HarddiskLight = 1,
- CDROMLight = 2,
- PowerLight = 3,
- KeyLock = 4,
- ANDisplay = 5, /* AlphaNumeric Display */
- SystemStatusLED = 6, /* 3 digit 7 segment LED */
- CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */
-
- GeneralServiceProcessor = 0,
-
- TransferData = 1,
- IGMC32 = 2,
- IGMC64 = 3,
-
- GeneralSystemPlanar = 0, /* 10/5/95 */
-
- } PnP_INTERFACE;
-
-/* PnP resources */
-
-/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */
-
-typedef struct _SERIAL_ID {
- unsigned char VendorID0; /* Bit(7)=0 */
- /* Bits(6:2)=1st character in */
- /* compressed ASCII */
- /* Bits(1:0)=2nd character in */
- /* compressed ASCII bits(4:3) */
- unsigned char VendorID1; /* Bits(7:5)=2nd character in */
- /* compressed ASCII bits(2:0) */
- /* Bits(4:0)=3rd character in */
- /* compressed ASCII */
- unsigned char VendorID2; /* Product number - vendor assigned */
- unsigned char VendorID3; /* Product number - vendor assigned */
-
-/* Serial number is to provide uniqueness if more than one board of same */
-/* type is in system. Must be "FFFFFFFF" if feature not supported. */
-
- unsigned char Serial0; /* Unique serial number bits (7:0) */
- unsigned char Serial1; /* Unique serial number bits (15:8) */
- unsigned char Serial2; /* Unique serial number bits (23:16) */
- unsigned char Serial3; /* Unique serial number bits (31:24) */
- unsigned char Checksum;
- } SERIAL_ID;
-
-typedef enum _PnPItemName {
- Unused = 0,
- PnPVersion = 1,
- LogicalDevice = 2,
- CompatibleDevice = 3,
- IRQFormat = 4,
- DMAFormat = 5,
- StartDepFunc = 6,
- EndDepFunc = 7,
- IOPort = 8,
- FixedIOPort = 9,
- Res1 = 10,
- Res2 = 11,
- Res3 = 12,
- SmallVendorItem = 14,
- EndTag = 15,
- MemoryRange = 1,
- ANSIIdentifier = 2,
- UnicodeIdentifier = 3,
- LargeVendorItem = 4,
- MemoryRange32 = 5,
- MemoryRangeFixed32 = 6,
- } PnPItemName;
-
-/* Define a bunch of access functions for the bits in the tag field */
-
-/* Tag type - 0 = small; 1 = large */
-#define tag_type(t) (((t) & 0x80)>>7)
-#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7))
-
-/* Small item name is 4 bits - one of PnPItemName enum above */
-#define tag_small_item_name(t) (((t) & 0x78)>>3)
-#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3))
-
-/* Small item count is 3 bits - count of further bytes in packet */
-#define tag_small_count(t) ((t) & 0x07)
-#define set_tag_count(t,v) (t = (t & 0x78) | (v))
-
-/* Large item name is 7 bits - one of PnPItemName enum above */
-#define tag_large_item_name(t) ((t) & 0x7f)
-#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v))
-
-/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */
-
-typedef union _PnP_TAG_PACKET {
- struct _S1_Pack{ /* VERSION PACKET */
- unsigned char Tag; /* small tag = 0x0a */
- unsigned char Version[2]; /* PnP version, Vendor version */
- } S1_Pack;
-
- struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */
- unsigned char Tag; /* small tag = 0x15 or 0x16 */
- unsigned char DevId[4]; /* Logical device id */
- unsigned char Flags[2]; /* bit(0) boot device; */
- /* bit(7:1) cmd in range x31-x37 */
- /* bit(7:0) cmd in range x28-x3f (opt)*/
- } S2_Pack;
-
- struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */
- unsigned char Tag; /* small tag = 0x1c */
- unsigned char CompatId[4]; /* Compatible device id */
- } S3_Pack;
-
- struct _S4_Pack{ /* IRQ PACKET */
- unsigned char Tag; /* small tag = 0x22 or 0x23 */
- unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */
- /* bit(0) is IRQ8 ... */
- unsigned char IRQInfo; /* optional; assume bit(0)=1; else */
- /* bit(0) - high true edge sensitive */
- /* bit(1) - low true edge sensitive */
- /* bit(2) - high true level sensitive*/
- /* bit(3) - low true level sensitive */
- /* bit(7:4) - must be 0 */
- } S4_Pack;
-
- struct _S5_Pack{ /* DMA PACKET */
- unsigned char Tag; /* small tag = 0x2a */
- unsigned char DMAMask; /* bit(0) is channel 0 ... */
- unsigned char DMAInfo;
- } S5_Pack;
-
- struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */
- unsigned char Tag; /* small tag = 0x30 or 0x31 */
- unsigned char Priority; /* Optional; if missing then x01; else*/
- /* x00 = best possible */
- /* x01 = acceptible */
- /* x02 = sub-optimal but functional */
- } S6_Pack;
-
- struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */
- unsigned char Tag; /* small tag = 0x38 */
- } S7_Pack;
-
- struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */
- unsigned char Tag; /* small tag x47 */
- unsigned char IOInfo; /* x0 = decode only bits(9:0); */
-#define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */
- unsigned char RangeMin[2]; /* Min base address */
- unsigned char RangeMax[2]; /* Max base address */
- unsigned char IOAlign; /* base alignmt, incr in 1B blocks */
- unsigned char IONum; /* number of contiguous I/O ports */
- } S8_Pack;
-
- struct _S9_Pack{ /* FIXED I/O PORT PACKET */
- unsigned char Tag; /* small tag = 0x4b */
- unsigned char Range[2]; /* base address 10 bits */
- unsigned char IONum; /* number of contiguous I/O ports */
- } S9_Pack;
-
- struct _S14_Pack{ /* VENDOR DEFINED PACKET */
- unsigned char Tag; /* small tag = 0x7m m = 1-7 */
- union _S14_Data{
- unsigned char Data[7]; /* Vendor defined */
- struct _S14_PPCPack{ /* Pr*p s14 pack */
- unsigned char Type; /* 00=non-IBM */
- unsigned char PPCData[6]; /* Vendor defined */
- } S14_PPCPack;
- } S14_Data;
- } S14_Pack;
-
- struct _S15_Pack{ /* END PACKET */
- unsigned char Tag; /* small tag = 0x78 or 0x79 */
- unsigned char Check; /* optional - checksum */
- } S15_Pack;
-
- struct _L1_Pack{ /* MEMORY RANGE PACKET */
- unsigned char Tag; /* large tag = 0x81 */
- unsigned char Count0; /* x09 */
- unsigned char Count1; /* x00 */
- unsigned char Data[9]; /* a variable array of bytes, */
- /* count in tag */
- } L1_Pack;
-
- struct _L2_Pack{ /* ANSI ID STRING PACKET */
- unsigned char Tag; /* large tag = 0x82 */
- unsigned char Count0; /* Length of string */
- unsigned char Count1;
- unsigned char Identifier[1]; /* a variable array of bytes, */
- /* count in tag */
- } L2_Pack;
-
- struct _L3_Pack{ /* UNICODE ID STRING PACKET */
- unsigned char Tag; /* large tag = 0x83 */
- unsigned char Count0; /* Length + 2 of string */
- unsigned char Count1;
- unsigned char Country0; /* TBD */
- unsigned char Country1; /* TBD */
- unsigned char Identifier[1]; /* a variable array of bytes, */
- /* count in tag */
- } L3_Pack;
-
- struct _L4_Pack{ /* VENDOR DEFINED PACKET */
- unsigned char Tag; /* large tag = 0x84 */
- unsigned char Count0;
- unsigned char Count1;
- union _L4_Data{
- unsigned char Data[1]; /* a variable array of bytes, */
- /* count in tag */
- struct _L4_PPCPack{ /* Pr*p L4 packet */
- unsigned char Type; /* 00=non-IBM */
- unsigned char PPCData[1]; /* a variable array of bytes, */
- /* count in tag */
- } L4_PPCPack;
- } L4_Data;
- } L4_Pack;
-
- struct _L5_Pack{
- unsigned char Tag; /* large tag = 0x85 */
- unsigned char Count0; /* Count = 17 */
- unsigned char Count1;
- unsigned char Data[17];
- } L5_Pack;
-
- struct _L6_Pack{
- unsigned char Tag; /* large tag = 0x86 */
- unsigned char Count0; /* Count = 9 */
- unsigned char Count1;
- unsigned char Data[9];
- } L6_Pack;
-
- } PnP_TAG_PACKET;
-
-#endif /* __ASSEMBLY__ */
-#endif /* ndef _PNP_ */
-#endif /* __KERNEL__ */
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 07/15] powerpc: move asm/amigappc.h
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
` (5 preceding siblings ...)
2006-04-05 5:10 ` [PATCH 06/15] powerpc: moce asm/pnp.h sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 5:10 ` [PATCH 08/15] powerpc: move asm/open_pic.h sfr
` (8 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/amigappc.h | 84 ++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/amigappc.h | 85 ----------------------------------------
2 files changed, 84 insertions(+), 85 deletions(-)
create mode 100644 include/asm-powerpc/amigappc.h
delete mode 100644 include/asm-ppc/amigappc.h
a53c21d9d235cc02ab34d696d1440a1ceda1e3d7
diff --git a/include/asm-powerpc/amigappc.h b/include/asm-powerpc/amigappc.h
new file mode 100644
index 0000000..e7f9c33
--- /dev/null
+++ b/include/asm-powerpc/amigappc.h
@@ -0,0 +1,84 @@
+#ifndef _ASM_POWERPC_AMIGAPPC_H
+#define _ASM_POWERPC_AMIGAPPC_H
+/*
+** This header defines some values and pointers for the Phase 5 PowerUp card.
+**
+** Copyright 1997, 1998 by Phase5, Germany.
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created: 7/22/97 by Jesper Skov
+*/
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+/* #include <asm/system.h> */
+#define mb() __asm__ __volatile__ ("sync" : : : "memory")
+
+#define APUS_WRITE(_a_, _v_) \
+do { \
+ (*((volatile unsigned char *)(_a_)) = (_v_)); \
+ mb(); \
+} while (0)
+
+#define APUS_READ(_a_, _v_) \
+do { \
+ (_v_) = (*((volatile unsigned char *)(_a_))); \
+ mb(); \
+} while (0)
+#endif /* ndef __ASSEMBLY__ */
+
+/* Maybe add a [#ifdef WANT_ZTWOBASE] condition to amigahw.h? */
+#define zTwoBase (0x80000000)
+
+#define APUS_IPL_BASE (zTwoBase + 0x00f60000)
+#define APUS_REG_RESET (APUS_IPL_BASE + 0x00)
+#define APUS_REG_WAITSTATE (APUS_IPL_BASE + 0x10)
+#define APUS_REG_SHADOW (APUS_IPL_BASE + 0x18)
+#define APUS_REG_LOCK (APUS_IPL_BASE + 0x20)
+#define APUS_REG_INT (APUS_IPL_BASE + 0x28)
+#define APUS_IPL_EMU (APUS_IPL_BASE + 0x30)
+#define APUS_INT_LVL (APUS_IPL_BASE + 0x38)
+
+#define REGSHADOW_SETRESET (0x80)
+#define REGSHADOW_SELFRESET (0x40)
+
+#define REGLOCK_SETRESET (0x80)
+#define REGLOCK_BLACKMAGICK1 (0x40)
+#define REGLOCK_BLACKMAGICK2 (0x20)
+#define REGLOCK_BLACKMAGICK3 (0x10)
+
+#define REGWAITSTATE_SETRESET (0x80)
+#define REGWAITSTATE_PPCW (0x08)
+#define REGWAITSTATE_PPCR (0x04)
+
+#define REGRESET_SETRESET (0x80)
+#define REGRESET_PPCRESET (0x10)
+#define REGRESET_M68KRESET (0x08)
+#define REGRESET_AMIGARESET (0x04)
+#define REGRESET_AUXRESET (0x02)
+#define REGRESET_SCSIRESET (0x01)
+
+#define REGINT_SETRESET (0x80)
+#define REGINT_ENABLEIPL (0x02)
+#define REGINT_INTMASTER (0x01)
+
+#define IPLEMU_SETRESET (0x80)
+#define IPLEMU_DISABLEINT (0x40)
+#define IPLEMU_IPL2 (0x20)
+#define IPLEMU_IPL1 (0x10)
+#define IPLEMU_IPL0 (0x08)
+#define IPLEMU_PPCIPL2 (0x04)
+#define IPLEMU_PPCIPL1 (0x02)
+#define IPLEMU_PPCIPL0 (0x01)
+#define IPLEMU_IPLMASK (IPLEMU_PPCIPL2|IPLEMU_PPCIPL1|IPLEMU_PPCIPL0)
+
+#define INTLVL_SETRESET (0x80)
+#define INTLVL_MASK (0x7f)
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_AMIGAPPC_H */
diff --git a/include/asm-ppc/amigappc.h b/include/asm-ppc/amigappc.h
deleted file mode 100644
index 35114ce..0000000
--- a/include/asm-ppc/amigappc.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
-** asm-ppc/amigappc.h -- This header defines some values and pointers for
-** the Phase 5 PowerUp card.
-**
-** Copyright 1997, 1998 by Phase5, Germany.
-**
-** This file is subject to the terms and conditions of the GNU General Public
-** License. See the file COPYING in the main directory of this archive
-** for more details.
-**
-** Created: 7/22/97 by Jesper Skov
-*/
-
-#ifdef __KERNEL__
-#ifndef _M68K_AMIGAPPC_H
-#define _M68K_AMIGAPPC_H
-
-#ifndef __ASSEMBLY__
-
-/* #include <asm/system.h> */
-#define mb() __asm__ __volatile__ ("sync" : : : "memory")
-
-#define APUS_WRITE(_a_, _v_) \
-do { \
- (*((volatile unsigned char *)(_a_)) = (_v_)); \
- mb(); \
-} while (0)
-
-#define APUS_READ(_a_, _v_) \
-do { \
- (_v_) = (*((volatile unsigned char *)(_a_))); \
- mb(); \
-} while (0)
-#endif /* ndef __ASSEMBLY__ */
-
-/* Maybe add a [#ifdef WANT_ZTWOBASE] condition to amigahw.h? */
-#define zTwoBase (0x80000000)
-
-#define APUS_IPL_BASE (zTwoBase + 0x00f60000)
-#define APUS_REG_RESET (APUS_IPL_BASE + 0x00)
-#define APUS_REG_WAITSTATE (APUS_IPL_BASE + 0x10)
-#define APUS_REG_SHADOW (APUS_IPL_BASE + 0x18)
-#define APUS_REG_LOCK (APUS_IPL_BASE + 0x20)
-#define APUS_REG_INT (APUS_IPL_BASE + 0x28)
-#define APUS_IPL_EMU (APUS_IPL_BASE + 0x30)
-#define APUS_INT_LVL (APUS_IPL_BASE + 0x38)
-
-#define REGSHADOW_SETRESET (0x80)
-#define REGSHADOW_SELFRESET (0x40)
-
-#define REGLOCK_SETRESET (0x80)
-#define REGLOCK_BLACKMAGICK1 (0x40)
-#define REGLOCK_BLACKMAGICK2 (0x20)
-#define REGLOCK_BLACKMAGICK3 (0x10)
-
-#define REGWAITSTATE_SETRESET (0x80)
-#define REGWAITSTATE_PPCW (0x08)
-#define REGWAITSTATE_PPCR (0x04)
-
-#define REGRESET_SETRESET (0x80)
-#define REGRESET_PPCRESET (0x10)
-#define REGRESET_M68KRESET (0x08)
-#define REGRESET_AMIGARESET (0x04)
-#define REGRESET_AUXRESET (0x02)
-#define REGRESET_SCSIRESET (0x01)
-
-#define REGINT_SETRESET (0x80)
-#define REGINT_ENABLEIPL (0x02)
-#define REGINT_INTMASTER (0x01)
-
-#define IPLEMU_SETRESET (0x80)
-#define IPLEMU_DISABLEINT (0x40)
-#define IPLEMU_IPL2 (0x20)
-#define IPLEMU_IPL1 (0x10)
-#define IPLEMU_IPL0 (0x08)
-#define IPLEMU_PPCIPL2 (0x04)
-#define IPLEMU_PPCIPL1 (0x02)
-#define IPLEMU_PPCIPL0 (0x01)
-#define IPLEMU_IPLMASK (IPLEMU_PPCIPL2|IPLEMU_PPCIPL1|IPLEMU_PPCIPL0)
-
-#define INTLVL_SETRESET (0x80)
-#define INTLVL_MASK (0x7f)
-
-#endif /* _M68k_AMIGAPPC_H */
-#endif /* __KERNEL__ */
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 08/15] powerpc: move asm/open_pic.h
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
` (6 preceding siblings ...)
2006-04-05 5:10 ` [PATCH 07/15] powerpc: move asm/amigappc.h sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 14:07 ` Kumar Gala
2006-04-05 5:10 ` [PATCH 09/15] powerpc: move asm/hydra.h sfr
` (7 subsequent siblings)
15 siblings, 1 reply; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/open_pic.h | 99 ++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/open_pic.h | 99 ----------------------------------------
2 files changed, 99 insertions(+), 99 deletions(-)
create mode 100644 include/asm-powerpc/open_pic.h
delete mode 100644 include/asm-ppc/open_pic.h
54316678b9e6aad8349f2df50dadd2597b675804
diff --git a/include/asm-powerpc/open_pic.h b/include/asm-powerpc/open_pic.h
new file mode 100644
index 0000000..3f197cf
--- /dev/null
+++ b/include/asm-powerpc/open_pic.h
@@ -0,0 +1,99 @@
+#ifndef _ASM_POWERPC_OPEN_PIC_H
+#define _ASM_POWERPC_OPEN_PIC_H
+
+/*
+ * include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling
+ *
+ * Copyright (C) 1997 Geert Uytterhoeven
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#include <linux/irq.h>
+
+#define OPENPIC_SIZE 0x40000
+
+/*
+ * Non-offset'ed vector numbers
+ */
+
+#define OPENPIC_VEC_TIMER 110 /* and up */
+#define OPENPIC_VEC_IPI 118 /* and up */
+#define OPENPIC_VEC_SPURIOUS 255
+
+/* Priorities */
+#define OPENPIC_PRIORITY_IPI_BASE 10
+#define OPENPIC_PRIORITY_DEFAULT 4
+#define OPENPIC_PRIORITY_NMI 9
+
+/* OpenPIC IRQ controller structure */
+extern struct hw_interrupt_type open_pic;
+
+/* OpenPIC IPI controller structure */
+#ifdef CONFIG_SMP
+extern struct hw_interrupt_type open_pic_ipi;
+#endif /* CONFIG_SMP */
+
+extern u_int OpenPIC_NumInitSenses;
+extern u_char *OpenPIC_InitSenses;
+extern void __iomem * OpenPIC_Addr;
+extern int epic_serial_mode;
+
+/* Exported functions */
+extern void openpic_set_sources(int first_irq, int num_irqs, void __iomem *isr);
+extern void openpic_init(int linux_irq_offset);
+extern void openpic_init_nmi_irq(u_int irq);
+extern void openpic_set_irq_priority(u_int irq, u_int pri);
+extern void openpic_hookup_cascade(u_int irq, char *name,
+ int (*cascade_fn)(struct pt_regs *));
+extern u_int openpic_irq(void);
+extern void openpic_eoi(void);
+extern void openpic_request_IPIs(void);
+extern void do_openpic_setup_cpu(void);
+extern int openpic_get_irq(struct pt_regs *regs);
+extern void openpic_reset_processor_phys(u_int cpumask);
+extern void openpic_setup_ISU(int isu_num, unsigned long addr);
+extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
+extern void smp_openpic_message_pass(int target, int msg);
+extern void openpic_set_k2_cascade(int irq);
+extern void openpic_set_priority(u_int pri);
+extern u_int openpic_get_priority(void);
+
+extern inline int openpic_to_irq(int irq)
+{
+ /* IRQ 0 usually means 'disabled'.. don't mess with it
+ * exceptions to this (sandpoint maybe?)
+ * shouldn't use openpic_to_irq
+ */
+ if (irq != 0){
+ return irq += NUM_8259_INTERRUPTS;
+ } else {
+ return 0;
+ }
+}
+/* Support for second openpic on G5 macs */
+
+// FIXME: To be replaced by sane cascaded controller management */
+
+#define PMAC_OPENPIC2_OFFSET 128
+
+#define OPENPIC2_VEC_TIMER 110 /* and up */
+#define OPENPIC2_VEC_IPI 118 /* and up */
+#define OPENPIC2_VEC_SPURIOUS 127
+
+
+extern void* OpenPIC2_Addr;
+
+/* Exported functions */
+extern void openpic2_set_sources(int first_irq, int num_irqs, void *isr);
+extern void openpic2_init(int linux_irq_offset);
+extern void openpic2_init_nmi_irq(u_int irq);
+extern u_int openpic2_irq(void);
+extern void openpic2_eoi(void);
+extern int openpic2_get_irq(struct pt_regs *regs);
+extern void openpic2_setup_ISU(int isu_num, unsigned long addr);
+
+#endif /* _ASM_POWERPC_OPEN_PIC_H */
diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h
deleted file mode 100644
index ec2f466..0000000
--- a/include/asm-ppc/open_pic.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling
- *
- * Copyright (C) 1997 Geert Uytterhoeven
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive
- * for more details.
- *
- */
-
-#ifndef _PPC_KERNEL_OPEN_PIC_H
-#define _PPC_KERNEL_OPEN_PIC_H
-
-#include <linux/config.h>
-#include <linux/irq.h>
-
-#define OPENPIC_SIZE 0x40000
-
-/*
- * Non-offset'ed vector numbers
- */
-
-#define OPENPIC_VEC_TIMER 110 /* and up */
-#define OPENPIC_VEC_IPI 118 /* and up */
-#define OPENPIC_VEC_SPURIOUS 255
-
-/* Priorities */
-#define OPENPIC_PRIORITY_IPI_BASE 10
-#define OPENPIC_PRIORITY_DEFAULT 4
-#define OPENPIC_PRIORITY_NMI 9
-
-/* OpenPIC IRQ controller structure */
-extern struct hw_interrupt_type open_pic;
-
-/* OpenPIC IPI controller structure */
-#ifdef CONFIG_SMP
-extern struct hw_interrupt_type open_pic_ipi;
-#endif /* CONFIG_SMP */
-
-extern u_int OpenPIC_NumInitSenses;
-extern u_char *OpenPIC_InitSenses;
-extern void __iomem * OpenPIC_Addr;
-extern int epic_serial_mode;
-
-/* Exported functions */
-extern void openpic_set_sources(int first_irq, int num_irqs, void __iomem *isr);
-extern void openpic_init(int linux_irq_offset);
-extern void openpic_init_nmi_irq(u_int irq);
-extern void openpic_set_irq_priority(u_int irq, u_int pri);
-extern void openpic_hookup_cascade(u_int irq, char *name,
- int (*cascade_fn)(struct pt_regs *));
-extern u_int openpic_irq(void);
-extern void openpic_eoi(void);
-extern void openpic_request_IPIs(void);
-extern void do_openpic_setup_cpu(void);
-extern int openpic_get_irq(struct pt_regs *regs);
-extern void openpic_reset_processor_phys(u_int cpumask);
-extern void openpic_setup_ISU(int isu_num, unsigned long addr);
-extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
-extern void smp_openpic_message_pass(int target, int msg);
-extern void openpic_set_k2_cascade(int irq);
-extern void openpic_set_priority(u_int pri);
-extern u_int openpic_get_priority(void);
-
-extern inline int openpic_to_irq(int irq)
-{
- /* IRQ 0 usually means 'disabled'.. don't mess with it
- * exceptions to this (sandpoint maybe?)
- * shouldn't use openpic_to_irq
- */
- if (irq != 0){
- return irq += NUM_8259_INTERRUPTS;
- } else {
- return 0;
- }
-}
-/* Support for second openpic on G5 macs */
-
-// FIXME: To be replaced by sane cascaded controller management */
-
-#define PMAC_OPENPIC2_OFFSET 128
-
-#define OPENPIC2_VEC_TIMER 110 /* and up */
-#define OPENPIC2_VEC_IPI 118 /* and up */
-#define OPENPIC2_VEC_SPURIOUS 127
-
-
-extern void* OpenPIC2_Addr;
-
-/* Exported functions */
-extern void openpic2_set_sources(int first_irq, int num_irqs, void *isr);
-extern void openpic2_init(int linux_irq_offset);
-extern void openpic2_init_nmi_irq(u_int irq);
-extern u_int openpic2_irq(void);
-extern void openpic2_eoi(void);
-extern int openpic2_get_irq(struct pt_regs *regs);
-extern void openpic2_setup_ISU(int isu_num, unsigned long addr);
-#endif /* _PPC_KERNEL_OPEN_PIC_H */
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 09/15] powerpc: move asm/hydra.h
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
` (7 preceding siblings ...)
2006-04-05 5:10 ` [PATCH 08/15] powerpc: move asm/open_pic.h sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 5:10 ` [PATCH 10/15] powerpc: move asm/mpc83xx.h sfr
` (6 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 7131 bytes --]
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/hydra.h | 102 +++++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/hydra.h | 102 -------------------------------------------
2 files changed, 102 insertions(+), 102 deletions(-)
create mode 100644 include/asm-powerpc/hydra.h
delete mode 100644 include/asm-ppc/hydra.h
cdf75e3d546f69e8d3cf7c32b705a40ce2552a22
diff --git a/include/asm-powerpc/hydra.h b/include/asm-powerpc/hydra.h
new file mode 100644
index 0000000..61c8abb
--- /dev/null
+++ b/include/asm-powerpc/hydra.h
@@ -0,0 +1,102 @@
+#ifndef _ASM_POWERCP_HYDRA_H
+#define _ASM_POWERCP_HYDRA_H
+
+/*
+ * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
+ *
+ * Copyright (C) 1997 Geert Uytterhoeven
+ *
+ * This file is based on the following documentation:
+ *
+ * Macintosh Technology in the Common Hardware Reference Platform
+ * Apple Computer, Inc.
+ *
+ * © Copyright 1995 Apple Computer, Inc. All rights reserved.
+ *
+ * It's available online from http://chrp.apple.com/MacTech.pdf.
+ * You can obtain paper copies of this book from computer bookstores or by
+ * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
+ * Francisco, CA 94104. Reference ISBN 1-55860-393-X.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#ifdef __KERNEL__
+
+struct Hydra {
+ /* DBDMA Controller Register Space */
+ char Pad1[0x30];
+ u_int CachePD;
+ u_int IDs;
+ u_int Feature_Control;
+ char Pad2[0x7fc4];
+ /* DBDMA Channel Register Space */
+ char SCSI_DMA[0x100];
+ char Pad3[0x300];
+ char SCCA_Tx_DMA[0x100];
+ char SCCA_Rx_DMA[0x100];
+ char SCCB_Tx_DMA[0x100];
+ char SCCB_Rx_DMA[0x100];
+ char Pad4[0x7800];
+ /* Device Register Space */
+ char SCSI[0x1000];
+ char ADB[0x1000];
+ char SCC_Legacy[0x1000];
+ char SCC[0x1000];
+ char Pad9[0x2000];
+ char VIA[0x2000];
+ char Pad10[0x28000];
+ char OpenPIC[0x40000];
+};
+
+extern volatile struct Hydra __iomem *Hydra;
+
+
+ /*
+ * Feature Control Register
+ */
+
+#define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */
+#define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */
+#define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */
+#define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */
+#define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */
+#define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */
+#define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */
+#define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */
+#define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */
+
+
+ /*
+ * OpenPIC Interrupt Sources
+ */
+
+#define HYDRA_INT_SIO 0
+#define HYDRA_INT_SCSI_DMA 1
+#define HYDRA_INT_SCCA_TX_DMA 2
+#define HYDRA_INT_SCCA_RX_DMA 3
+#define HYDRA_INT_SCCB_TX_DMA 4
+#define HYDRA_INT_SCCB_RX_DMA 5
+#define HYDRA_INT_SCSI 6
+#define HYDRA_INT_SCCA 7
+#define HYDRA_INT_SCCB 8
+#define HYDRA_INT_VIA 9
+#define HYDRA_INT_ADB 10
+#define HYDRA_INT_ADB_NMI 11
+#define HYDRA_INT_EXT1 12 /* PCI IRQW */
+#define HYDRA_INT_EXT2 13 /* PCI IRQX */
+#define HYDRA_INT_EXT3 14 /* PCI IRQY */
+#define HYDRA_INT_EXT4 15 /* PCI IRQZ */
+#define HYDRA_INT_EXT5 16 /* IDE Primay/Secondary */
+#define HYDRA_INT_EXT6 17 /* IDE Secondary */
+#define HYDRA_INT_EXT7 18 /* Power Off Request */
+#define HYDRA_INT_SPARE 19
+
+extern int hydra_init(void);
+extern void macio_adb_init(void);
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_POWERCP_HYDRA_H */
diff --git a/include/asm-ppc/hydra.h b/include/asm-ppc/hydra.h
deleted file mode 100644
index 833a8af..0000000
--- a/include/asm-ppc/hydra.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
- *
- * Copyright (C) 1997 Geert Uytterhoeven
- *
- * This file is based on the following documentation:
- *
- * Macintosh Technology in the Common Hardware Reference Platform
- * Apple Computer, Inc.
- *
- * © Copyright 1995 Apple Computer, Inc. All rights reserved.
- *
- * It's available online from http://chrp.apple.com/MacTech.pdf.
- * You can obtain paper copies of this book from computer bookstores or by
- * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
- * Francisco, CA 94104. Reference ISBN 1-55860-393-X.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-#ifndef _ASMPPC_HYDRA_H
-#define _ASMPPC_HYDRA_H
-
-#ifdef __KERNEL__
-
-struct Hydra {
- /* DBDMA Controller Register Space */
- char Pad1[0x30];
- u_int CachePD;
- u_int IDs;
- u_int Feature_Control;
- char Pad2[0x7fc4];
- /* DBDMA Channel Register Space */
- char SCSI_DMA[0x100];
- char Pad3[0x300];
- char SCCA_Tx_DMA[0x100];
- char SCCA_Rx_DMA[0x100];
- char SCCB_Tx_DMA[0x100];
- char SCCB_Rx_DMA[0x100];
- char Pad4[0x7800];
- /* Device Register Space */
- char SCSI[0x1000];
- char ADB[0x1000];
- char SCC_Legacy[0x1000];
- char SCC[0x1000];
- char Pad9[0x2000];
- char VIA[0x2000];
- char Pad10[0x28000];
- char OpenPIC[0x40000];
-};
-
-extern volatile struct Hydra __iomem *Hydra;
-
-
- /*
- * Feature Control Register
- */
-
-#define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */
-#define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */
-#define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */
-#define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */
-#define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */
-#define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */
-#define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */
-#define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */
-#define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */
-
-
- /*
- * OpenPIC Interrupt Sources
- */
-
-#define HYDRA_INT_SIO 0
-#define HYDRA_INT_SCSI_DMA 1
-#define HYDRA_INT_SCCA_TX_DMA 2
-#define HYDRA_INT_SCCA_RX_DMA 3
-#define HYDRA_INT_SCCB_TX_DMA 4
-#define HYDRA_INT_SCCB_RX_DMA 5
-#define HYDRA_INT_SCSI 6
-#define HYDRA_INT_SCCA 7
-#define HYDRA_INT_SCCB 8
-#define HYDRA_INT_VIA 9
-#define HYDRA_INT_ADB 10
-#define HYDRA_INT_ADB_NMI 11
-#define HYDRA_INT_EXT1 12 /* PCI IRQW */
-#define HYDRA_INT_EXT2 13 /* PCI IRQX */
-#define HYDRA_INT_EXT3 14 /* PCI IRQY */
-#define HYDRA_INT_EXT4 15 /* PCI IRQZ */
-#define HYDRA_INT_EXT5 16 /* IDE Primay/Secondary */
-#define HYDRA_INT_EXT6 17 /* IDE Secondary */
-#define HYDRA_INT_EXT7 18 /* Power Off Request */
-#define HYDRA_INT_SPARE 19
-
-extern int hydra_init(void);
-extern void macio_adb_init(void);
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASMPPC_HYDRA_H */
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 10/15] powerpc: move asm/mpc83xx.h
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
` (8 preceding siblings ...)
2006-04-05 5:10 ` [PATCH 09/15] powerpc: move asm/hydra.h sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 14:17 ` Kumar Gala
2006-04-05 5:10 ` [PATCH 11/15] powerpc: move asm/ocp.h sfr
` (5 subsequent siblings)
15 siblings, 1 reply; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/mpc83xx.h | 115 +++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/mpc83xx.h | 116 -----------------------------------------
2 files changed, 115 insertions(+), 116 deletions(-)
create mode 100644 include/asm-powerpc/mpc83xx.h
delete mode 100644 include/asm-ppc/mpc83xx.h
ce28e1e8654ad07cc23573a31f8cea992d41f9cc
diff --git a/include/asm-powerpc/mpc83xx.h b/include/asm-powerpc/mpc83xx.h
new file mode 100644
index 0000000..da4b0fa
--- /dev/null
+++ b/include/asm-powerpc/mpc83xx.h
@@ -0,0 +1,115 @@
+#ifndef _ASM_POWERPC_MPC83XX_H
+#define _ASM_POWERPC_MPC83XX_H
+/*
+ * include/asm-ppc/mpc83xx.h
+ *
+ * MPC83xx definitions
+ *
+ * Maintainer: Kumar Gala <galak@kernel.crashing.org>
+ *
+ * Copyright 2005 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+
+#include <asm/mmu.h>
+
+#ifdef CONFIG_83xx
+
+#ifdef CONFIG_MPC834x_SYS
+#include <platforms/83xx/mpc834x_sys.h>
+#endif
+
+#define _IO_BASE isa_io_base
+#define _ISA_MEM_BASE isa_mem_base
+#ifdef CONFIG_PCI
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define PCI_DRAM_OFFSET 0
+#endif
+
+/*
+ * The "residual" board information structure the boot loader passes
+ * into the kernel.
+ */
+extern unsigned char __res[];
+
+/* Internal IRQs on MPC83xx OpenPIC */
+/* Not all of these exist on all MPC83xx implementations */
+
+#ifndef MPC83xx_IPIC_IRQ_OFFSET
+#define MPC83xx_IPIC_IRQ_OFFSET 0
+#endif
+
+#define NR_IPIC_INTS 128
+
+#define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET)
+
+#define MPC83xx_CCSRBAR_SIZE (1024*1024)
+
+/* Let modules/drivers get at immrbar (physical) */
+extern phys_addr_t immrbar;
+
+enum ppc_sys_devices {
+ MPC83xx_TSEC1,
+ MPC83xx_TSEC2,
+ MPC83xx_IIC1,
+ MPC83xx_IIC2,
+ MPC83xx_DUART,
+ MPC83xx_SEC2,
+ MPC83xx_USB2_DR,
+ MPC83xx_USB2_MPH,
+ MPC83xx_MDIO,
+ NUM_PPC_SYS_DEVS,
+};
+
+#endif /* CONFIG_83xx */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_MPC83XX_H */
diff --git a/include/asm-ppc/mpc83xx.h b/include/asm-ppc/mpc83xx.h
deleted file mode 100644
index 3c23fc4..0000000
--- a/include/asm-ppc/mpc83xx.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * include/asm-ppc/mpc83xx.h
- *
- * MPC83xx definitions
- *
- * Maintainer: Kumar Gala <galak@kernel.crashing.org>
- *
- * Copyright 2005 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_MPC83xx_H__
-#define __ASM_MPC83xx_H__
-
-#include <linux/config.h>
-#include <asm/mmu.h>
-
-#ifdef CONFIG_83xx
-
-#ifdef CONFIG_MPC834x_SYS
-#include <platforms/83xx/mpc834x_sys.h>
-#endif
-
-#define _IO_BASE isa_io_base
-#define _ISA_MEM_BASE isa_mem_base
-#ifdef CONFIG_PCI
-#define PCI_DRAM_OFFSET pci_dram_offset
-#else
-#define PCI_DRAM_OFFSET 0
-#endif
-
-/*
- * The "residual" board information structure the boot loader passes
- * into the kernel.
- */
-extern unsigned char __res[];
-
-/* Internal IRQs on MPC83xx OpenPIC */
-/* Not all of these exist on all MPC83xx implementations */
-
-#ifndef MPC83xx_IPIC_IRQ_OFFSET
-#define MPC83xx_IPIC_IRQ_OFFSET 0
-#endif
-
-#define NR_IPIC_INTS 128
-
-#define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET)
-
-#define MPC83xx_CCSRBAR_SIZE (1024*1024)
-
-/* Let modules/drivers get at immrbar (physical) */
-extern phys_addr_t immrbar;
-
-enum ppc_sys_devices {
- MPC83xx_TSEC1,
- MPC83xx_TSEC2,
- MPC83xx_IIC1,
- MPC83xx_IIC2,
- MPC83xx_DUART,
- MPC83xx_SEC2,
- MPC83xx_USB2_DR,
- MPC83xx_USB2_MPH,
- MPC83xx_MDIO,
- NUM_PPC_SYS_DEVS,
-};
-
-#endif /* CONFIG_83xx */
-#endif /* __ASM_MPC83xx_H__ */
-#endif /* __KERNEL__ */
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 11/15] powerpc: move asm/ocp.h
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
` (9 preceding siblings ...)
2006-04-05 5:10 ` [PATCH 10/15] powerpc: move asm/mpc83xx.h sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 14:07 ` Kumar Gala
2006-04-05 5:10 ` [PATCH 12/15] powerpc: move asm/ocp_ids.h sfr
` (4 subsequent siblings)
15 siblings, 1 reply; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/ocp.h | 206 +++++++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/ocp.h | 207 ---------------------------------------------
2 files changed, 206 insertions(+), 207 deletions(-)
create mode 100644 include/asm-powerpc/ocp.h
delete mode 100644 include/asm-ppc/ocp.h
c7b417812dc2ebece32356c0a5e93966de9ba2cd
diff --git a/include/asm-powerpc/ocp.h b/include/asm-powerpc/ocp.h
new file mode 100644
index 0000000..8916c52
--- /dev/null
+++ b/include/asm-powerpc/ocp.h
@@ -0,0 +1,206 @@
+#ifndef _ASM_POWERPC_OCP_H
+#define _ASM_POWERPC_OCP_H
+/*
+ * ocp.h
+ *
+ * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
+ * Mipsys - France
+ *
+ * Derived from work (c) Armin Kuster akuster@pacbell.net
+ *
+ * Additional support and port to 2.6 LDM/sysfs by
+ * Matt Porter <mporter@kernel.crashing.org>
+ * Copyright 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * TODO: - Add get/put interface & fixup locking to provide same API for
+ * 2.4 and 2.5
+ * - Rework PM callbacks
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/devfs_fs_kernel.h>
+#include <linux/device.h>
+
+#include <asm/mmu.h>
+#include <asm/ocp_ids.h>
+#include <asm/rwsem.h>
+#include <asm/semaphore.h>
+
+#ifdef CONFIG_PPC_OCP
+
+#define OCP_MAX_IRQS 7
+#define MAX_EMACS 4
+#define OCP_IRQ_NA -1 /* used when ocp device does not have an irq */
+#define OCP_IRQ_MUL -2 /* used for ocp devices with multiply irqs */
+#define OCP_NULL_TYPE -1 /* used to mark end of list */
+#define OCP_CPM_NA 0 /* No Clock or Power Management avaliable */
+#define OCP_PADDR_NA 0 /* No MMIO registers */
+
+#define OCP_ANY_ID (~0)
+#define OCP_ANY_INDEX -1
+
+extern struct list_head ocp_devices;
+extern struct rw_semaphore ocp_devices_sem;
+
+struct ocp_device_id {
+ unsigned int vendor, function; /* Vendor and function ID or OCP_ANY_ID */
+ unsigned long driver_data; /* Data private to the driver */
+};
+
+
+/*
+ * Static definition of an OCP device.
+ *
+ * @vendor: Vendor code. It is _STRONGLY_ discouraged to use
+ * the vendor code as a way to match a unique device,
+ * though I kept that possibility open, you should
+ * really define different function codes for different
+ * device types
+ * @function: This is the function code for this device.
+ * @index: This index is used for mapping the Nth function of a
+ * given core. This is typically used for cross-driver
+ * matching, like looking for a given MAL or ZMII from
+ * an EMAC or for getting to the proper set of DCRs.
+ * Indices are no longer magically calculated based on
+ * structure ordering, they have to be actually coded
+ * into the ocp_def to avoid any possible confusion
+ * I _STRONGLY_ (again ? wow !) encourage anybody relying
+ * on index mapping to encode the "target" index in an
+ * associated structure pointed to by "additions", see
+ * how it's done for the EMAC driver.
+ * @paddr: Device physical address (may not mean anything...)
+ * @irq: Interrupt line for this device (TODO: think about making
+ * an array with this)
+ * @pm: Currently, contains the bitmask in CPMFR DCR for the device
+ * @additions: Optionally points to a function specific structure
+ * providing additional informations for a given device
+ * instance. It's currently used by the EMAC driver for MAL
+ * channel & ZMII port mapping among others.
+ * @show: Optionally points to a function specific structure
+ * providing a sysfs show routine for additions fields.
+ */
+struct ocp_def {
+ unsigned int vendor;
+ unsigned int function;
+ int index;
+ phys_addr_t paddr;
+ int irq;
+ unsigned long pm;
+ void *additions;
+ void (*show)(struct device *);
+};
+
+
+/* Struct for a given device instance */
+struct ocp_device {
+ struct list_head link;
+ char name[80]; /* device name */
+ struct ocp_def *def; /* device definition */
+ void *drvdata; /* driver data for this device */
+ struct ocp_driver *driver;
+ u32 current_state; /* Current operating state. In ACPI-speak,
+ this is D0-D3, D0 being fully functional,
+ and D3 being off. */
+ struct device dev;
+};
+
+struct ocp_driver {
+ struct list_head node;
+ char *name;
+ const struct ocp_device_id *id_table; /* NULL if wants all devices */
+ int (*probe) (struct ocp_device *dev); /* New device inserted */
+ void (*remove) (struct ocp_device *dev); /* Device removed (NULL if not a hot-plug capable driver) */
+ int (*suspend) (struct ocp_device *dev, pm_message_t state); /* Device suspended */
+ int (*resume) (struct ocp_device *dev); /* Device woken up */
+ struct device_driver driver;
+};
+
+#define to_ocp_dev(n) container_of(n, struct ocp_device, dev)
+#define to_ocp_drv(n) container_of(n, struct ocp_driver, driver)
+
+/* Similar to the helpers above, these manipulate per-ocp_dev
+ * driver-specific data. Currently stored as ocp_dev::ocpdev,
+ * a void pointer, but it is not present on older kernels.
+ */
+static inline void *
+ocp_get_drvdata(struct ocp_device *pdev)
+{
+ return pdev->drvdata;
+}
+
+static inline void
+ocp_set_drvdata(struct ocp_device *pdev, void *data)
+{
+ pdev->drvdata = data;
+}
+
+#if defined (CONFIG_PM)
+/*
+ * This is right for the IBM 405 and 440 but will need to be
+ * generalized if the OCP stuff gets used on other processors.
+ */
+static inline void
+ocp_force_power_off(struct ocp_device *odev)
+{
+ mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm);
+}
+
+static inline void
+ocp_force_power_on(struct ocp_device *odev)
+{
+ mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm);
+}
+#else
+#define ocp_force_power_off(x) (void)(x)
+#define ocp_force_power_on(x) (void)(x)
+#endif
+
+/* Register/Unregister an OCP driver */
+extern int ocp_register_driver(struct ocp_driver *drv);
+extern void ocp_unregister_driver(struct ocp_driver *drv);
+
+/* Build list of devices */
+extern int ocp_early_init(void) __init;
+
+/* Find a device by index */
+extern struct ocp_device *ocp_find_device(unsigned int vendor, unsigned int function, int index);
+
+/* Get a def by index */
+extern struct ocp_def *ocp_get_one_device(unsigned int vendor, unsigned int function, int index);
+
+/* Add a device by index */
+extern int ocp_add_one_device(struct ocp_def *def);
+
+/* Remove a device by index */
+extern int ocp_remove_one_device(unsigned int vendor, unsigned int function, int index);
+
+/* Iterate over devices and execute a routine */
+extern void ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg), void *arg);
+
+/* Sysfs support */
+#define OCP_SYSFS_ADDTL(type, format, name, field) \
+static ssize_t \
+show_##name##_##field(struct device *dev, struct device_attribute *attr, char *buf) \
+{ \
+ struct ocp_device *odev = to_ocp_dev(dev); \
+ type *add = odev->def->additions; \
+ \
+ return sprintf(buf, format, add->field); \
+} \
+static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL);
+
+#ifdef CONFIG_IBM_OCP
+#include <asm/ibm_ocp.h>
+#endif
+
+#endif /* CONFIG_PPC_OCP */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_OCP_H */
diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h
deleted file mode 100644
index 983116f..0000000
--- a/include/asm-ppc/ocp.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * ocp.h
- *
- * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
- * Mipsys - France
- *
- * Derived from work (c) Armin Kuster akuster@pacbell.net
- *
- * Additional support and port to 2.6 LDM/sysfs by
- * Matt Porter <mporter@kernel.crashing.org>
- * Copyright 2003-2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * TODO: - Add get/put interface & fixup locking to provide same API for
- * 2.4 and 2.5
- * - Rework PM callbacks
- */
-
-#ifdef __KERNEL__
-#ifndef __OCP_H__
-#define __OCP_H__
-
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/config.h>
-#include <linux/devfs_fs_kernel.h>
-#include <linux/device.h>
-
-#include <asm/mmu.h>
-#include <asm/ocp_ids.h>
-#include <asm/rwsem.h>
-#include <asm/semaphore.h>
-
-#ifdef CONFIG_PPC_OCP
-
-#define OCP_MAX_IRQS 7
-#define MAX_EMACS 4
-#define OCP_IRQ_NA -1 /* used when ocp device does not have an irq */
-#define OCP_IRQ_MUL -2 /* used for ocp devices with multiply irqs */
-#define OCP_NULL_TYPE -1 /* used to mark end of list */
-#define OCP_CPM_NA 0 /* No Clock or Power Management avaliable */
-#define OCP_PADDR_NA 0 /* No MMIO registers */
-
-#define OCP_ANY_ID (~0)
-#define OCP_ANY_INDEX -1
-
-extern struct list_head ocp_devices;
-extern struct rw_semaphore ocp_devices_sem;
-
-struct ocp_device_id {
- unsigned int vendor, function; /* Vendor and function ID or OCP_ANY_ID */
- unsigned long driver_data; /* Data private to the driver */
-};
-
-
-/*
- * Static definition of an OCP device.
- *
- * @vendor: Vendor code. It is _STRONGLY_ discouraged to use
- * the vendor code as a way to match a unique device,
- * though I kept that possibility open, you should
- * really define different function codes for different
- * device types
- * @function: This is the function code for this device.
- * @index: This index is used for mapping the Nth function of a
- * given core. This is typically used for cross-driver
- * matching, like looking for a given MAL or ZMII from
- * an EMAC or for getting to the proper set of DCRs.
- * Indices are no longer magically calculated based on
- * structure ordering, they have to be actually coded
- * into the ocp_def to avoid any possible confusion
- * I _STRONGLY_ (again ? wow !) encourage anybody relying
- * on index mapping to encode the "target" index in an
- * associated structure pointed to by "additions", see
- * how it's done for the EMAC driver.
- * @paddr: Device physical address (may not mean anything...)
- * @irq: Interrupt line for this device (TODO: think about making
- * an array with this)
- * @pm: Currently, contains the bitmask in CPMFR DCR for the device
- * @additions: Optionally points to a function specific structure
- * providing additional informations for a given device
- * instance. It's currently used by the EMAC driver for MAL
- * channel & ZMII port mapping among others.
- * @show: Optionally points to a function specific structure
- * providing a sysfs show routine for additions fields.
- */
-struct ocp_def {
- unsigned int vendor;
- unsigned int function;
- int index;
- phys_addr_t paddr;
- int irq;
- unsigned long pm;
- void *additions;
- void (*show)(struct device *);
-};
-
-
-/* Struct for a given device instance */
-struct ocp_device {
- struct list_head link;
- char name[80]; /* device name */
- struct ocp_def *def; /* device definition */
- void *drvdata; /* driver data for this device */
- struct ocp_driver *driver;
- u32 current_state; /* Current operating state. In ACPI-speak,
- this is D0-D3, D0 being fully functional,
- and D3 being off. */
- struct device dev;
-};
-
-struct ocp_driver {
- struct list_head node;
- char *name;
- const struct ocp_device_id *id_table; /* NULL if wants all devices */
- int (*probe) (struct ocp_device *dev); /* New device inserted */
- void (*remove) (struct ocp_device *dev); /* Device removed (NULL if not a hot-plug capable driver) */
- int (*suspend) (struct ocp_device *dev, pm_message_t state); /* Device suspended */
- int (*resume) (struct ocp_device *dev); /* Device woken up */
- struct device_driver driver;
-};
-
-#define to_ocp_dev(n) container_of(n, struct ocp_device, dev)
-#define to_ocp_drv(n) container_of(n, struct ocp_driver, driver)
-
-/* Similar to the helpers above, these manipulate per-ocp_dev
- * driver-specific data. Currently stored as ocp_dev::ocpdev,
- * a void pointer, but it is not present on older kernels.
- */
-static inline void *
-ocp_get_drvdata(struct ocp_device *pdev)
-{
- return pdev->drvdata;
-}
-
-static inline void
-ocp_set_drvdata(struct ocp_device *pdev, void *data)
-{
- pdev->drvdata = data;
-}
-
-#if defined (CONFIG_PM)
-/*
- * This is right for the IBM 405 and 440 but will need to be
- * generalized if the OCP stuff gets used on other processors.
- */
-static inline void
-ocp_force_power_off(struct ocp_device *odev)
-{
- mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm);
-}
-
-static inline void
-ocp_force_power_on(struct ocp_device *odev)
-{
- mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm);
-}
-#else
-#define ocp_force_power_off(x) (void)(x)
-#define ocp_force_power_on(x) (void)(x)
-#endif
-
-/* Register/Unregister an OCP driver */
-extern int ocp_register_driver(struct ocp_driver *drv);
-extern void ocp_unregister_driver(struct ocp_driver *drv);
-
-/* Build list of devices */
-extern int ocp_early_init(void) __init;
-
-/* Find a device by index */
-extern struct ocp_device *ocp_find_device(unsigned int vendor, unsigned int function, int index);
-
-/* Get a def by index */
-extern struct ocp_def *ocp_get_one_device(unsigned int vendor, unsigned int function, int index);
-
-/* Add a device by index */
-extern int ocp_add_one_device(struct ocp_def *def);
-
-/* Remove a device by index */
-extern int ocp_remove_one_device(unsigned int vendor, unsigned int function, int index);
-
-/* Iterate over devices and execute a routine */
-extern void ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg), void *arg);
-
-/* Sysfs support */
-#define OCP_SYSFS_ADDTL(type, format, name, field) \
-static ssize_t \
-show_##name##_##field(struct device *dev, struct device_attribute *attr, char *buf) \
-{ \
- struct ocp_device *odev = to_ocp_dev(dev); \
- type *add = odev->def->additions; \
- \
- return sprintf(buf, format, add->field); \
-} \
-static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL);
-
-#ifdef CONFIG_IBM_OCP
-#include <asm/ibm_ocp.h>
-#endif
-
-#endif /* CONFIG_PPC_OCP */
-#endif /* __OCP_H__ */
-#endif /* __KERNEL__ */
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 12/15] powerpc: move asm/ocp_ids.h
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
` (10 preceding siblings ...)
2006-04-05 5:10 ` [PATCH 11/15] powerpc: move asm/ocp.h sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 14:07 ` Kumar Gala
2006-04-05 5:10 ` [PATCH 13/15] powerpc: move asm/reg_booke.h sfr
` (3 subsequent siblings)
15 siblings, 1 reply; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/ocp_ids.h | 75 +++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/ocp_ids.h | 73 ----------------------------------------
2 files changed, 75 insertions(+), 73 deletions(-)
create mode 100644 include/asm-powerpc/ocp_ids.h
delete mode 100644 include/asm-ppc/ocp_ids.h
a374f458829d868a3142bff918ef872e0ecff1a8
diff --git a/include/asm-powerpc/ocp_ids.h b/include/asm-powerpc/ocp_ids.h
new file mode 100644
index 0000000..78e5906
--- /dev/null
+++ b/include/asm-powerpc/ocp_ids.h
@@ -0,0 +1,75 @@
+#ifndef _ASM_POWERPC_OCP_IDS_H
+#define _ASM_POWERPC_OCP_IDS_H
+/*
+ * OCP device ids based on the ideas from PCI
+ *
+ * The numbers below are almost completely arbitrary, and in fact
+ * strings might work better. -- paulus
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/*
+ * Vender device
+ * [xxxx] [xxxx]
+ *
+ * Keep in order, please
+ */
+
+/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */
+
+#define OCP_VENDOR_INVALID 0x0000
+#define OCP_VENDOR_ARM 0x0004
+#define OCP_VENDOR_FREESCALE 0x1057
+#define OCP_VENDOR_IBM 0x1014
+#define OCP_VENDOR_MOTOROLA OCP_VENDOR_FREESCALE
+#define OCP_VENDOR_XILINX 0x10ee
+#define OCP_VENDOR_UNKNOWN 0xFFFF
+
+/* device identification */
+
+/* define type */
+#define OCP_FUNC_INVALID 0x0000
+
+/* system 0x0001 - 0x001F */
+
+/* Timers 0x0020 - 0x002F */
+
+/* Serial 0x0030 - 0x006F*/
+#define OCP_FUNC_16550 0x0031
+#define OCP_FUNC_IIC 0x0032
+#define OCP_FUNC_USB 0x0033
+#define OCP_FUNC_PSC_UART 0x0034
+
+/* Memory devices 0x0090 - 0x009F */
+#define OCP_FUNC_MAL 0x0090
+#define OCP_FUNC_DMA 0x0091
+
+/* Display 0x00A0 - 0x00AF */
+
+/* Sound 0x00B0 - 0x00BF */
+
+/* Mass Storage 0x00C0 - 0xxCF */
+#define OCP_FUNC_IDE 0x00C0
+
+/* Misc 0x00D0 - 0x00DF*/
+#define OCP_FUNC_GPIO 0x00D0
+#define OCP_FUNC_ZMII 0x00D1
+#define OCP_FUNC_PERFMON 0x00D2 /* Performance Monitor */
+#define OCP_FUNC_RGMII 0x00D3
+#define OCP_FUNC_TAH 0x00D4
+#define OCP_FUNC_SEC2 0x00D5 /* Crypto/Security 2.0 */
+
+/* Network 0x0200 - 0x02FF */
+#define OCP_FUNC_EMAC 0x0200
+#define OCP_FUNC_GFAR 0x0201 /* TSEC & FEC */
+
+/* Bridge devices 0xE00 - 0xEFF */
+#define OCP_FUNC_OPB 0x0E00
+
+#define OCP_FUNC_UNKNOWN 0xFFFF
+
+#endif /* _ASM_POWERPC_OCP_IDS_H */
diff --git a/include/asm-ppc/ocp_ids.h b/include/asm-ppc/ocp_ids.h
deleted file mode 100644
index 8ae4b31..0000000
--- a/include/asm-ppc/ocp_ids.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * ocp_ids.h
- *
- * OCP device ids based on the ideas from PCI
- *
- * The numbers below are almost completely arbitrary, and in fact
- * strings might work better. -- paulus
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-/*
- * Vender device
- * [xxxx] [xxxx]
- *
- * Keep in order, please
- */
-
-/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */
-
-#define OCP_VENDOR_INVALID 0x0000
-#define OCP_VENDOR_ARM 0x0004
-#define OCP_VENDOR_FREESCALE 0x1057
-#define OCP_VENDOR_IBM 0x1014
-#define OCP_VENDOR_MOTOROLA OCP_VENDOR_FREESCALE
-#define OCP_VENDOR_XILINX 0x10ee
-#define OCP_VENDOR_UNKNOWN 0xFFFF
-
-/* device identification */
-
-/* define type */
-#define OCP_FUNC_INVALID 0x0000
-
-/* system 0x0001 - 0x001F */
-
-/* Timers 0x0020 - 0x002F */
-
-/* Serial 0x0030 - 0x006F*/
-#define OCP_FUNC_16550 0x0031
-#define OCP_FUNC_IIC 0x0032
-#define OCP_FUNC_USB 0x0033
-#define OCP_FUNC_PSC_UART 0x0034
-
-/* Memory devices 0x0090 - 0x009F */
-#define OCP_FUNC_MAL 0x0090
-#define OCP_FUNC_DMA 0x0091
-
-/* Display 0x00A0 - 0x00AF */
-
-/* Sound 0x00B0 - 0x00BF */
-
-/* Mass Storage 0x00C0 - 0xxCF */
-#define OCP_FUNC_IDE 0x00C0
-
-/* Misc 0x00D0 - 0x00DF*/
-#define OCP_FUNC_GPIO 0x00D0
-#define OCP_FUNC_ZMII 0x00D1
-#define OCP_FUNC_PERFMON 0x00D2 /* Performance Monitor */
-#define OCP_FUNC_RGMII 0x00D3
-#define OCP_FUNC_TAH 0x00D4
-#define OCP_FUNC_SEC2 0x00D5 /* Crypto/Security 2.0 */
-
-/* Network 0x0200 - 0x02FF */
-#define OCP_FUNC_EMAC 0x0200
-#define OCP_FUNC_GFAR 0x0201 /* TSEC & FEC */
-
-/* Bridge devices 0xE00 - 0xEFF */
-#define OCP_FUNC_OPB 0x0E00
-
-#define OCP_FUNC_UNKNOWN 0xFFFF
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 13/15] powerpc: move asm/reg_booke.h
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
` (11 preceding siblings ...)
2006-04-05 5:10 ` [PATCH 12/15] powerpc: move asm/ocp_ids.h sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 5:10 ` [PATCH 14/15] powerpc: move asm/mpc85xx.h sfr
` (2 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Some white space cleanups.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/reg_booke.h | 503 +++++++++++++++++++++++++++++++++++++++
include/asm-ppc/reg_booke.h | 502 ---------------------------------------
2 files changed, 503 insertions(+), 502 deletions(-)
create mode 100644 include/asm-powerpc/reg_booke.h
delete mode 100644 include/asm-ppc/reg_booke.h
c1f8fa598014ca7f56835066255273235543ea91
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
new file mode 100644
index 0000000..59531a9
--- /dev/null
+++ b/include/asm-powerpc/reg_booke.h
@@ -0,0 +1,503 @@
+#ifndef _ASM_POWERPC_REG_BOOKE_H
+#define _ASM_POWERPC_REG_BOOKE_H
+/*
+ * Contains register definitions common to the Book E PowerPC
+ * specification. Notice that while the IBM-40x series of CPUs
+ * are not true Book E PowerPCs, they borrowed a number of features
+ * before Book E was finalized, and are included here as well. Unfortunatly,
+ * they sometimes used different locations than true Book E CPUs did.
+ */
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+/* Device Control Registers */
+void __mtdcr(int reg, unsigned int val);
+unsigned int __mfdcr(int reg);
+#define mfdcr(rn) \
+ ({unsigned int rval; \
+ if (__builtin_constant_p(rn)) \
+ asm volatile("mfdcr %0," __stringify(rn) \
+ : "=r" (rval)); \
+ else \
+ rval = __mfdcr(rn); \
+ rval;})
+
+#define mtdcr(rn, v) \
+do { \
+ if (__builtin_constant_p(rn)) \
+ asm volatile("mtdcr " __stringify(rn) ",%0" \
+ : : "r" (v)); \
+ else \
+ __mtdcr(rn, v); \
+} while (0)
+
+/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
+#define mfdcri(base, reg) \
+({ \
+ mtdcr(base ## _CFGADDR, base ## _ ## reg); \
+ mfdcr(base ## _CFGDATA); \
+})
+
+#define mtdcri(base, reg, data) \
+do { \
+ mtdcr(base ## _CFGADDR, base ## _ ## reg); \
+ mtdcr(base ## _CFGDATA, data); \
+} while (0)
+
+/* Performance Monitor Registers */
+#define mfpmr(rn) ({unsigned int rval; \
+ asm volatile("mfpmr %0," __stringify(rn) \
+ : "=r" (rval)); rval;})
+#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
+#endif /* __ASSEMBLY__ */
+
+/* Freescale Book E Performance Monitor APU Registers */
+#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
+#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
+#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
+#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
+#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
+#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
+#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
+#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
+
+#define PMLCA_FC 0x80000000 /* Freeze Counter */
+#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
+#define PMLCA_FCU 0x20000000 /* Freeze in User */
+#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
+#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
+#define PMLCA_CE 0x04000000 /* Condition Enable */
+
+#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
+#define PMLCA_EVENT_SHIFT 16
+
+#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
+#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
+#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
+#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
+
+#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
+#define PMLCB_THRESHMUL_SHIFT 8
+
+#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
+#define PMLCB_THRESHOLD_SHIFT 0
+
+#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
+
+#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
+#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
+#define PMGC0_FCECE 0x20000000 /* Freeze countes on
+ Enabled Condition or
+ Event */
+
+#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
+#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
+#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
+#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
+#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
+#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
+#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
+#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
+#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
+#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
+#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
+#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
+#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
+
+
+/* Machine State Register (MSR) Fields */
+#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
+#define MSR_SPE (1<<25) /* Enable SPE */
+#define MSR_DWE (1<<10) /* Debug Wait Enable */
+#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
+#define MSR_IS MSR_IR /* Instruction Space */
+#define MSR_DS MSR_DR /* Data Space */
+#define MSR_PMM (1<<2) /* Performance monitor mark bit */
+
+/* Default MSR for kernel mode. */
+#if defined (CONFIG_40x)
+#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
+#elif defined(CONFIG_BOOKE)
+#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE)
+#endif
+
+/* Special Purpose Registers (SPRNs)*/
+#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
+#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
+#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
+#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
+#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
+#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
+#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
+#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
+#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
+#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
+#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
+#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
+#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
+#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
+#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
+#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
+#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
+#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
+#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
+#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
+#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
+#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
+#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
+#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
+#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
+#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
+#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */
+#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */
+#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */
+#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
+#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
+#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
+#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
+#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
+#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
+#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
+#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
+#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
+#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
+#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
+#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
+#define SPRN_MCSR 0x23C /* Machine Check Status Register */
+#define SPRN_MCAR 0x23D /* Machine Check Address Register */
+#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
+#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
+#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
+#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
+#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
+#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
+#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
+#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
+#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
+#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */
+#define SPRN_PID1 0x279 /* Process ID Register 1 */
+#define SPRN_PID2 0x27A /* Process ID Register 2 */
+#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
+#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
+#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
+#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
+#define SPRN_MMUCR 0x3B2 /* MMU Control Register */
+#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
+#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
+#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
+#define SPRN_SLER 0x3BB /* Little-endian real mode */
+#define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */
+#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
+#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
+#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
+#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
+#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
+#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
+#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
+#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
+#define SPRN_SVR 0x3FF /* System Version Register */
+
+/*
+ * SPRs which have conflicting definitions on true Book E versus classic,
+ * or IBM 40x.
+ */
+#ifdef CONFIG_BOOKE
+#define SPRN_PID 0x030 /* Process ID */
+#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
+#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
+#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
+#define SPRN_DEAR 0x03D /* Data Error Address Register */
+#define SPRN_ESR 0x03E /* Exception Syndrome Register */
+#define SPRN_PIR 0x11E /* Processor Identification Register */
+#define SPRN_DBSR 0x130 /* Debug Status Register */
+#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */
+#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */
+#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */
+#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */
+#define SPRN_DAC1 0x13C /* Data Address Compare 1 */
+#define SPRN_DAC2 0x13D /* Data Address Compare 2 */
+#define SPRN_TSR 0x150 /* Timer Status Register */
+#define SPRN_TCR 0x154 /* Timer Control Register */
+#endif /* Book E */
+#ifdef CONFIG_40x
+#define SPRN_PID 0x3B1 /* Process ID */
+#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
+#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
+#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
+#define SPRN_TSR 0x3D8 /* Timer Status Register */
+#define SPRN_TCR 0x3DA /* Timer Control Register */
+#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
+#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
+#define SPRN_DBSR 0x3F0 /* Debug Status Register */
+#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
+#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
+#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
+#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */
+#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
+#endif
+
+/* Bit definitions for CCR1. */
+#define CCR1_TCS 0x00000080 /* Timer Clock Select */
+
+/* Bit definitions for the MCSR. */
+#ifdef CONFIG_440A
+#define MCSR_MCS 0x80000000 /* Machine Check Summary */
+#define MCSR_IB 0x40000000 /* Instruction PLB Error */
+#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
+#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
+#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
+#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
+#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
+#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
+#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
+#endif
+#ifdef CONFIG_E500
+#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
+#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
+#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
+#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
+#define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */
+#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
+#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */
+#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */
+#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */
+#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */
+#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */
+#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
+#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
+#endif
+#ifdef CONFIG_E200
+#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
+#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */
+#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */
+#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
+ fetch for an exception handler */
+#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/
+#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
+#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
+ store or cache line push */
+#endif
+
+/* Bit definitions for the DBSR. */
+/*
+ * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
+ */
+#ifdef CONFIG_BOOKE
+#define DBSR_IC 0x08000000 /* Instruction Completion */
+#define DBSR_BT 0x04000000 /* Branch Taken */
+#define DBSR_TIE 0x01000000 /* Trap Instruction Event */
+#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */
+#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */
+#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */
+#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */
+#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */
+#define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */
+#define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */
+#define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */
+#endif
+#ifdef CONFIG_40x
+#define DBSR_IC 0x80000000 /* Instruction Completion */
+#define DBSR_BT 0x40000000 /* Branch taken */
+#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */
+#define DBSR_IAC1 0x00800000 /* Instruction Address Compare 1 Event */
+#define DBSR_IAC2 0x00400000 /* Instruction Address Compare 2 Event */
+#define DBSR_IAC3 0x00200000 /* Instruction Address Compare 3 Event */
+#define DBSR_IAC4 0x00100000 /* Instruction Address Compare 4 Event */
+#define DBSR_DAC1R 0x00080000 /* Data Address Compare 1 Read Event */
+#define DBSR_DAC1W 0x00040000 /* Data Address Compare 1 Write Event */
+#define DBSR_DAC2R 0x00020000 /* Data Address Compare 2 Read Event */
+#define DBSR_DAC2W 0x00010000 /* Data Address Compare 2 Write Event */
+#endif
+
+/* Bit definitions related to the ESR. */
+#define ESR_MCI 0x80000000 /* Machine Check - Instruction */
+#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
+#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
+#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
+#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
+#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
+#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
+#define ESR_PTR 0x02000000 /* Program Exception - Trap */
+#define ESR_FP 0x01000000 /* Floating Point Operation */
+#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
+#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
+#define ESR_ST 0x00800000 /* Store Operation */
+#define ESR_DLK 0x00200000 /* Data Cache Locking */
+#define ESR_ILK 0x00100000 /* Instr. Cache Locking */
+#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */
+#define ESR_BO 0x00020000 /* Byte Ordering */
+
+/* Bit definitions related to the DBCR0. */
+#define DBCR0_EDM 0x80000000 /* External Debug Mode */
+#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
+#define DBCR0_RST 0x30000000 /* all the bits in the RST field */
+#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
+#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
+#define DBCR0_RST_CORE 0x10000000 /* Core Reset */
+#define DBCR0_RST_NONE 0x00000000 /* No Reset */
+#define DBCR0_IC 0x08000000 /* Instruction Completion */
+#define DBCR0_BT 0x04000000 /* Branch Taken */
+#define DBCR0_EDE 0x02000000 /* Exception Debug Event */
+#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
+#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */
+#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */
+#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */
+#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */
+#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */
+#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */
+#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */
+#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */
+#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */
+#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
+#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
+
+/* Bit definitions related to the TCR. */
+#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
+#define TCR_WP_MASK TCR_WP(3)
+#define WP_2_17 0 /* 2^17 clocks */
+#define WP_2_21 1 /* 2^21 clocks */
+#define WP_2_25 2 /* 2^25 clocks */
+#define WP_2_29 3 /* 2^29 clocks */
+#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
+#define TCR_WRC_MASK TCR_WRC(3)
+#define WRC_NONE 0 /* No reset will occur */
+#define WRC_CORE 1 /* Core reset will occur */
+#define WRC_CHIP 2 /* Chip reset will occur */
+#define WRC_SYSTEM 3 /* System reset will occur */
+#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
+#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
+#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */
+#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
+#define TCR_FP_MASK TCR_FP(3)
+#define FP_2_9 0 /* 2^9 clocks */
+#define FP_2_13 1 /* 2^13 clocks */
+#define FP_2_17 2 /* 2^17 clocks */
+#define FP_2_21 3 /* 2^21 clocks */
+#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
+#define TCR_ARE 0x00400000 /* Auto Reload Enable */
+
+/* Bit definitions for the TSR. */
+#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
+#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
+#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
+#define WRS_NONE 0 /* No WDT reset occurred */
+#define WRS_CORE 1 /* WDT forced core reset */
+#define WRS_CHIP 2 /* WDT forced chip reset */
+#define WRS_SYSTEM 3 /* WDT forced system reset */
+#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
+#define TSR_DIS TSR_PIS /* DEC Interrupt Status */
+#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
+
+/* Bit definitions for the DCCR. */
+#define DCCR_NOCACHE 0 /* Noncacheable */
+#define DCCR_CACHE 1 /* Cacheable */
+
+/* Bit definitions for DCWR. */
+#define DCWR_COPY 0 /* Copy-back */
+#define DCWR_WRITE 1 /* Write-through */
+
+/* Bit definitions for ICCR. */
+#define ICCR_NOCACHE 0 /* Noncacheable */
+#define ICCR_CACHE 1 /* Cacheable */
+
+/* Bit definitions for L1CSR0. */
+#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
+#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
+#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
+#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
+
+/* Bit definitions for L1CSR1. */
+#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
+#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
+#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
+
+/* Bit definitions for SGR. */
+#define SGR_NORMAL 0 /* Speculative fetching allowed. */
+#define SGR_GUARDED 1 /* Speculative fetching disallowed. */
+
+/* Bit definitions for SPEFSCR. */
+#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
+#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
+#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
+#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
+#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
+#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
+#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
+#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
+#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
+#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
+#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
+#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
+#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
+#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
+#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
+#define SPEFSCR_OV 0x00004000 /* Integer overflow */
+#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
+#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
+#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
+#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
+#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
+#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
+#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
+#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
+#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
+#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
+#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
+#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
+
+/*
+ * The IBM-403 is an even more odd special case, as it is much
+ * older than the IBM-405 series. We put these down here incase someone
+ * wishes to support these machines again.
+ */
+#ifdef CONFIG_403GCX
+/* Special Purpose Registers (SPRNs)*/
+#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
+#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
+#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
+#define SPRN_TBHI 0x3DC /* Time Base High */
+#define SPRN_TBLO 0x3DD /* Time Base Low */
+#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
+#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
+#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
+#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
+#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
+
+
+/* Bit definitions for the DBCR. */
+#define DBCR_EDM DBCR0_EDM
+#define DBCR_IDM DBCR0_IDM
+#define DBCR_RST(x) (((x) & 0x3) << 28)
+#define DBCR_RST_NONE 0
+#define DBCR_RST_CORE 1
+#define DBCR_RST_CHIP 2
+#define DBCR_RST_SYSTEM 3
+#define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */
+#define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */
+#define DBCR_EDE DBCR0_EDE /* Exception Debug Event */
+#define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */
+#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
+#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
+#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
+#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
+#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
+#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
+#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
+#define DAC_BYTE 0
+#define DAC_HALF 1
+#define DAC_WORD 2
+#define DAC_QUAD 3
+#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
+#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
+#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
+#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
+#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
+#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
+#define DBCR_SIA 0x00000008 /* Second IAC Enable */
+#define DBCR_SDA 0x00000004 /* Second DAC Enable */
+#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
+#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
+
+#endif /* 403GCX */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_REG_BOOKE_H */
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
deleted file mode 100644
index 00ad9c7..0000000
--- a/include/asm-ppc/reg_booke.h
+++ /dev/null
@@ -1,502 +0,0 @@
-/*
- * Contains register definitions common to the Book E PowerPC
- * specification. Notice that while the IBM-40x series of CPUs
- * are not true Book E PowerPCs, they borrowed a number of features
- * before Book E was finalized, and are included here as well. Unfortunatly,
- * they sometimes used different locations than true Book E CPUs did.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_PPC_REG_BOOKE_H__
-#define __ASM_PPC_REG_BOOKE_H__
-
-#ifndef __ASSEMBLY__
-/* Device Control Registers */
-void __mtdcr(int reg, unsigned int val);
-unsigned int __mfdcr(int reg);
-#define mfdcr(rn) \
- ({unsigned int rval; \
- if (__builtin_constant_p(rn)) \
- asm volatile("mfdcr %0," __stringify(rn) \
- : "=r" (rval)); \
- else \
- rval = __mfdcr(rn); \
- rval;})
-
-#define mtdcr(rn, v) \
-do { \
- if (__builtin_constant_p(rn)) \
- asm volatile("mtdcr " __stringify(rn) ",%0" \
- : : "r" (v)); \
- else \
- __mtdcr(rn, v); \
-} while (0)
-
-/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
-#define mfdcri(base, reg) \
-({ \
- mtdcr(base ## _CFGADDR, base ## _ ## reg); \
- mfdcr(base ## _CFGDATA); \
-})
-
-#define mtdcri(base, reg, data) \
-do { \
- mtdcr(base ## _CFGADDR, base ## _ ## reg); \
- mtdcr(base ## _CFGDATA, data); \
-} while (0)
-
-/* Performance Monitor Registers */
-#define mfpmr(rn) ({unsigned int rval; \
- asm volatile("mfpmr %0," __stringify(rn) \
- : "=r" (rval)); rval;})
-#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
-#endif /* __ASSEMBLY__ */
-
-/* Freescale Book E Performance Monitor APU Registers */
-#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
-#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
-#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
-#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
-#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
-#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
-#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
-#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
-
-#define PMLCA_FC 0x80000000 /* Freeze Counter */
-#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
-#define PMLCA_FCU 0x20000000 /* Freeze in User */
-#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
-#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
-#define PMLCA_CE 0x04000000 /* Condition Enable */
-
-#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
-#define PMLCA_EVENT_SHIFT 16
-
-#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
-#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
-#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
-#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
-
-#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
-#define PMLCB_THRESHMUL_SHIFT 8
-
-#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
-#define PMLCB_THRESHOLD_SHIFT 0
-
-#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
-
-#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
-#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
-#define PMGC0_FCECE 0x20000000 /* Freeze countes on
- Enabled Condition or
- Event */
-
-#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
-#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
-#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
-#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
-#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
-#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
-#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
-#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
-#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
-#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
-#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
-#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
-#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
-
-
-/* Machine State Register (MSR) Fields */
-#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
-#define MSR_SPE (1<<25) /* Enable SPE */
-#define MSR_DWE (1<<10) /* Debug Wait Enable */
-#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
-#define MSR_IS MSR_IR /* Instruction Space */
-#define MSR_DS MSR_DR /* Data Space */
-#define MSR_PMM (1<<2) /* Performance monitor mark bit */
-
-/* Default MSR for kernel mode. */
-#if defined (CONFIG_40x)
-#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
-#elif defined(CONFIG_BOOKE)
-#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE)
-#endif
-
-/* Special Purpose Registers (SPRNs)*/
-#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
-#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
-#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
-#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
-#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
-#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
-#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
-#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
-#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
-#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
-#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
-#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
-#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
-#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
-#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
-#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
-#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
-#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
-#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
-#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
-#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
-#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
-#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
-#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
-#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
-#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
-#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */
-#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */
-#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */
-#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
-#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
-#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
-#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
-#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
-#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
-#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
-#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
-#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
-#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
-#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
-#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
-#define SPRN_MCSR 0x23C /* Machine Check Status Register */
-#define SPRN_MCAR 0x23D /* Machine Check Address Register */
-#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
-#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
-#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
-#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
-#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
-#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
-#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
-#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
-#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
-#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */
-#define SPRN_PID1 0x279 /* Process ID Register 1 */
-#define SPRN_PID2 0x27A /* Process ID Register 2 */
-#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
-#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
-#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
-#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
-#define SPRN_MMUCR 0x3B2 /* MMU Control Register */
-#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
-#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
-#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
-#define SPRN_SLER 0x3BB /* Little-endian real mode */
-#define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */
-#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
-#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
-#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
-#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
-#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
-#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
-#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
-#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
-#define SPRN_SVR 0x3FF /* System Version Register */
-
-/*
- * SPRs which have conflicting definitions on true Book E versus classic,
- * or IBM 40x.
- */
-#ifdef CONFIG_BOOKE
-#define SPRN_PID 0x030 /* Process ID */
-#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
-#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
-#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
-#define SPRN_DEAR 0x03D /* Data Error Address Register */
-#define SPRN_ESR 0x03E /* Exception Syndrome Register */
-#define SPRN_PIR 0x11E /* Processor Identification Register */
-#define SPRN_DBSR 0x130 /* Debug Status Register */
-#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */
-#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */
-#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */
-#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */
-#define SPRN_DAC1 0x13C /* Data Address Compare 1 */
-#define SPRN_DAC2 0x13D /* Data Address Compare 2 */
-#define SPRN_TSR 0x150 /* Timer Status Register */
-#define SPRN_TCR 0x154 /* Timer Control Register */
-#endif /* Book E */
-#ifdef CONFIG_40x
-#define SPRN_PID 0x3B1 /* Process ID */
-#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
-#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
-#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
-#define SPRN_TSR 0x3D8 /* Timer Status Register */
-#define SPRN_TCR 0x3DA /* Timer Control Register */
-#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
-#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
-#define SPRN_DBSR 0x3F0 /* Debug Status Register */
-#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
-#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
-#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
-#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */
-#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
-#endif
-
-/* Bit definitions for CCR1. */
-#define CCR1_TCS 0x00000080 /* Timer Clock Select */
-
-/* Bit definitions for the MCSR. */
-#ifdef CONFIG_440A
-#define MCSR_MCS 0x80000000 /* Machine Check Summary */
-#define MCSR_IB 0x40000000 /* Instruction PLB Error */
-#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
-#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
-#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
-#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
-#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
-#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
-#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
-#endif
-#ifdef CONFIG_E500
-#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
-#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
-#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
-#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
-#define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */
-#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
-#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */
-#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */
-#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */
-#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */
-#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */
-#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
-#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
-#endif
-#ifdef CONFIG_E200
-#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
-#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */
-#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */
-#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
- fetch for an exception handler */
-#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/
-#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
-#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
- store or cache line push */
-#endif
-
-/* Bit definitions for the DBSR. */
-/*
- * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
- */
-#ifdef CONFIG_BOOKE
-#define DBSR_IC 0x08000000 /* Instruction Completion */
-#define DBSR_BT 0x04000000 /* Branch Taken */
-#define DBSR_TIE 0x01000000 /* Trap Instruction Event */
-#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */
-#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */
-#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */
-#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */
-#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */
-#define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */
-#define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */
-#define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */
-#endif
-#ifdef CONFIG_40x
-#define DBSR_IC 0x80000000 /* Instruction Completion */
-#define DBSR_BT 0x40000000 /* Branch taken */
-#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */
-#define DBSR_IAC1 0x00800000 /* Instruction Address Compare 1 Event */
-#define DBSR_IAC2 0x00400000 /* Instruction Address Compare 2 Event */
-#define DBSR_IAC3 0x00200000 /* Instruction Address Compare 3 Event */
-#define DBSR_IAC4 0x00100000 /* Instruction Address Compare 4 Event */
-#define DBSR_DAC1R 0x00080000 /* Data Address Compare 1 Read Event */
-#define DBSR_DAC1W 0x00040000 /* Data Address Compare 1 Write Event */
-#define DBSR_DAC2R 0x00020000 /* Data Address Compare 2 Read Event */
-#define DBSR_DAC2W 0x00010000 /* Data Address Compare 2 Write Event */
-#endif
-
-/* Bit definitions related to the ESR. */
-#define ESR_MCI 0x80000000 /* Machine Check - Instruction */
-#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
-#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
-#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
-#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
-#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
-#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
-#define ESR_PTR 0x02000000 /* Program Exception - Trap */
-#define ESR_FP 0x01000000 /* Floating Point Operation */
-#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
-#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
-#define ESR_ST 0x00800000 /* Store Operation */
-#define ESR_DLK 0x00200000 /* Data Cache Locking */
-#define ESR_ILK 0x00100000 /* Instr. Cache Locking */
-#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */
-#define ESR_BO 0x00020000 /* Byte Ordering */
-
-/* Bit definitions related to the DBCR0. */
-#define DBCR0_EDM 0x80000000 /* External Debug Mode */
-#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
-#define DBCR0_RST 0x30000000 /* all the bits in the RST field */
-#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
-#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
-#define DBCR0_RST_CORE 0x10000000 /* Core Reset */
-#define DBCR0_RST_NONE 0x00000000 /* No Reset */
-#define DBCR0_IC 0x08000000 /* Instruction Completion */
-#define DBCR0_BT 0x04000000 /* Branch Taken */
-#define DBCR0_EDE 0x02000000 /* Exception Debug Event */
-#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
-#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */
-#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */
-#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */
-#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */
-#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */
-#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */
-#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */
-#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */
-#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */
-#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
-#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
-
-/* Bit definitions related to the TCR. */
-#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
-#define TCR_WP_MASK TCR_WP(3)
-#define WP_2_17 0 /* 2^17 clocks */
-#define WP_2_21 1 /* 2^21 clocks */
-#define WP_2_25 2 /* 2^25 clocks */
-#define WP_2_29 3 /* 2^29 clocks */
-#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
-#define TCR_WRC_MASK TCR_WRC(3)
-#define WRC_NONE 0 /* No reset will occur */
-#define WRC_CORE 1 /* Core reset will occur */
-#define WRC_CHIP 2 /* Chip reset will occur */
-#define WRC_SYSTEM 3 /* System reset will occur */
-#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
-#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
-#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */
-#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
-#define TCR_FP_MASK TCR_FP(3)
-#define FP_2_9 0 /* 2^9 clocks */
-#define FP_2_13 1 /* 2^13 clocks */
-#define FP_2_17 2 /* 2^17 clocks */
-#define FP_2_21 3 /* 2^21 clocks */
-#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
-#define TCR_ARE 0x00400000 /* Auto Reload Enable */
-
-/* Bit definitions for the TSR. */
-#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
-#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
-#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
-#define WRS_NONE 0 /* No WDT reset occurred */
-#define WRS_CORE 1 /* WDT forced core reset */
-#define WRS_CHIP 2 /* WDT forced chip reset */
-#define WRS_SYSTEM 3 /* WDT forced system reset */
-#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
-#define TSR_DIS TSR_PIS /* DEC Interrupt Status */
-#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
-
-/* Bit definitions for the DCCR. */
-#define DCCR_NOCACHE 0 /* Noncacheable */
-#define DCCR_CACHE 1 /* Cacheable */
-
-/* Bit definitions for DCWR. */
-#define DCWR_COPY 0 /* Copy-back */
-#define DCWR_WRITE 1 /* Write-through */
-
-/* Bit definitions for ICCR. */
-#define ICCR_NOCACHE 0 /* Noncacheable */
-#define ICCR_CACHE 1 /* Cacheable */
-
-/* Bit definitions for L1CSR0. */
-#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
-#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
-#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
-#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
-
-/* Bit definitions for L1CSR1. */
-#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
-#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
-#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
-
-/* Bit definitions for SGR. */
-#define SGR_NORMAL 0 /* Speculative fetching allowed. */
-#define SGR_GUARDED 1 /* Speculative fetching disallowed. */
-
-/* Bit definitions for SPEFSCR. */
-#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
-#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
-#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
-#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
-#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
-#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
-#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
-#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
-#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
-#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
-#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
-#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
-#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
-#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
-#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
-#define SPEFSCR_OV 0x00004000 /* Integer overflow */
-#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
-#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
-#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
-#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
-#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
-#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
-#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
-#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
-#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
-#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
-#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
-#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
-
-/*
- * The IBM-403 is an even more odd special case, as it is much
- * older than the IBM-405 series. We put these down here incase someone
- * wishes to support these machines again.
- */
-#ifdef CONFIG_403GCX
-/* Special Purpose Registers (SPRNs)*/
-#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
-#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
-#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
-#define SPRN_TBHI 0x3DC /* Time Base High */
-#define SPRN_TBLO 0x3DD /* Time Base Low */
-#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
-#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
-#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
-#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
-#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
-
-
-/* Bit definitions for the DBCR. */
-#define DBCR_EDM DBCR0_EDM
-#define DBCR_IDM DBCR0_IDM
-#define DBCR_RST(x) (((x) & 0x3) << 28)
-#define DBCR_RST_NONE 0
-#define DBCR_RST_CORE 1
-#define DBCR_RST_CHIP 2
-#define DBCR_RST_SYSTEM 3
-#define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */
-#define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */
-#define DBCR_EDE DBCR0_EDE /* Exception Debug Event */
-#define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */
-#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
-#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
-#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
-#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
-#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
-#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
-#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
-#define DAC_BYTE 0
-#define DAC_HALF 1
-#define DAC_WORD 2
-#define DAC_QUAD 3
-#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
-#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
-#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
-#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
-#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
-#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
-#define DBCR_SIA 0x00000008 /* Second IAC Enable */
-#define DBCR_SDA 0x00000004 /* Second DAC Enable */
-#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
-#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
-#endif /* 403GCX */
-#endif /* __ASM_PPC_REG_BOOKE_H__ */
-#endif /* __KERNEL__ */
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 14/15] powerpc: move asm/mpc85xx.h
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
` (12 preceding siblings ...)
2006-04-05 5:10 ` [PATCH 13/15] powerpc: move asm/reg_booke.h sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 14:17 ` Kumar Gala
2006-04-05 5:10 ` [PATCH 15/15] powerpc: remove include hack sfr
2006-04-05 14:28 ` [PATCH 00/15] powerpc: move some header files Kumar Gala
15 siblings, 1 reply; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/mpc85xx.h | 195 ++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/mpc85xx.h | 198 -----------------------------------------
2 files changed, 195 insertions(+), 198 deletions(-)
create mode 100644 include/asm-powerpc/mpc85xx.h
delete mode 100644 include/asm-ppc/mpc85xx.h
4fc7b6e78d24e11e704ef7b5a1ceb659d3a03cc2
diff --git a/include/asm-powerpc/mpc85xx.h b/include/asm-powerpc/mpc85xx.h
new file mode 100644
index 0000000..4113165
--- /dev/null
+++ b/include/asm-powerpc/mpc85xx.h
@@ -0,0 +1,195 @@
+#ifndef _ASM_POWERPC_MPC85XX_H
+#define _ASM_POWERPC_MPC85XX_H
+/*
+ * MPC85xx definitions
+ *
+ * Maintainer: Kumar Gala <galak@kernel.crashing.org>
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+
+#include <asm/mmu.h>
+
+#ifdef CONFIG_85xx
+
+#ifdef CONFIG_MPC8540_ADS
+#include <platforms/85xx/mpc8540_ads.h>
+#endif
+#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
+#include <platforms/85xx/mpc8555_cds.h>
+#endif
+#ifdef CONFIG_MPC8560_ADS
+#include <platforms/85xx/mpc8560_ads.h>
+#endif
+#ifdef CONFIG_SBC8560
+#include <platforms/85xx/sbc8560.h>
+#endif
+#ifdef CONFIG_STX_GP3
+#include <platforms/85xx/stx_gp3.h>
+#endif
+#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || \
+ defined(CONFIG_TQM8555) || defined(CONFIG_TQM8560)
+#include <platforms/85xx/tqm85xx.h>
+#endif
+
+#define _IO_BASE isa_io_base
+#define _ISA_MEM_BASE isa_mem_base
+#ifdef CONFIG_PCI
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define PCI_DRAM_OFFSET 0
+#endif
+
+/*
+ * The "residual" board information structure the boot loader passes
+ * into the kernel.
+ */
+extern unsigned char __res[];
+
+/* Offset from CCSRBAR */
+#define MPC85xx_CPM_OFFSET (0x80000)
+#define MPC85xx_CPM_SIZE (0x40000)
+#define MPC85xx_DMA_OFFSET (0x21000)
+#define MPC85xx_DMA_SIZE (0x01000)
+#define MPC85xx_DMA0_OFFSET (0x21100)
+#define MPC85xx_DMA0_SIZE (0x00080)
+#define MPC85xx_DMA1_OFFSET (0x21180)
+#define MPC85xx_DMA1_SIZE (0x00080)
+#define MPC85xx_DMA2_OFFSET (0x21200)
+#define MPC85xx_DMA2_SIZE (0x00080)
+#define MPC85xx_DMA3_OFFSET (0x21280)
+#define MPC85xx_DMA3_SIZE (0x00080)
+#define MPC85xx_ENET1_OFFSET (0x24000)
+#define MPC85xx_ENET1_SIZE (0x01000)
+#define MPC85xx_MIIM_OFFSET (0x24520)
+#define MPC85xx_MIIM_SIZE (0x00018)
+#define MPC85xx_ENET2_OFFSET (0x25000)
+#define MPC85xx_ENET2_SIZE (0x01000)
+#define MPC85xx_ENET3_OFFSET (0x26000)
+#define MPC85xx_ENET3_SIZE (0x01000)
+#define MPC85xx_GUTS_OFFSET (0xe0000)
+#define MPC85xx_GUTS_SIZE (0x01000)
+#define MPC85xx_IIC1_OFFSET (0x03000)
+#define MPC85xx_IIC1_SIZE (0x00100)
+#define MPC85xx_OPENPIC_OFFSET (0x40000)
+#define MPC85xx_OPENPIC_SIZE (0x40000)
+#define MPC85xx_PCI1_OFFSET (0x08000)
+#define MPC85xx_PCI1_SIZE (0x01000)
+#define MPC85xx_PCI2_OFFSET (0x09000)
+#define MPC85xx_PCI2_SIZE (0x01000)
+#define MPC85xx_PERFMON_OFFSET (0xe1000)
+#define MPC85xx_PERFMON_SIZE (0x01000)
+#define MPC85xx_SEC2_OFFSET (0x30000)
+#define MPC85xx_SEC2_SIZE (0x10000)
+#define MPC85xx_UART0_OFFSET (0x04500)
+#define MPC85xx_UART0_SIZE (0x00100)
+#define MPC85xx_UART1_OFFSET (0x04600)
+#define MPC85xx_UART1_SIZE (0x00100)
+
+#define MPC85xx_CCSRBAR_SIZE (1024*1024)
+
+/* Let modules/drivers get at CCSRBAR */
+extern phys_addr_t get_ccsrbar(void);
+
+#ifdef MODULE
+#define CCSRBAR get_ccsrbar()
+#else
+#define CCSRBAR BOARD_CCSRBAR
+#endif
+
+enum ppc_sys_devices {
+ MPC85xx_TSEC1,
+ MPC85xx_TSEC2,
+ MPC85xx_FEC,
+ MPC85xx_IIC1,
+ MPC85xx_DMA0,
+ MPC85xx_DMA1,
+ MPC85xx_DMA2,
+ MPC85xx_DMA3,
+ MPC85xx_DUART,
+ MPC85xx_PERFMON,
+ MPC85xx_SEC2,
+ MPC85xx_CPM_SPI,
+ MPC85xx_CPM_I2C,
+ MPC85xx_CPM_USB,
+ MPC85xx_CPM_SCC1,
+ MPC85xx_CPM_SCC2,
+ MPC85xx_CPM_SCC3,
+ MPC85xx_CPM_SCC4,
+ MPC85xx_CPM_FCC1,
+ MPC85xx_CPM_FCC2,
+ MPC85xx_CPM_FCC3,
+ MPC85xx_CPM_MCC1,
+ MPC85xx_CPM_MCC2,
+ MPC85xx_CPM_SMC1,
+ MPC85xx_CPM_SMC2,
+ MPC85xx_eTSEC1,
+ MPC85xx_eTSEC2,
+ MPC85xx_eTSEC3,
+ MPC85xx_eTSEC4,
+ MPC85xx_IIC2,
+ MPC85xx_MDIO,
+ NUM_PPC_SYS_DEVS,
+};
+
+/* Internal interrupts are all Level Sensitive, and Positive Polarity */
+#define MPC85XX_INTERNAL_IRQ_SENSES \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */
+
+#endif /* CONFIG_85xx */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_MPC85XX_H */
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
deleted file mode 100644
index f47002a..0000000
--- a/include/asm-ppc/mpc85xx.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * include/asm-ppc/mpc85xx.h
- *
- * MPC85xx definitions
- *
- * Maintainer: Kumar Gala <galak@kernel.crashing.org>
- *
- * Copyright 2004 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_MPC85xx_H__
-#define __ASM_MPC85xx_H__
-
-#include <linux/config.h>
-#include <asm/mmu.h>
-
-#ifdef CONFIG_85xx
-
-#ifdef CONFIG_MPC8540_ADS
-#include <platforms/85xx/mpc8540_ads.h>
-#endif
-#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
-#include <platforms/85xx/mpc8555_cds.h>
-#endif
-#ifdef CONFIG_MPC8560_ADS
-#include <platforms/85xx/mpc8560_ads.h>
-#endif
-#ifdef CONFIG_SBC8560
-#include <platforms/85xx/sbc8560.h>
-#endif
-#ifdef CONFIG_STX_GP3
-#include <platforms/85xx/stx_gp3.h>
-#endif
-#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || \
- defined(CONFIG_TQM8555) || defined(CONFIG_TQM8560)
-#include <platforms/85xx/tqm85xx.h>
-#endif
-
-#define _IO_BASE isa_io_base
-#define _ISA_MEM_BASE isa_mem_base
-#ifdef CONFIG_PCI
-#define PCI_DRAM_OFFSET pci_dram_offset
-#else
-#define PCI_DRAM_OFFSET 0
-#endif
-
-/*
- * The "residual" board information structure the boot loader passes
- * into the kernel.
- */
-extern unsigned char __res[];
-
-/* Offset from CCSRBAR */
-#define MPC85xx_CPM_OFFSET (0x80000)
-#define MPC85xx_CPM_SIZE (0x40000)
-#define MPC85xx_DMA_OFFSET (0x21000)
-#define MPC85xx_DMA_SIZE (0x01000)
-#define MPC85xx_DMA0_OFFSET (0x21100)
-#define MPC85xx_DMA0_SIZE (0x00080)
-#define MPC85xx_DMA1_OFFSET (0x21180)
-#define MPC85xx_DMA1_SIZE (0x00080)
-#define MPC85xx_DMA2_OFFSET (0x21200)
-#define MPC85xx_DMA2_SIZE (0x00080)
-#define MPC85xx_DMA3_OFFSET (0x21280)
-#define MPC85xx_DMA3_SIZE (0x00080)
-#define MPC85xx_ENET1_OFFSET (0x24000)
-#define MPC85xx_ENET1_SIZE (0x01000)
-#define MPC85xx_MIIM_OFFSET (0x24520)
-#define MPC85xx_MIIM_SIZE (0x00018)
-#define MPC85xx_ENET2_OFFSET (0x25000)
-#define MPC85xx_ENET2_SIZE (0x01000)
-#define MPC85xx_ENET3_OFFSET (0x26000)
-#define MPC85xx_ENET3_SIZE (0x01000)
-#define MPC85xx_GUTS_OFFSET (0xe0000)
-#define MPC85xx_GUTS_SIZE (0x01000)
-#define MPC85xx_IIC1_OFFSET (0x03000)
-#define MPC85xx_IIC1_SIZE (0x00100)
-#define MPC85xx_OPENPIC_OFFSET (0x40000)
-#define MPC85xx_OPENPIC_SIZE (0x40000)
-#define MPC85xx_PCI1_OFFSET (0x08000)
-#define MPC85xx_PCI1_SIZE (0x01000)
-#define MPC85xx_PCI2_OFFSET (0x09000)
-#define MPC85xx_PCI2_SIZE (0x01000)
-#define MPC85xx_PERFMON_OFFSET (0xe1000)
-#define MPC85xx_PERFMON_SIZE (0x01000)
-#define MPC85xx_SEC2_OFFSET (0x30000)
-#define MPC85xx_SEC2_SIZE (0x10000)
-#define MPC85xx_UART0_OFFSET (0x04500)
-#define MPC85xx_UART0_SIZE (0x00100)
-#define MPC85xx_UART1_OFFSET (0x04600)
-#define MPC85xx_UART1_SIZE (0x00100)
-
-#define MPC85xx_CCSRBAR_SIZE (1024*1024)
-
-/* Let modules/drivers get at CCSRBAR */
-extern phys_addr_t get_ccsrbar(void);
-
-#ifdef MODULE
-#define CCSRBAR get_ccsrbar()
-#else
-#define CCSRBAR BOARD_CCSRBAR
-#endif
-
-enum ppc_sys_devices {
- MPC85xx_TSEC1,
- MPC85xx_TSEC2,
- MPC85xx_FEC,
- MPC85xx_IIC1,
- MPC85xx_DMA0,
- MPC85xx_DMA1,
- MPC85xx_DMA2,
- MPC85xx_DMA3,
- MPC85xx_DUART,
- MPC85xx_PERFMON,
- MPC85xx_SEC2,
- MPC85xx_CPM_SPI,
- MPC85xx_CPM_I2C,
- MPC85xx_CPM_USB,
- MPC85xx_CPM_SCC1,
- MPC85xx_CPM_SCC2,
- MPC85xx_CPM_SCC3,
- MPC85xx_CPM_SCC4,
- MPC85xx_CPM_FCC1,
- MPC85xx_CPM_FCC2,
- MPC85xx_CPM_FCC3,
- MPC85xx_CPM_MCC1,
- MPC85xx_CPM_MCC2,
- MPC85xx_CPM_SMC1,
- MPC85xx_CPM_SMC2,
- MPC85xx_eTSEC1,
- MPC85xx_eTSEC2,
- MPC85xx_eTSEC3,
- MPC85xx_eTSEC4,
- MPC85xx_IIC2,
- MPC85xx_MDIO,
- NUM_PPC_SYS_DEVS,
-};
-
-/* Internal interrupts are all Level Sensitive, and Positive Polarity */
-#define MPC85XX_INTERNAL_IRQ_SENSES \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */
-
-#endif /* CONFIG_85xx */
-#endif /* __ASM_MPC85xx_H__ */
-#endif /* __KERNEL__ */
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 15/15] powerpc: remove include hack
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
` (13 preceding siblings ...)
2006-04-05 5:10 ` [PATCH 14/15] powerpc: move asm/mpc85xx.h sfr
@ 2006-04-05 5:10 ` sfr
2006-04-05 14:28 ` [PATCH 00/15] powerpc: move some header files Kumar Gala
15 siblings, 0 replies; 27+ messages in thread
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
From: Stephen Rothwell <sfr@canb.auug.org.au>
This patch removes the Makefile hack that allows including files from
include/asm-ppc when doing a 32bit ARCH=powerpc build. Build tested
for all three 32bit defconfigs and pseries_defconfig.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
arch/powerpc/Makefile | 21 +++------------------
1 files changed, 3 insertions(+), 18 deletions(-)
50d33a5568cebd00d7148e90a6b5b6865f029602
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 6ec84d3..f757532 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -36,7 +36,7 @@ export CROSS32CC CROSS32AS CROSS32LD CRO
KBUILD_DEFCONFIG := $(shell uname -m)_defconfig
ifeq ($(CONFIG_PPC64),y)
-OLDARCH := ppc64
+UTS_MACHINE := ppc64
SZ := 64
new_nm := $(shell if $(NM) --help 2>&1 | grep -- '--synthetic' > /dev/null; then echo y; else echo n; fi)
@@ -46,12 +46,10 @@ NM := $(NM) --synthetic
endif
else
-OLDARCH := ppc
+UTS_MACHINE := ppc
SZ := 32
endif
-UTS_MACHINE := $(OLDARCH)
-
ifeq ($(HAS_BIARCH),y)
override AS += -a$(SZ)
override LD += -m elf$(SZ)ppc
@@ -60,8 +58,7 @@ endif
LDFLAGS_vmlinux := -Bstatic
-# The -Iarch/$(ARCH)/include is temporary while we are merging
-CPPFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH) -Iarch/$(ARCH)/include
+CPPFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH)
AFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH)
CFLAGS-$(CONFIG_PPC64) := -mminimal-toc -mtraceback=none -mcall-aixdesc
CFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH) -ffixed-r2 -mmultiple
@@ -69,9 +66,6 @@ CPPFLAGS += $(CPPFLAGS-y)
AFLAGS += $(AFLAGS-y)
CFLAGS += -msoft-float -pipe $(CFLAGS-y)
CPP = $(CC) -E $(CFLAGS)
-# Temporary hack until we have migrated to asm-powerpc
-LINUXINCLUDE-$(CONFIG_PPC32) := -Iarch/$(ARCH)/include
-LINUXINCLUDE += $(LINUXINCLUDE-y)
CHECKFLAGS += -m$(SZ) -D__powerpc__ -D__powerpc$(SZ)__
@@ -165,18 +159,9 @@ archclean:
$(Q)$(MAKE) $(clean)=$(boot)
archmrproper:
- $(Q)rm -rf arch/$(ARCH)/include
archprepare: checkbin
-ifeq ($(CONFIG_PPC32),y)
-# Temporary hack until we have migrated to asm-powerpc
-include/asm: arch/$(ARCH)/include/asm
-arch/$(ARCH)/include/asm: FORCE
- $(Q)if [ ! -d arch/$(ARCH)/include ]; then mkdir -p arch/$(ARCH)/include; fi
- $(Q)ln -fsn $(srctree)/include/asm-$(OLDARCH) arch/$(ARCH)/include/asm
-endif
-
# Use the file '.tmp_gas_check' for binutils tests, as gas won't output
# to stdout and these checks are run even on install targets.
TOUT := .tmp_gas_check
--
1.2.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH 04/15] powerpc: move asm/bootinfo.h
2006-04-05 5:10 ` [PATCH 04/15] powerpc: move asm/bootinfo.h sfr
@ 2006-04-05 14:05 ` Kumar Gala
0 siblings, 0 replies; 27+ messages in thread
From: Kumar Gala @ 2006-04-05 14:05 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev, paulus
Nack, we are using the flat dev tree so old boot methods should stay
in arch/ppc.
- k
On Apr 5, 2006, at 12:10 AM, sfr@canb.auug.org.au wrote:
> From: Stephen Rothwell <sfr@canb.auug.org.au>
>
> Since files in arch/powerpc now depend on asm/bootinfo.h,
> move it to include/asm-powerpc.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
>
> ---
>
> include/asm-powerpc/bootinfo.h | 52 +++++++++++++++++++++++++++++
> +++++++++++
> include/asm-ppc/bootinfo.h | 52
> ----------------------------------------
> 2 files changed, 52 insertions(+), 52 deletions(-)
> create mode 100644 include/asm-powerpc/bootinfo.h
> delete mode 100644 include/asm-ppc/bootinfo.h
>
> 355987a8cf0cf4b644e83b8268a9a34cf4524ee0
> diff --git a/include/asm-powerpc/bootinfo.h b/include/asm-powerpc/
> bootinfo.h
> new file mode 100644
> index 0000000..231c534
> --- /dev/null
> +++ b/include/asm-powerpc/bootinfo.h
> @@ -0,0 +1,52 @@
> +#ifndef _ASM_POWERPC_BOOTINFO_H
> +#define _ASM_POWERPC_BOOTINFO_H
> +
> +/*
> + * Non-machine dependent bootinfo structure. Basic idea
> + * borrowed from the m68k.
> + *
> + * Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org>
> + */
> +
> +#ifdef __KERNEL__
> +
> +#include <asm/page.h>
> +
> +#if defined(CONFIG_APUS) && !defined(__BOOTER__)
> +#include <asm-m68k/bootinfo.h>
> +#else
> +
> +struct bi_record {
> + unsigned long tag; /* tag ID */
> + unsigned long size; /* size of record (in bytes) */
> + unsigned long data[0]; /* data */
> +};
> +
> +#define BI_FIRST 0x1010 /* first record - marker */
> +#define BI_LAST 0x1011 /* last record - marker */
> +#define BI_CMD_LINE 0x1012
> +#define BI_BOOTLOADER_ID 0x1013
> +#define BI_INITRD 0x1014
> +#define BI_SYSMAP 0x1015
> +#define BI_MACHTYPE 0x1016
> +#define BI_MEMSIZE 0x1017
> +#define BI_BOARD_INFO 0x1018
> +
> +extern struct bi_record *find_bootinfo(void);
> +extern void bootinfo_init(struct bi_record *rec);
> +extern void bootinfo_append(unsigned long tag, unsigned long size,
> void * data);
> +extern void parse_bootinfo(struct bi_record *rec);
> +extern unsigned long boot_mem_size;
> +
> +static inline struct bi_record *
> +bootinfo_addr(unsigned long offset)
> +{
> +
> + return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1,
> + (1 << 20));
> +}
> +#endif /* CONFIG_APUS */
> +
> +
> +#endif /* __KERNEL__ */
> +#endif /* _ASM_POWERPC_BOOTINFO_H */
> diff --git a/include/asm-ppc/bootinfo.h b/include/asm-ppc/bootinfo.h
> deleted file mode 100644
> index 93d955c..0000000
> --- a/include/asm-ppc/bootinfo.h
> +++ /dev/null
> @@ -1,52 +0,0 @@
> -/*
> - * Non-machine dependent bootinfo structure. Basic idea
> - * borrowed from the m68k.
> - *
> - * Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org>
> - */
> -
> -#ifdef __KERNEL__
> -#ifndef _PPC_BOOTINFO_H
> -#define _PPC_BOOTINFO_H
> -
> -#include <linux/config.h>
> -#include <asm/page.h>
> -
> -#if defined(CONFIG_APUS) && !defined(__BOOTER__)
> -#include <asm-m68k/bootinfo.h>
> -#else
> -
> -struct bi_record {
> - unsigned long tag; /* tag ID */
> - unsigned long size; /* size of record (in bytes) */
> - unsigned long data[0]; /* data */
> -};
> -
> -#define BI_FIRST 0x1010 /* first record - marker */
> -#define BI_LAST 0x1011 /* last record - marker */
> -#define BI_CMD_LINE 0x1012
> -#define BI_BOOTLOADER_ID 0x1013
> -#define BI_INITRD 0x1014
> -#define BI_SYSMAP 0x1015
> -#define BI_MACHTYPE 0x1016
> -#define BI_MEMSIZE 0x1017
> -#define BI_BOARD_INFO 0x1018
> -
> -extern struct bi_record *find_bootinfo(void);
> -extern void bootinfo_init(struct bi_record *rec);
> -extern void bootinfo_append(unsigned long tag, unsigned long size,
> void * data);
> -extern void parse_bootinfo(struct bi_record *rec);
> -extern unsigned long boot_mem_size;
> -
> -static inline struct bi_record *
> -bootinfo_addr(unsigned long offset)
> -{
> -
> - return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1,
> - (1 << 20));
> -}
> -#endif /* CONFIG_APUS */
> -
> -
> -#endif /* _PPC_BOOTINFO_H */
> -#endif /* __KERNEL__ */
> --
> 1.2.4
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 08/15] powerpc: move asm/open_pic.h
2006-04-05 5:10 ` [PATCH 08/15] powerpc: move asm/open_pic.h sfr
@ 2006-04-05 14:07 ` Kumar Gala
0 siblings, 0 replies; 27+ messages in thread
From: Kumar Gala @ 2006-04-05 14:07 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev, paulus
I'd need to check, but I dont think we should move this since arch/
powerpc is using mpic to handle openpic and I'm guessing it has its
own headers.
- k
On Apr 5, 2006, at 12:10 AM, sfr@canb.auug.org.au wrote:
> From: Stephen Rothwell <sfr@canb.auug.org.au>
>
> Since the ARCH=powerpc build depends on this file, move it to
> include/asm-powerpc.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
>
> ---
>
> include/asm-powerpc/open_pic.h | 99 +++++++++++++++++++++++++++++
> +++++++++++
> include/asm-ppc/open_pic.h | 99
> ----------------------------------------
> 2 files changed, 99 insertions(+), 99 deletions(-)
> create mode 100644 include/asm-powerpc/open_pic.h
> delete mode 100644 include/asm-ppc/open_pic.h
>
> 54316678b9e6aad8349f2df50dadd2597b675804
> diff --git a/include/asm-powerpc/open_pic.h b/include/asm-powerpc/
> open_pic.h
> new file mode 100644
> index 0000000..3f197cf
> --- /dev/null
> +++ b/include/asm-powerpc/open_pic.h
> @@ -0,0 +1,99 @@
> +#ifndef _ASM_POWERPC_OPEN_PIC_H
> +#define _ASM_POWERPC_OPEN_PIC_H
> +
> +/*
> + * include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling
> + *
> + * Copyright (C) 1997 Geert Uytterhoeven
> + *
> + * This file is subject to the terms and conditions of the GNU
> General Public
> + * License. See the file COPYING in the main directory of this
> archive
> + * for more details.
> + *
> + */
> +
> +#include <linux/irq.h>
> +
> +#define OPENPIC_SIZE 0x40000
> +
> +/*
> + * Non-offset'ed vector numbers
> + */
> +
> +#define OPENPIC_VEC_TIMER 110 /* and up */
> +#define OPENPIC_VEC_IPI 118 /* and up */
> +#define OPENPIC_VEC_SPURIOUS 255
> +
> +/* Priorities */
> +#define OPENPIC_PRIORITY_IPI_BASE 10
> +#define OPENPIC_PRIORITY_DEFAULT 4
> +#define OPENPIC_PRIORITY_NMI 9
> +
> +/* OpenPIC IRQ controller structure */
> +extern struct hw_interrupt_type open_pic;
> +
> +/* OpenPIC IPI controller structure */
> +#ifdef CONFIG_SMP
> +extern struct hw_interrupt_type open_pic_ipi;
> +#endif /* CONFIG_SMP */
> +
> +extern u_int OpenPIC_NumInitSenses;
> +extern u_char *OpenPIC_InitSenses;
> +extern void __iomem * OpenPIC_Addr;
> +extern int epic_serial_mode;
> +
> +/* Exported functions */
> +extern void openpic_set_sources(int first_irq, int num_irqs, void
> __iomem *isr);
> +extern void openpic_init(int linux_irq_offset);
> +extern void openpic_init_nmi_irq(u_int irq);
> +extern void openpic_set_irq_priority(u_int irq, u_int pri);
> +extern void openpic_hookup_cascade(u_int irq, char *name,
> + int (*cascade_fn)(struct pt_regs *));
> +extern u_int openpic_irq(void);
> +extern void openpic_eoi(void);
> +extern void openpic_request_IPIs(void);
> +extern void do_openpic_setup_cpu(void);
> +extern int openpic_get_irq(struct pt_regs *regs);
> +extern void openpic_reset_processor_phys(u_int cpumask);
> +extern void openpic_setup_ISU(int isu_num, unsigned long addr);
> +extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
> +extern void smp_openpic_message_pass(int target, int msg);
> +extern void openpic_set_k2_cascade(int irq);
> +extern void openpic_set_priority(u_int pri);
> +extern u_int openpic_get_priority(void);
> +
> +extern inline int openpic_to_irq(int irq)
> +{
> + /* IRQ 0 usually means 'disabled'.. don't mess with it
> + * exceptions to this (sandpoint maybe?)
> + * shouldn't use openpic_to_irq
> + */
> + if (irq != 0){
> + return irq += NUM_8259_INTERRUPTS;
> + } else {
> + return 0;
> + }
> +}
> +/* Support for second openpic on G5 macs */
> +
> +// FIXME: To be replaced by sane cascaded controller management */
> +
> +#define PMAC_OPENPIC2_OFFSET 128
> +
> +#define OPENPIC2_VEC_TIMER 110 /* and up */
> +#define OPENPIC2_VEC_IPI 118 /* and up */
> +#define OPENPIC2_VEC_SPURIOUS 127
> +
> +
> +extern void* OpenPIC2_Addr;
> +
> +/* Exported functions */
> +extern void openpic2_set_sources(int first_irq, int num_irqs, void
> *isr);
> +extern void openpic2_init(int linux_irq_offset);
> +extern void openpic2_init_nmi_irq(u_int irq);
> +extern u_int openpic2_irq(void);
> +extern void openpic2_eoi(void);
> +extern int openpic2_get_irq(struct pt_regs *regs);
> +extern void openpic2_setup_ISU(int isu_num, unsigned long addr);
> +
> +#endif /* _ASM_POWERPC_OPEN_PIC_H */
> diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h
> deleted file mode 100644
> index ec2f466..0000000
> --- a/include/asm-ppc/open_pic.h
> +++ /dev/null
> @@ -1,99 +0,0 @@
> -/*
> - * include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling
> - *
> - * Copyright (C) 1997 Geert Uytterhoeven
> - *
> - * This file is subject to the terms and conditions of the GNU
> General Public
> - * License. See the file COPYING in the main directory of this
> archive
> - * for more details.
> - *
> - */
> -
> -#ifndef _PPC_KERNEL_OPEN_PIC_H
> -#define _PPC_KERNEL_OPEN_PIC_H
> -
> -#include <linux/config.h>
> -#include <linux/irq.h>
> -
> -#define OPENPIC_SIZE 0x40000
> -
> -/*
> - * Non-offset'ed vector numbers
> - */
> -
> -#define OPENPIC_VEC_TIMER 110 /* and up */
> -#define OPENPIC_VEC_IPI 118 /* and up */
> -#define OPENPIC_VEC_SPURIOUS 255
> -
> -/* Priorities */
> -#define OPENPIC_PRIORITY_IPI_BASE 10
> -#define OPENPIC_PRIORITY_DEFAULT 4
> -#define OPENPIC_PRIORITY_NMI 9
> -
> -/* OpenPIC IRQ controller structure */
> -extern struct hw_interrupt_type open_pic;
> -
> -/* OpenPIC IPI controller structure */
> -#ifdef CONFIG_SMP
> -extern struct hw_interrupt_type open_pic_ipi;
> -#endif /* CONFIG_SMP */
> -
> -extern u_int OpenPIC_NumInitSenses;
> -extern u_char *OpenPIC_InitSenses;
> -extern void __iomem * OpenPIC_Addr;
> -extern int epic_serial_mode;
> -
> -/* Exported functions */
> -extern void openpic_set_sources(int first_irq, int num_irqs, void
> __iomem *isr);
> -extern void openpic_init(int linux_irq_offset);
> -extern void openpic_init_nmi_irq(u_int irq);
> -extern void openpic_set_irq_priority(u_int irq, u_int pri);
> -extern void openpic_hookup_cascade(u_int irq, char *name,
> - int (*cascade_fn)(struct pt_regs *));
> -extern u_int openpic_irq(void);
> -extern void openpic_eoi(void);
> -extern void openpic_request_IPIs(void);
> -extern void do_openpic_setup_cpu(void);
> -extern int openpic_get_irq(struct pt_regs *regs);
> -extern void openpic_reset_processor_phys(u_int cpumask);
> -extern void openpic_setup_ISU(int isu_num, unsigned long addr);
> -extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
> -extern void smp_openpic_message_pass(int target, int msg);
> -extern void openpic_set_k2_cascade(int irq);
> -extern void openpic_set_priority(u_int pri);
> -extern u_int openpic_get_priority(void);
> -
> -extern inline int openpic_to_irq(int irq)
> -{
> - /* IRQ 0 usually means 'disabled'.. don't mess with it
> - * exceptions to this (sandpoint maybe?)
> - * shouldn't use openpic_to_irq
> - */
> - if (irq != 0){
> - return irq += NUM_8259_INTERRUPTS;
> - } else {
> - return 0;
> - }
> -}
> -/* Support for second openpic on G5 macs */
> -
> -// FIXME: To be replaced by sane cascaded controller management */
> -
> -#define PMAC_OPENPIC2_OFFSET 128
> -
> -#define OPENPIC2_VEC_TIMER 110 /* and up */
> -#define OPENPIC2_VEC_IPI 118 /* and up */
> -#define OPENPIC2_VEC_SPURIOUS 127
> -
> -
> -extern void* OpenPIC2_Addr;
> -
> -/* Exported functions */
> -extern void openpic2_set_sources(int first_irq, int num_irqs, void
> *isr);
> -extern void openpic2_init(int linux_irq_offset);
> -extern void openpic2_init_nmi_irq(u_int irq);
> -extern u_int openpic2_irq(void);
> -extern void openpic2_eoi(void);
> -extern int openpic2_get_irq(struct pt_regs *regs);
> -extern void openpic2_setup_ISU(int isu_num, unsigned long addr);
> -#endif /* _PPC_KERNEL_OPEN_PIC_H */
> --
> 1.2.4
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 11/15] powerpc: move asm/ocp.h
2006-04-05 5:10 ` [PATCH 11/15] powerpc: move asm/ocp.h sfr
@ 2006-04-05 14:07 ` Kumar Gala
0 siblings, 0 replies; 27+ messages in thread
From: Kumar Gala @ 2006-04-05 14:07 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev, paulus
Nack. OCP should not exist in arch/powerpc so leave this header where
it is.
- k
On Apr 5, 2006, at 12:10 AM, sfr@canb.auug.org.au wrote:
> From: Stephen Rothwell <sfr@canb.auug.org.au>
>
> Since the ARCH=powerpc build depends on this file, move it to
> include/asm-powerpc.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
>
> ---
>
> include/asm-powerpc/ocp.h | 206 ++++++++++++++++++++++++++++++++++
> +++++++++++
> include/asm-ppc/ocp.h | 207
> ---------------------------------------------
> 2 files changed, 206 insertions(+), 207 deletions(-)
> create mode 100644 include/asm-powerpc/ocp.h
> delete mode 100644 include/asm-ppc/ocp.h
>
> c7b417812dc2ebece32356c0a5e93966de9ba2cd
> diff --git a/include/asm-powerpc/ocp.h b/include/asm-powerpc/ocp.h
> new file mode 100644
> index 0000000..8916c52
> --- /dev/null
> +++ b/include/asm-powerpc/ocp.h
> @@ -0,0 +1,206 @@
> +#ifndef _ASM_POWERPC_OCP_H
> +#define _ASM_POWERPC_OCP_H
> +/*
> + * ocp.h
> + *
> + * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
> + * Mipsys - France
> + *
> + * Derived from work (c) Armin Kuster akuster@pacbell.net
> + *
> + * Additional support and port to 2.6 LDM/sysfs by
> + * Matt Porter <mporter@kernel.crashing.org>
> + * Copyright 2003-2004 MontaVista Software, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + *
> + * TODO: - Add get/put interface & fixup locking to provide same
> API for
> + * 2.4 and 2.5
> + * - Rework PM callbacks
> + */
> +
> +#ifdef __KERNEL__
> +
> +#include <linux/init.h>
> +#include <linux/list.h>
> +#include <linux/devfs_fs_kernel.h>
> +#include <linux/device.h>
> +
> +#include <asm/mmu.h>
> +#include <asm/ocp_ids.h>
> +#include <asm/rwsem.h>
> +#include <asm/semaphore.h>
> +
> +#ifdef CONFIG_PPC_OCP
> +
> +#define OCP_MAX_IRQS 7
> +#define MAX_EMACS 4
> +#define OCP_IRQ_NA -1 /* used when ocp device does not have an irq */
> +#define OCP_IRQ_MUL -2 /* used for ocp devices with multiply irqs */
> +#define OCP_NULL_TYPE -1 /* used to mark end of list */
> +#define OCP_CPM_NA 0 /* No Clock or Power Management avaliable */
> +#define OCP_PADDR_NA 0 /* No MMIO registers */
> +
> +#define OCP_ANY_ID (~0)
> +#define OCP_ANY_INDEX -1
> +
> +extern struct list_head ocp_devices;
> +extern struct rw_semaphore ocp_devices_sem;
> +
> +struct ocp_device_id {
> + unsigned int vendor, function; /* Vendor and function ID or
> OCP_ANY_ID */
> + unsigned long driver_data; /* Data private to the driver */
> +};
> +
> +
> +/*
> + * Static definition of an OCP device.
> + *
> + * @vendor: Vendor code. It is _STRONGLY_ discouraged to use
> + * the vendor code as a way to match a unique device,
> + * though I kept that possibility open, you should
> + * really define different function codes for different
> + * device types
> + * @function: This is the function code for this device.
> + * @index: This index is used for mapping the Nth function of a
> + * given core. This is typically used for cross-driver
> + * matching, like looking for a given MAL or ZMII from
> + * an EMAC or for getting to the proper set of DCRs.
> + * Indices are no longer magically calculated based on
> + * structure ordering, they have to be actually coded
> + * into the ocp_def to avoid any possible confusion
> + * I _STRONGLY_ (again ? wow !) encourage anybody relying
> + * on index mapping to encode the "target" index in an
> + * associated structure pointed to by "additions", see
> + * how it's done for the EMAC driver.
> + * @paddr: Device physical address (may not mean anything...)
> + * @irq: Interrupt line for this device (TODO: think about
> making
> + * an array with this)
> + * @pm: Currently, contains the bitmask in CPMFR DCR for
> the device
> + * @additions: Optionally points to a function specific structure
> + * providing additional informations for a given device
> + * instance. It's currently used by the EMAC driver
> for MAL
> + * channel & ZMII port mapping among others.
> + * @show: Optionally points to a function specific structure
> + * providing a sysfs show routine for additions fields.
> + */
> +struct ocp_def {
> + unsigned int vendor;
> + unsigned int function;
> + int index;
> + phys_addr_t paddr;
> + int irq;
> + unsigned long pm;
> + void *additions;
> + void (*show)(struct device *);
> +};
> +
> +
> +/* Struct for a given device instance */
> +struct ocp_device {
> + struct list_head link;
> + char name[80]; /* device name */
> + struct ocp_def *def; /* device definition */
> + void *drvdata; /* driver data for this device */
> + struct ocp_driver *driver;
> + u32 current_state; /* Current operating state. In ACPI-speak,
> + this is D0-D3, D0 being fully functional,
> + and D3 being off. */
> + struct device dev;
> +};
> +
> +struct ocp_driver {
> + struct list_head node;
> + char *name;
> + const struct ocp_device_id *id_table; /* NULL if wants all
> devices */
> + int (*probe) (struct ocp_device *dev); /* New device inserted */
> + void (*remove) (struct ocp_device *dev); /* Device removed (NULL
> if not a hot-plug capable driver) */
> + int (*suspend) (struct ocp_device *dev, pm_message_t state); /*
> Device suspended */
> + int (*resume) (struct ocp_device *dev); /*
> Device woken up */
> + struct device_driver driver;
> +};
> +
> +#define to_ocp_dev(n) container_of(n, struct ocp_device, dev)
> +#define to_ocp_drv(n) container_of(n, struct ocp_driver, driver)
> +
> +/* Similar to the helpers above, these manipulate per-ocp_dev
> + * driver-specific data. Currently stored as ocp_dev::ocpdev,
> + * a void pointer, but it is not present on older kernels.
> + */
> +static inline void *
> +ocp_get_drvdata(struct ocp_device *pdev)
> +{
> + return pdev->drvdata;
> +}
> +
> +static inline void
> +ocp_set_drvdata(struct ocp_device *pdev, void *data)
> +{
> + pdev->drvdata = data;
> +}
> +
> +#if defined (CONFIG_PM)
> +/*
> + * This is right for the IBM 405 and 440 but will need to be
> + * generalized if the OCP stuff gets used on other processors.
> + */
> +static inline void
> +ocp_force_power_off(struct ocp_device *odev)
> +{
> + mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm);
> +}
> +
> +static inline void
> +ocp_force_power_on(struct ocp_device *odev)
> +{
> + mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm);
> +}
> +#else
> +#define ocp_force_power_off(x) (void)(x)
> +#define ocp_force_power_on(x) (void)(x)
> +#endif
> +
> +/* Register/Unregister an OCP driver */
> +extern int ocp_register_driver(struct ocp_driver *drv);
> +extern void ocp_unregister_driver(struct ocp_driver *drv);
> +
> +/* Build list of devices */
> +extern int ocp_early_init(void) __init;
> +
> +/* Find a device by index */
> +extern struct ocp_device *ocp_find_device(unsigned int vendor,
> unsigned int function, int index);
> +
> +/* Get a def by index */
> +extern struct ocp_def *ocp_get_one_device(unsigned int vendor,
> unsigned int function, int index);
> +
> +/* Add a device by index */
> +extern int ocp_add_one_device(struct ocp_def *def);
> +
> +/* Remove a device by index */
> +extern int ocp_remove_one_device(unsigned int vendor, unsigned int
> function, int index);
> +
> +/* Iterate over devices and execute a routine */
> +extern void ocp_for_each_device(void(*callback)(struct ocp_device
> *, void *arg), void *arg);
> +
> +/* Sysfs support */
> +#define OCP_SYSFS_ADDTL(type, format, name, field) \
> +static ssize_t \
> +show_##name##_##field(struct device *dev, struct device_attribute
> *attr, char *buf) \
> +{ \
> + struct ocp_device *odev = to_ocp_dev(dev); \
> + type *add = odev->def->additions; \
> + \
> + return sprintf(buf, format, add->field); \
> +} \
> +static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field,
> NULL);
> +
> +#ifdef CONFIG_IBM_OCP
> +#include <asm/ibm_ocp.h>
> +#endif
> +
> +#endif /* CONFIG_PPC_OCP */
> +#endif /* __KERNEL__ */
> +#endif /* _ASM_POWERPC_OCP_H */
> diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h
> deleted file mode 100644
> index 983116f..0000000
> --- a/include/asm-ppc/ocp.h
> +++ /dev/null
> @@ -1,207 +0,0 @@
> -/*
> - * ocp.h
> - *
> - * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
> - * Mipsys - France
> - *
> - * Derived from work (c) Armin Kuster akuster@pacbell.net
> - *
> - * Additional support and port to 2.6 LDM/sysfs by
> - * Matt Porter <mporter@kernel.crashing.org>
> - * Copyright 2003-2004 MontaVista Software, Inc.
> - *
> - * This program is free software; you can redistribute it and/or
> modify it
> - * under the terms of the GNU General Public License as
> published by the
> - * Free Software Foundation; either version 2 of the License, or
> (at your
> - * option) any later version.
> - *
> - * TODO: - Add get/put interface & fixup locking to provide same
> API for
> - * 2.4 and 2.5
> - * - Rework PM callbacks
> - */
> -
> -#ifdef __KERNEL__
> -#ifndef __OCP_H__
> -#define __OCP_H__
> -
> -#include <linux/init.h>
> -#include <linux/list.h>
> -#include <linux/config.h>
> -#include <linux/devfs_fs_kernel.h>
> -#include <linux/device.h>
> -
> -#include <asm/mmu.h>
> -#include <asm/ocp_ids.h>
> -#include <asm/rwsem.h>
> -#include <asm/semaphore.h>
> -
> -#ifdef CONFIG_PPC_OCP
> -
> -#define OCP_MAX_IRQS 7
> -#define MAX_EMACS 4
> -#define OCP_IRQ_NA -1 /* used when ocp device does not have an irq */
> -#define OCP_IRQ_MUL -2 /* used for ocp devices with multiply irqs */
> -#define OCP_NULL_TYPE -1 /* used to mark end of list */
> -#define OCP_CPM_NA 0 /* No Clock or Power Management avaliable */
> -#define OCP_PADDR_NA 0 /* No MMIO registers */
> -
> -#define OCP_ANY_ID (~0)
> -#define OCP_ANY_INDEX -1
> -
> -extern struct list_head ocp_devices;
> -extern struct rw_semaphore ocp_devices_sem;
> -
> -struct ocp_device_id {
> - unsigned int vendor, function; /* Vendor and function ID or
> OCP_ANY_ID */
> - unsigned long driver_data; /* Data private to the driver */
> -};
> -
> -
> -/*
> - * Static definition of an OCP device.
> - *
> - * @vendor: Vendor code. It is _STRONGLY_ discouraged to use
> - * the vendor code as a way to match a unique device,
> - * though I kept that possibility open, you should
> - * really define different function codes for different
> - * device types
> - * @function: This is the function code for this device.
> - * @index: This index is used for mapping the Nth function of a
> - * given core. This is typically used for cross-driver
> - * matching, like looking for a given MAL or ZMII from
> - * an EMAC or for getting to the proper set of DCRs.
> - * Indices are no longer magically calculated based on
> - * structure ordering, they have to be actually coded
> - * into the ocp_def to avoid any possible confusion
> - * I _STRONGLY_ (again ? wow !) encourage anybody relying
> - * on index mapping to encode the "target" index in an
> - * associated structure pointed to by "additions", see
> - * how it's done for the EMAC driver.
> - * @paddr: Device physical address (may not mean anything...)
> - * @irq: Interrupt line for this device (TODO: think about
> making
> - * an array with this)
> - * @pm: Currently, contains the bitmask in CPMFR DCR for
> the device
> - * @additions: Optionally points to a function specific structure
> - * providing additional informations for a given device
> - * instance. It's currently used by the EMAC driver
> for MAL
> - * channel & ZMII port mapping among others.
> - * @show: Optionally points to a function specific structure
> - * providing a sysfs show routine for additions fields.
> - */
> -struct ocp_def {
> - unsigned int vendor;
> - unsigned int function;
> - int index;
> - phys_addr_t paddr;
> - int irq;
> - unsigned long pm;
> - void *additions;
> - void (*show)(struct device *);
> -};
> -
> -
> -/* Struct for a given device instance */
> -struct ocp_device {
> - struct list_head link;
> - char name[80]; /* device name */
> - struct ocp_def *def; /* device definition */
> - void *drvdata; /* driver data for this device */
> - struct ocp_driver *driver;
> - u32 current_state; /* Current operating state. In ACPI-speak,
> - this is D0-D3, D0 being fully functional,
> - and D3 being off. */
> - struct device dev;
> -};
> -
> -struct ocp_driver {
> - struct list_head node;
> - char *name;
> - const struct ocp_device_id *id_table; /* NULL if wants all
> devices */
> - int (*probe) (struct ocp_device *dev); /* New device inserted */
> - void (*remove) (struct ocp_device *dev); /* Device removed (NULL
> if not a hot-plug capable driver) */
> - int (*suspend) (struct ocp_device *dev, pm_message_t state); /*
> Device suspended */
> - int (*resume) (struct ocp_device *dev); /*
> Device woken up */
> - struct device_driver driver;
> -};
> -
> -#define to_ocp_dev(n) container_of(n, struct ocp_device, dev)
> -#define to_ocp_drv(n) container_of(n, struct ocp_driver, driver)
> -
> -/* Similar to the helpers above, these manipulate per-ocp_dev
> - * driver-specific data. Currently stored as ocp_dev::ocpdev,
> - * a void pointer, but it is not present on older kernels.
> - */
> -static inline void *
> -ocp_get_drvdata(struct ocp_device *pdev)
> -{
> - return pdev->drvdata;
> -}
> -
> -static inline void
> -ocp_set_drvdata(struct ocp_device *pdev, void *data)
> -{
> - pdev->drvdata = data;
> -}
> -
> -#if defined (CONFIG_PM)
> -/*
> - * This is right for the IBM 405 and 440 but will need to be
> - * generalized if the OCP stuff gets used on other processors.
> - */
> -static inline void
> -ocp_force_power_off(struct ocp_device *odev)
> -{
> - mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm);
> -}
> -
> -static inline void
> -ocp_force_power_on(struct ocp_device *odev)
> -{
> - mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm);
> -}
> -#else
> -#define ocp_force_power_off(x) (void)(x)
> -#define ocp_force_power_on(x) (void)(x)
> -#endif
> -
> -/* Register/Unregister an OCP driver */
> -extern int ocp_register_driver(struct ocp_driver *drv);
> -extern void ocp_unregister_driver(struct ocp_driver *drv);
> -
> -/* Build list of devices */
> -extern int ocp_early_init(void) __init;
> -
> -/* Find a device by index */
> -extern struct ocp_device *ocp_find_device(unsigned int vendor,
> unsigned int function, int index);
> -
> -/* Get a def by index */
> -extern struct ocp_def *ocp_get_one_device(unsigned int vendor,
> unsigned int function, int index);
> -
> -/* Add a device by index */
> -extern int ocp_add_one_device(struct ocp_def *def);
> -
> -/* Remove a device by index */
> -extern int ocp_remove_one_device(unsigned int vendor, unsigned int
> function, int index);
> -
> -/* Iterate over devices and execute a routine */
> -extern void ocp_for_each_device(void(*callback)(struct ocp_device
> *, void *arg), void *arg);
> -
> -/* Sysfs support */
> -#define OCP_SYSFS_ADDTL(type, format, name, field) \
> -static ssize_t \
> -show_##name##_##field(struct device *dev, struct device_attribute
> *attr, char *buf) \
> -{ \
> - struct ocp_device *odev = to_ocp_dev(dev); \
> - type *add = odev->def->additions; \
> - \
> - return sprintf(buf, format, add->field); \
> -} \
> -static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field,
> NULL);
> -
> -#ifdef CONFIG_IBM_OCP
> -#include <asm/ibm_ocp.h>
> -#endif
> -
> -#endif /* CONFIG_PPC_OCP */
> -#endif /* __OCP_H__ */
> -#endif /* __KERNEL__ */
> --
> 1.2.4
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 12/15] powerpc: move asm/ocp_ids.h
2006-04-05 5:10 ` [PATCH 12/15] powerpc: move asm/ocp_ids.h sfr
@ 2006-04-05 14:07 ` Kumar Gala
0 siblings, 0 replies; 27+ messages in thread
From: Kumar Gala @ 2006-04-05 14:07 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev, paulus
Nack. OCP should not exist in arch/powerpc so leave this header where
it is.
- k
On Apr 5, 2006, at 12:10 AM, sfr@canb.auug.org.au wrote:
> From: Stephen Rothwell <sfr@canb.auug.org.au>
>
> Since the ARCH=powerpc build depends on this file, move it to
> include/asm-powerpc.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
>
> ---
>
> include/asm-powerpc/ocp_ids.h | 75 ++++++++++++++++++++++++++++++
> +++++++++++
> include/asm-ppc/ocp_ids.h | 73
> ----------------------------------------
> 2 files changed, 75 insertions(+), 73 deletions(-)
> create mode 100644 include/asm-powerpc/ocp_ids.h
> delete mode 100644 include/asm-ppc/ocp_ids.h
>
> a374f458829d868a3142bff918ef872e0ecff1a8
> diff --git a/include/asm-powerpc/ocp_ids.h b/include/asm-powerpc/
> ocp_ids.h
> new file mode 100644
> index 0000000..78e5906
> --- /dev/null
> +++ b/include/asm-powerpc/ocp_ids.h
> @@ -0,0 +1,75 @@
> +#ifndef _ASM_POWERPC_OCP_IDS_H
> +#define _ASM_POWERPC_OCP_IDS_H
> +/*
> + * OCP device ids based on the ideas from PCI
> + *
> + * The numbers below are almost completely arbitrary, and in fact
> + * strings might work better. -- paulus
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +/*
> + * Vender device
> + * [xxxx] [xxxx]
> + *
> + * Keep in order, please
> + */
> +
> +/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */
> +
> +#define OCP_VENDOR_INVALID 0x0000
> +#define OCP_VENDOR_ARM 0x0004
> +#define OCP_VENDOR_FREESCALE 0x1057
> +#define OCP_VENDOR_IBM 0x1014
> +#define OCP_VENDOR_MOTOROLA OCP_VENDOR_FREESCALE
> +#define OCP_VENDOR_XILINX 0x10ee
> +#define OCP_VENDOR_UNKNOWN 0xFFFF
> +
> +/* device identification */
> +
> +/* define type */
> +#define OCP_FUNC_INVALID 0x0000
> +
> +/* system 0x0001 - 0x001F */
> +
> +/* Timers 0x0020 - 0x002F */
> +
> +/* Serial 0x0030 - 0x006F*/
> +#define OCP_FUNC_16550 0x0031
> +#define OCP_FUNC_IIC 0x0032
> +#define OCP_FUNC_USB 0x0033
> +#define OCP_FUNC_PSC_UART 0x0034
> +
> +/* Memory devices 0x0090 - 0x009F */
> +#define OCP_FUNC_MAL 0x0090
> +#define OCP_FUNC_DMA 0x0091
> +
> +/* Display 0x00A0 - 0x00AF */
> +
> +/* Sound 0x00B0 - 0x00BF */
> +
> +/* Mass Storage 0x00C0 - 0xxCF */
> +#define OCP_FUNC_IDE 0x00C0
> +
> +/* Misc 0x00D0 - 0x00DF*/
> +#define OCP_FUNC_GPIO 0x00D0
> +#define OCP_FUNC_ZMII 0x00D1
> +#define OCP_FUNC_PERFMON 0x00D2 /* Performance Monitor */
> +#define OCP_FUNC_RGMII 0x00D3
> +#define OCP_FUNC_TAH 0x00D4
> +#define OCP_FUNC_SEC2 0x00D5 /* Crypto/Security 2.0 */
> +
> +/* Network 0x0200 - 0x02FF */
> +#define OCP_FUNC_EMAC 0x0200
> +#define OCP_FUNC_GFAR 0x0201 /* TSEC & FEC */
> +
> +/* Bridge devices 0xE00 - 0xEFF */
> +#define OCP_FUNC_OPB 0x0E00
> +
> +#define OCP_FUNC_UNKNOWN 0xFFFF
> +
> +#endif /* _ASM_POWERPC_OCP_IDS_H */
> diff --git a/include/asm-ppc/ocp_ids.h b/include/asm-ppc/ocp_ids.h
> deleted file mode 100644
> index 8ae4b31..0000000
> --- a/include/asm-ppc/ocp_ids.h
> +++ /dev/null
> @@ -1,73 +0,0 @@
> -/*
> - * ocp_ids.h
> - *
> - * OCP device ids based on the ideas from PCI
> - *
> - * The numbers below are almost completely arbitrary, and in fact
> - * strings might work better. -- paulus
> - *
> - * This program is free software; you can redistribute it and/or
> modify it
> - * under the terms of the GNU General Public License as
> published by the
> - * Free Software Foundation; either version 2 of the License, or
> (at your
> - * option) any later version.
> - */
> -
> -/*
> - * Vender device
> - * [xxxx] [xxxx]
> - *
> - * Keep in order, please
> - */
> -
> -/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */
> -
> -#define OCP_VENDOR_INVALID 0x0000
> -#define OCP_VENDOR_ARM 0x0004
> -#define OCP_VENDOR_FREESCALE 0x1057
> -#define OCP_VENDOR_IBM 0x1014
> -#define OCP_VENDOR_MOTOROLA OCP_VENDOR_FREESCALE
> -#define OCP_VENDOR_XILINX 0x10ee
> -#define OCP_VENDOR_UNKNOWN 0xFFFF
> -
> -/* device identification */
> -
> -/* define type */
> -#define OCP_FUNC_INVALID 0x0000
> -
> -/* system 0x0001 - 0x001F */
> -
> -/* Timers 0x0020 - 0x002F */
> -
> -/* Serial 0x0030 - 0x006F*/
> -#define OCP_FUNC_16550 0x0031
> -#define OCP_FUNC_IIC 0x0032
> -#define OCP_FUNC_USB 0x0033
> -#define OCP_FUNC_PSC_UART 0x0034
> -
> -/* Memory devices 0x0090 - 0x009F */
> -#define OCP_FUNC_MAL 0x0090
> -#define OCP_FUNC_DMA 0x0091
> -
> -/* Display 0x00A0 - 0x00AF */
> -
> -/* Sound 0x00B0 - 0x00BF */
> -
> -/* Mass Storage 0x00C0 - 0xxCF */
> -#define OCP_FUNC_IDE 0x00C0
> -
> -/* Misc 0x00D0 - 0x00DF*/
> -#define OCP_FUNC_GPIO 0x00D0
> -#define OCP_FUNC_ZMII 0x00D1
> -#define OCP_FUNC_PERFMON 0x00D2 /* Performance Monitor */
> -#define OCP_FUNC_RGMII 0x00D3
> -#define OCP_FUNC_TAH 0x00D4
> -#define OCP_FUNC_SEC2 0x00D5 /* Crypto/Security 2.0 */
> -
> -/* Network 0x0200 - 0x02FF */
> -#define OCP_FUNC_EMAC 0x0200
> -#define OCP_FUNC_GFAR 0x0201 /* TSEC & FEC */
> -
> -/* Bridge devices 0xE00 - 0xEFF */
> -#define OCP_FUNC_OPB 0x0E00
> -
> -#define OCP_FUNC_UNKNOWN 0xFFFF
> --
> 1.2.4
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 10/15] powerpc: move asm/mpc83xx.h
2006-04-05 5:10 ` [PATCH 10/15] powerpc: move asm/mpc83xx.h sfr
@ 2006-04-05 14:17 ` Kumar Gala
0 siblings, 0 replies; 27+ messages in thread
From: Kumar Gala @ 2006-04-05 14:17 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev, paulus
Nack. I was avoiding moving this header since it introduces a number
things that should only exist in arch/ppc.
- k
On Apr 5, 2006, at 12:10 AM, sfr@canb.auug.org.au wrote:
> From: Stephen Rothwell <sfr@canb.auug.org.au>
>
> Since the ARCH=powerpc build depends on this file, move it to
> include/asm-powerpc.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
>
> ---
>
> include/asm-powerpc/mpc83xx.h | 115 ++++++++++++++++++++++++++++++
> +++++++++++
> include/asm-ppc/mpc83xx.h | 116
> -----------------------------------------
> 2 files changed, 115 insertions(+), 116 deletions(-)
> create mode 100644 include/asm-powerpc/mpc83xx.h
> delete mode 100644 include/asm-ppc/mpc83xx.h
>
> ce28e1e8654ad07cc23573a31f8cea992d41f9cc
> diff --git a/include/asm-powerpc/mpc83xx.h b/include/asm-powerpc/
> mpc83xx.h
> new file mode 100644
> index 0000000..da4b0fa
> --- /dev/null
> +++ b/include/asm-powerpc/mpc83xx.h
> @@ -0,0 +1,115 @@
> +#ifndef _ASM_POWERPC_MPC83XX_H
> +#define _ASM_POWERPC_MPC83XX_H
> +/*
> + * include/asm-ppc/mpc83xx.h
> + *
> + * MPC83xx definitions
> + *
> + * Maintainer: Kumar Gala <galak@kernel.crashing.org>
> + *
> + * Copyright 2005 Freescale Semiconductor, Inc
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +#ifdef __KERNEL__
> +
> +#include <asm/mmu.h>
> +
> +#ifdef CONFIG_83xx
> +
> +#ifdef CONFIG_MPC834x_SYS
> +#include <platforms/83xx/mpc834x_sys.h>
> +#endif
> +
> +#define _IO_BASE isa_io_base
> +#define _ISA_MEM_BASE isa_mem_base
> +#ifdef CONFIG_PCI
> +#define PCI_DRAM_OFFSET pci_dram_offset
> +#else
> +#define PCI_DRAM_OFFSET 0
> +#endif
> +
> +/*
> + * The "residual" board information structure the boot loader passes
> + * into the kernel.
> + */
> +extern unsigned char __res[];
> +
> +/* Internal IRQs on MPC83xx OpenPIC */
> +/* Not all of these exist on all MPC83xx implementations */
> +
> +#ifndef MPC83xx_IPIC_IRQ_OFFSET
> +#define MPC83xx_IPIC_IRQ_OFFSET 0
> +#endif
> +
> +#define NR_IPIC_INTS 128
> +
> +#define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET)
> +
> +#define MPC83xx_CCSRBAR_SIZE (1024*1024)
> +
> +/* Let modules/drivers get at immrbar (physical) */
> +extern phys_addr_t immrbar;
> +
> +enum ppc_sys_devices {
> + MPC83xx_TSEC1,
> + MPC83xx_TSEC2,
> + MPC83xx_IIC1,
> + MPC83xx_IIC2,
> + MPC83xx_DUART,
> + MPC83xx_SEC2,
> + MPC83xx_USB2_DR,
> + MPC83xx_USB2_MPH,
> + MPC83xx_MDIO,
> + NUM_PPC_SYS_DEVS,
> +};
> +
> +#endif /* CONFIG_83xx */
> +#endif /* __KERNEL__ */
> +#endif /* _ASM_POWERPC_MPC83XX_H */
> diff --git a/include/asm-ppc/mpc83xx.h b/include/asm-ppc/mpc83xx.h
> deleted file mode 100644
> index 3c23fc4..0000000
> --- a/include/asm-ppc/mpc83xx.h
> +++ /dev/null
> @@ -1,116 +0,0 @@
> -/*
> - * include/asm-ppc/mpc83xx.h
> - *
> - * MPC83xx definitions
> - *
> - * Maintainer: Kumar Gala <galak@kernel.crashing.org>
> - *
> - * Copyright 2005 Freescale Semiconductor, Inc
> - *
> - * This program is free software; you can redistribute it and/or
> modify it
> - * under the terms of the GNU General Public License as
> published by the
> - * Free Software Foundation; either version 2 of the License, or
> (at your
> - * option) any later version.
> - */
> -
> -#ifdef __KERNEL__
> -#ifndef __ASM_MPC83xx_H__
> -#define __ASM_MPC83xx_H__
> -
> -#include <linux/config.h>
> -#include <asm/mmu.h>
> -
> -#ifdef CONFIG_83xx
> -
> -#ifdef CONFIG_MPC834x_SYS
> -#include <platforms/83xx/mpc834x_sys.h>
> -#endif
> -
> -#define _IO_BASE isa_io_base
> -#define _ISA_MEM_BASE isa_mem_base
> -#ifdef CONFIG_PCI
> -#define PCI_DRAM_OFFSET pci_dram_offset
> -#else
> -#define PCI_DRAM_OFFSET 0
> -#endif
> -
> -/*
> - * The "residual" board information structure the boot loader passes
> - * into the kernel.
> - */
> -extern unsigned char __res[];
> -
> -/* Internal IRQs on MPC83xx OpenPIC */
> -/* Not all of these exist on all MPC83xx implementations */
> -
> -#ifndef MPC83xx_IPIC_IRQ_OFFSET
> -#define MPC83xx_IPIC_IRQ_OFFSET 0
> -#endif
> -
> -#define NR_IPIC_INTS 128
> -
> -#define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET)
> -
> -#define MPC83xx_CCSRBAR_SIZE (1024*1024)
> -
> -/* Let modules/drivers get at immrbar (physical) */
> -extern phys_addr_t immrbar;
> -
> -enum ppc_sys_devices {
> - MPC83xx_TSEC1,
> - MPC83xx_TSEC2,
> - MPC83xx_IIC1,
> - MPC83xx_IIC2,
> - MPC83xx_DUART,
> - MPC83xx_SEC2,
> - MPC83xx_USB2_DR,
> - MPC83xx_USB2_MPH,
> - MPC83xx_MDIO,
> - NUM_PPC_SYS_DEVS,
> -};
> -
> -#endif /* CONFIG_83xx */
> -#endif /* __ASM_MPC83xx_H__ */
> -#endif /* __KERNEL__ */
> --
> 1.2.4
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 14/15] powerpc: move asm/mpc85xx.h
2006-04-05 5:10 ` [PATCH 14/15] powerpc: move asm/mpc85xx.h sfr
@ 2006-04-05 14:17 ` Kumar Gala
0 siblings, 0 replies; 27+ messages in thread
From: Kumar Gala @ 2006-04-05 14:17 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev, paulus
Nack. I was avoiding moving this header since it introduces a number
things that should only exist in arch/ppc.
- k
On Apr 5, 2006, at 12:10 AM, sfr@canb.auug.org.au wrote:
> From: Stephen Rothwell <sfr@canb.auug.org.au>
>
> Since the ARCH=powerpc build depends on this file, move it to
> include/asm-powerpc.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
>
> ---
>
> include/asm-powerpc/mpc85xx.h | 195 ++++++++++++++++++++++++++++++
> ++++++++++
> include/asm-ppc/mpc85xx.h | 198
> -----------------------------------------
> 2 files changed, 195 insertions(+), 198 deletions(-)
> create mode 100644 include/asm-powerpc/mpc85xx.h
> delete mode 100644 include/asm-ppc/mpc85xx.h
>
> 4fc7b6e78d24e11e704ef7b5a1ceb659d3a03cc2
> diff --git a/include/asm-powerpc/mpc85xx.h b/include/asm-powerpc/
> mpc85xx.h
> new file mode 100644
> index 0000000..4113165
> --- /dev/null
> +++ b/include/asm-powerpc/mpc85xx.h
> @@ -0,0 +1,195 @@
> +#ifndef _ASM_POWERPC_MPC85XX_H
> +#define _ASM_POWERPC_MPC85XX_H
> +/*
> + * MPC85xx definitions
> + *
> + * Maintainer: Kumar Gala <galak@kernel.crashing.org>
> + *
> + * Copyright 2004 Freescale Semiconductor, Inc
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +#ifdef __KERNEL__
> +
> +#include <asm/mmu.h>
> +
> +#ifdef CONFIG_85xx
> +
> +#ifdef CONFIG_MPC8540_ADS
> +#include <platforms/85xx/mpc8540_ads.h>
> +#endif
> +#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
> +#include <platforms/85xx/mpc8555_cds.h>
> +#endif
> +#ifdef CONFIG_MPC8560_ADS
> +#include <platforms/85xx/mpc8560_ads.h>
> +#endif
> +#ifdef CONFIG_SBC8560
> +#include <platforms/85xx/sbc8560.h>
> +#endif
> +#ifdef CONFIG_STX_GP3
> +#include <platforms/85xx/stx_gp3.h>
> +#endif
> +#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || \
> + defined(CONFIG_TQM8555) || defined(CONFIG_TQM8560)
> +#include <platforms/85xx/tqm85xx.h>
> +#endif
> +
> +#define _IO_BASE isa_io_base
> +#define _ISA_MEM_BASE isa_mem_base
> +#ifdef CONFIG_PCI
> +#define PCI_DRAM_OFFSET pci_dram_offset
> +#else
> +#define PCI_DRAM_OFFSET 0
> +#endif
> +
> +/*
> + * The "residual" board information structure the boot loader passes
> + * into the kernel.
> + */
> +extern unsigned char __res[];
> +
> +/* Offset from CCSRBAR */
> +#define MPC85xx_CPM_OFFSET (0x80000)
> +#define MPC85xx_CPM_SIZE (0x40000)
> +#define MPC85xx_DMA_OFFSET (0x21000)
> +#define MPC85xx_DMA_SIZE (0x01000)
> +#define MPC85xx_DMA0_OFFSET (0x21100)
> +#define MPC85xx_DMA0_SIZE (0x00080)
> +#define MPC85xx_DMA1_OFFSET (0x21180)
> +#define MPC85xx_DMA1_SIZE (0x00080)
> +#define MPC85xx_DMA2_OFFSET (0x21200)
> +#define MPC85xx_DMA2_SIZE (0x00080)
> +#define MPC85xx_DMA3_OFFSET (0x21280)
> +#define MPC85xx_DMA3_SIZE (0x00080)
> +#define MPC85xx_ENET1_OFFSET (0x24000)
> +#define MPC85xx_ENET1_SIZE (0x01000)
> +#define MPC85xx_MIIM_OFFSET (0x24520)
> +#define MPC85xx_MIIM_SIZE (0x00018)
> +#define MPC85xx_ENET2_OFFSET (0x25000)
> +#define MPC85xx_ENET2_SIZE (0x01000)
> +#define MPC85xx_ENET3_OFFSET (0x26000)
> +#define MPC85xx_ENET3_SIZE (0x01000)
> +#define MPC85xx_GUTS_OFFSET (0xe0000)
> +#define MPC85xx_GUTS_SIZE (0x01000)
> +#define MPC85xx_IIC1_OFFSET (0x03000)
> +#define MPC85xx_IIC1_SIZE (0x00100)
> +#define MPC85xx_OPENPIC_OFFSET (0x40000)
> +#define MPC85xx_OPENPIC_SIZE (0x40000)
> +#define MPC85xx_PCI1_OFFSET (0x08000)
> +#define MPC85xx_PCI1_SIZE (0x01000)
> +#define MPC85xx_PCI2_OFFSET (0x09000)
> +#define MPC85xx_PCI2_SIZE (0x01000)
> +#define MPC85xx_PERFMON_OFFSET (0xe1000)
> +#define MPC85xx_PERFMON_SIZE (0x01000)
> +#define MPC85xx_SEC2_OFFSET (0x30000)
> +#define MPC85xx_SEC2_SIZE (0x10000)
> +#define MPC85xx_UART0_OFFSET (0x04500)
> +#define MPC85xx_UART0_SIZE (0x00100)
> +#define MPC85xx_UART1_OFFSET (0x04600)
> +#define MPC85xx_UART1_SIZE (0x00100)
> +
> +#define MPC85xx_CCSRBAR_SIZE (1024*1024)
> +
> +/* Let modules/drivers get at CCSRBAR */
> +extern phys_addr_t get_ccsrbar(void);
> +
> +#ifdef MODULE
> +#define CCSRBAR get_ccsrbar()
> +#else
> +#define CCSRBAR BOARD_CCSRBAR
> +#endif
> +
> +enum ppc_sys_devices {
> + MPC85xx_TSEC1,
> + MPC85xx_TSEC2,
> + MPC85xx_FEC,
> + MPC85xx_IIC1,
> + MPC85xx_DMA0,
> + MPC85xx_DMA1,
> + MPC85xx_DMA2,
> + MPC85xx_DMA3,
> + MPC85xx_DUART,
> + MPC85xx_PERFMON,
> + MPC85xx_SEC2,
> + MPC85xx_CPM_SPI,
> + MPC85xx_CPM_I2C,
> + MPC85xx_CPM_USB,
> + MPC85xx_CPM_SCC1,
> + MPC85xx_CPM_SCC2,
> + MPC85xx_CPM_SCC3,
> + MPC85xx_CPM_SCC4,
> + MPC85xx_CPM_FCC1,
> + MPC85xx_CPM_FCC2,
> + MPC85xx_CPM_FCC3,
> + MPC85xx_CPM_MCC1,
> + MPC85xx_CPM_MCC2,
> + MPC85xx_CPM_SMC1,
> + MPC85xx_CPM_SMC2,
> + MPC85xx_eTSEC1,
> + MPC85xx_eTSEC2,
> + MPC85xx_eTSEC3,
> + MPC85xx_eTSEC4,
> + MPC85xx_IIC2,
> + MPC85xx_MDIO,
> + NUM_PPC_SYS_DEVS,
> +};
> +
> +/* Internal interrupts are all Level Sensitive, and Positive
> Polarity */
> +#define MPC85XX_INTERNAL_IRQ_SENSES \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */
> +
> +#endif /* CONFIG_85xx */
> +#endif /* __KERNEL__ */
> +#endif /* _ASM_POWERPC_MPC85XX_H */
> diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
> deleted file mode 100644
> index f47002a..0000000
> --- a/include/asm-ppc/mpc85xx.h
> +++ /dev/null
> @@ -1,198 +0,0 @@
> -/*
> - * include/asm-ppc/mpc85xx.h
> - *
> - * MPC85xx definitions
> - *
> - * Maintainer: Kumar Gala <galak@kernel.crashing.org>
> - *
> - * Copyright 2004 Freescale Semiconductor, Inc
> - *
> - * This program is free software; you can redistribute it and/or
> modify it
> - * under the terms of the GNU General Public License as
> published by the
> - * Free Software Foundation; either version 2 of the License, or
> (at your
> - * option) any later version.
> - */
> -
> -#ifdef __KERNEL__
> -#ifndef __ASM_MPC85xx_H__
> -#define __ASM_MPC85xx_H__
> -
> -#include <linux/config.h>
> -#include <asm/mmu.h>
> -
> -#ifdef CONFIG_85xx
> -
> -#ifdef CONFIG_MPC8540_ADS
> -#include <platforms/85xx/mpc8540_ads.h>
> -#endif
> -#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
> -#include <platforms/85xx/mpc8555_cds.h>
> -#endif
> -#ifdef CONFIG_MPC8560_ADS
> -#include <platforms/85xx/mpc8560_ads.h>
> -#endif
> -#ifdef CONFIG_SBC8560
> -#include <platforms/85xx/sbc8560.h>
> -#endif
> -#ifdef CONFIG_STX_GP3
> -#include <platforms/85xx/stx_gp3.h>
> -#endif
> -#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || \
> - defined(CONFIG_TQM8555) || defined(CONFIG_TQM8560)
> -#include <platforms/85xx/tqm85xx.h>
> -#endif
> -
> -#define _IO_BASE isa_io_base
> -#define _ISA_MEM_BASE isa_mem_base
> -#ifdef CONFIG_PCI
> -#define PCI_DRAM_OFFSET pci_dram_offset
> -#else
> -#define PCI_DRAM_OFFSET 0
> -#endif
> -
> -/*
> - * The "residual" board information structure the boot loader passes
> - * into the kernel.
> - */
> -extern unsigned char __res[];
> -
> -/* Offset from CCSRBAR */
> -#define MPC85xx_CPM_OFFSET (0x80000)
> -#define MPC85xx_CPM_SIZE (0x40000)
> -#define MPC85xx_DMA_OFFSET (0x21000)
> -#define MPC85xx_DMA_SIZE (0x01000)
> -#define MPC85xx_DMA0_OFFSET (0x21100)
> -#define MPC85xx_DMA0_SIZE (0x00080)
> -#define MPC85xx_DMA1_OFFSET (0x21180)
> -#define MPC85xx_DMA1_SIZE (0x00080)
> -#define MPC85xx_DMA2_OFFSET (0x21200)
> -#define MPC85xx_DMA2_SIZE (0x00080)
> -#define MPC85xx_DMA3_OFFSET (0x21280)
> -#define MPC85xx_DMA3_SIZE (0x00080)
> -#define MPC85xx_ENET1_OFFSET (0x24000)
> -#define MPC85xx_ENET1_SIZE (0x01000)
> -#define MPC85xx_MIIM_OFFSET (0x24520)
> -#define MPC85xx_MIIM_SIZE (0x00018)
> -#define MPC85xx_ENET2_OFFSET (0x25000)
> -#define MPC85xx_ENET2_SIZE (0x01000)
> -#define MPC85xx_ENET3_OFFSET (0x26000)
> -#define MPC85xx_ENET3_SIZE (0x01000)
> -#define MPC85xx_GUTS_OFFSET (0xe0000)
> -#define MPC85xx_GUTS_SIZE (0x01000)
> -#define MPC85xx_IIC1_OFFSET (0x03000)
> -#define MPC85xx_IIC1_SIZE (0x00100)
> -#define MPC85xx_OPENPIC_OFFSET (0x40000)
> -#define MPC85xx_OPENPIC_SIZE (0x40000)
> -#define MPC85xx_PCI1_OFFSET (0x08000)
> -#define MPC85xx_PCI1_SIZE (0x01000)
> -#define MPC85xx_PCI2_OFFSET (0x09000)
> -#define MPC85xx_PCI2_SIZE (0x01000)
> -#define MPC85xx_PERFMON_OFFSET (0xe1000)
> -#define MPC85xx_PERFMON_SIZE (0x01000)
> -#define MPC85xx_SEC2_OFFSET (0x30000)
> -#define MPC85xx_SEC2_SIZE (0x10000)
> -#define MPC85xx_UART0_OFFSET (0x04500)
> -#define MPC85xx_UART0_SIZE (0x00100)
> -#define MPC85xx_UART1_OFFSET (0x04600)
> -#define MPC85xx_UART1_SIZE (0x00100)
> -
> -#define MPC85xx_CCSRBAR_SIZE (1024*1024)
> -
> -/* Let modules/drivers get at CCSRBAR */
> -extern phys_addr_t get_ccsrbar(void);
> -
> -#ifdef MODULE
> -#define CCSRBAR get_ccsrbar()
> -#else
> -#define CCSRBAR BOARD_CCSRBAR
> -#endif
> -
> -enum ppc_sys_devices {
> - MPC85xx_TSEC1,
> - MPC85xx_TSEC2,
> - MPC85xx_FEC,
> - MPC85xx_IIC1,
> - MPC85xx_DMA0,
> - MPC85xx_DMA1,
> - MPC85xx_DMA2,
> - MPC85xx_DMA3,
> - MPC85xx_DUART,
> - MPC85xx_PERFMON,
> - MPC85xx_SEC2,
> - MPC85xx_CPM_SPI,
> - MPC85xx_CPM_I2C,
> - MPC85xx_CPM_USB,
> - MPC85xx_CPM_SCC1,
> - MPC85xx_CPM_SCC2,
> - MPC85xx_CPM_SCC3,
> - MPC85xx_CPM_SCC4,
> - MPC85xx_CPM_FCC1,
> - MPC85xx_CPM_FCC2,
> - MPC85xx_CPM_FCC3,
> - MPC85xx_CPM_MCC1,
> - MPC85xx_CPM_MCC2,
> - MPC85xx_CPM_SMC1,
> - MPC85xx_CPM_SMC2,
> - MPC85xx_eTSEC1,
> - MPC85xx_eTSEC2,
> - MPC85xx_eTSEC3,
> - MPC85xx_eTSEC4,
> - MPC85xx_IIC2,
> - MPC85xx_MDIO,
> - NUM_PPC_SYS_DEVS,
> -};
> -
> -/* Internal interrupts are all Level Sensitive, and Positive
> Polarity */
> -#define MPC85XX_INTERNAL_IRQ_SENSES \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */
> -
> -#endif /* CONFIG_85xx */
> -#endif /* __ASM_MPC85xx_H__ */
> -#endif /* __KERNEL__ */
> --
> 1.2.4
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 00/15] powerpc: move some header files
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
` (14 preceding siblings ...)
2006-04-05 5:10 ` [PATCH 15/15] powerpc: remove include hack sfr
@ 2006-04-05 14:28 ` Kumar Gala
2006-04-05 16:03 ` Stephen Rothwell
15 siblings, 1 reply; 27+ messages in thread
From: Kumar Gala @ 2006-04-05 14:28 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev, paulus
On Apr 5, 2006, at 12:10 AM, sfr@canb.auug.org.au wrote:
> This patch set moves sufficient include files from include/asm-ppc
> to include/asm-powerpc to allow us to remove the include hack in the
> arch/powerpc/Makefile.
>
> b/arch/powerpc/Makefile | 21 ++------------
> b/include/asm-powerpc/amigappc.h | 9 ++----
> b/include/asm-powerpc/bootinfo.h | 8 ++---
> b/include/asm-powerpc/highmem.h | 11 +++----
> b/include/asm-powerpc/hydra.h | 8 ++---
> b/include/asm-powerpc/mpc83xx.h | 7 ++--
> b/include/asm-powerpc/mpc85xx.h | 9 ++----
> b/include/asm-powerpc/mpc8xx.h | 10 +++---
> b/include/asm-powerpc/ocp.h | 7 ++--
> b/include/asm-powerpc/ocp_ids.h | 6 ++--
> b/include/asm-powerpc/open_pic.h | 10 +++---
> b/include/asm-powerpc/pnp.h | 8 ++---
> b/include/asm-powerpc/reg_booke.h | 55 ++++++++++++++++++
> +-------------------
> b/include/asm-powerpc/residual.h | 6 ++--
> b/include/asm-powerpc/suspend.h | 17 +++++++++++
> include/asm-ppc/suspend.h | 12 --------
> 16 files changed, 95 insertions(+), 109 deletions(-)
How about we do the following to remove the include hack:
don't move the following (determine what needs them to build and
fixup, I dont believe any of these need to exist at this point in
arch/powerpc for it to build any supported arch/powerpc platform:
b/include/asm-powerpc/amigappc.h | 9 ++----
b/include/asm-powerpc/bootinfo.h | 8 ++---
b/include/asm-powerpc/mpc8xx.h | 10 +++---
b/include/asm-powerpc/ocp.h | 7 ++--
b/include/asm-powerpc/ocp_ids.h | 6 ++--
b/include/asm-powerpc/open_pic.h | 10 +++---
Duplicate these headers (then I'll go through and clean them up,
removing arch/ppc'ism):
b/include/asm-powerpc/mpc83xx.h | 7 ++--
b/include/asm-powerpc/mpc85xx.h | 9 ++----
- kumar
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 00/15] powerpc: move some header files
2006-04-05 14:28 ` [PATCH 00/15] powerpc: move some header files Kumar Gala
@ 2006-04-05 16:03 ` Stephen Rothwell
2006-04-05 16:15 ` Kumar Gala
0 siblings, 1 reply; 27+ messages in thread
From: Stephen Rothwell @ 2006-04-05 16:03 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, paulus
[-- Attachment #1: Type: text/plain, Size: 1456 bytes --]
On Wed, 5 Apr 2006 09:28:55 -0500 Kumar Gala <galak@kernel.crashing.org> wrote:
>
> How about we do the following to remove the include hack:
>
> don't move the following (determine what needs them to build and
> fixup, I dont believe any of these need to exist at this point in
> arch/powerpc for it to build any supported arch/powerpc platform:
I only moved the files that were actually required to build the defconfigs
for the three 32 bit builds in arch/powerpc ...
> b/include/asm-powerpc/amigappc.h | 9 ++----
> b/include/asm-powerpc/bootinfo.h | 8 ++---
> b/include/asm-powerpc/mpc8xx.h | 10 +++---
> b/include/asm-powerpc/ocp.h | 7 ++--
> b/include/asm-powerpc/ocp_ids.h | 6 ++--
> b/include/asm-powerpc/open_pic.h | 10 +++---
So maybe I could attempt to remove the dependencies instead of moving the
files. You are right that it is worth it if we can just get rid of these
files.
> Duplicate these headers (then I'll go through and clean them up,
> removing arch/ppc'ism):
>
> b/include/asm-powerpc/mpc83xx.h | 7 ++--
> b/include/asm-powerpc/mpc85xx.h | 9 ++----
I guess that would work, but Paulus is going to not like me as he already
put all these patches into the powerpc tree. :-)
Something to keep me entertained for another day.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 191 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 00/15] powerpc: move some header files
2006-04-05 16:03 ` Stephen Rothwell
@ 2006-04-05 16:15 ` Kumar Gala
2006-04-05 17:07 ` Stephen Rothwell
2006-04-05 22:28 ` Paul Mackerras
0 siblings, 2 replies; 27+ messages in thread
From: Kumar Gala @ 2006-04-05 16:15 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linuxppc-dev, paulus
On Apr 5, 2006, at 11:03 AM, Stephen Rothwell wrote:
> On Wed, 5 Apr 2006 09:28:55 -0500 Kumar Gala
> <galak@kernel.crashing.org> wrote:
>>
>> How about we do the following to remove the include hack:
>>
>> don't move the following (determine what needs them to build and
>> fixup, I dont believe any of these need to exist at this point in
>> arch/powerpc for it to build any supported arch/powerpc platform:
>
> I only moved the files that were actually required to build the
> defconfigs
> for the three 32 bit builds in arch/powerpc ...
>
>> b/include/asm-powerpc/amigappc.h | 9 ++----
>> b/include/asm-powerpc/bootinfo.h | 8 ++---
>> b/include/asm-powerpc/mpc8xx.h | 10 +++---
>> b/include/asm-powerpc/ocp.h | 7 ++--
>> b/include/asm-powerpc/ocp_ids.h | 6 ++--
>> b/include/asm-powerpc/open_pic.h | 10 +++---
>
> So maybe I could attempt to remove the dependencies instead of
> moving the
> files. You are right that it is worth it if we can just get rid of
> these
> files.
>
>> Duplicate these headers (then I'll go through and clean them up,
>> removing arch/ppc'ism):
>>
>> b/include/asm-powerpc/mpc83xx.h | 7 ++--
>> b/include/asm-powerpc/mpc85xx.h | 9 ++----
>
> I guess that would work, but Paulus is going to not like me as he
> already
> put all these patches into the powerpc tree. :-)
That's Paulus own doing for his premature pull :)
> Something to keep me entertained for another day.
I'm guessing you had to pull some of them in because of the following:
io.h:#include <asm-ppc/io.h>
mmu_context.h:#include <asm-ppc/mmu_context.h>
mmu.h:#include <asm-ppc/mmu.h>
pci-bridge.h:#include <asm-ppc/pci-bridge.h>
pgalloc.h:#include <asm-ppc/pgalloc.h>
pgtable.h:#include <asm-ppc/pgtable.h>
I think addressing these will make life easier with the other includes.
- kumar
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 00/15] powerpc: move some header files
2006-04-05 16:15 ` Kumar Gala
@ 2006-04-05 17:07 ` Stephen Rothwell
2006-04-05 22:28 ` Paul Mackerras
1 sibling, 0 replies; 27+ messages in thread
From: Stephen Rothwell @ 2006-04-05 17:07 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, paulus
[-- Attachment #1: Type: text/plain, Size: 824 bytes --]
On Wed, 5 Apr 2006 11:15:04 -0500 Kumar Gala <galak@kernel.crashing.org> wrote:
>
> I'm guessing you had to pull some of them in because of the following:
>
> io.h:#include <asm-ppc/io.h>
> mmu_context.h:#include <asm-ppc/mmu_context.h>
> mmu.h:#include <asm-ppc/mmu.h>
> pci-bridge.h:#include <asm-ppc/pci-bridge.h>
> pgalloc.h:#include <asm-ppc/pgalloc.h>
> pgtable.h:#include <asm-ppc/pgtable.h>
>
> I think addressing these will make life easier with the other includes.
I'll have a look at these in the morning, thanks for the hint.
I am thinking of creating an include/asm-powerpc/<xx>_32.h for each of the asm-ppc
files above and then only putting into them what we need for arch/powerpc.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 191 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 00/15] powerpc: move some header files
2006-04-05 16:15 ` Kumar Gala
2006-04-05 17:07 ` Stephen Rothwell
@ 2006-04-05 22:28 ` Paul Mackerras
1 sibling, 0 replies; 27+ messages in thread
From: Paul Mackerras @ 2006-04-05 22:28 UTC (permalink / raw)
To: Kumar Gala; +Cc: Stephen Rothwell, linuxppc-dev
Kumar Gala writes:
> > I guess that would work, but Paulus is going to not like me as he
> > already
> > put all these patches into the powerpc tree. :-)
>
> That's Paulus own doing for his premature pull :)
For now I have reverted the powerpc.git tree to remove those commits
of Stephen's, so all it has now (compared to v2.6.17-rc1) are a CHRP
booting fix and the "iSeries has only 256 IRQs" patch.
Everyone, if you have done a pull from powerpc.git in the last 24
hours, please do this on your repository:
git reset b86756ae76dc5e7ecff3ca52a5842155e6d457de
That will get us back into sync. Sorry about the to-ing and fro-ing
on this.
Paul.
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2006-04-05 22:28 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2006-04-05 5:10 [PATCH 00/15] powerpc: move some header files sfr
2006-04-05 5:10 ` [PATCH 01/15] powerpc: move asm/hignmem.h sfr
2006-04-05 5:10 ` [PATCH 02/15] powerpc: move asm/suspend.h sfr
2006-04-05 5:10 ` [PATCH 03/15] powerpc: move asm/mpc8xx.h sfr
2006-04-05 5:10 ` [PATCH 04/15] powerpc: move asm/bootinfo.h sfr
2006-04-05 14:05 ` Kumar Gala
2006-04-05 5:10 ` [PATCH 05/15] powerpc: move asm/residual.h sfr
2006-04-05 5:10 ` [PATCH 06/15] powerpc: moce asm/pnp.h sfr
2006-04-05 5:10 ` [PATCH 07/15] powerpc: move asm/amigappc.h sfr
2006-04-05 5:10 ` [PATCH 08/15] powerpc: move asm/open_pic.h sfr
2006-04-05 14:07 ` Kumar Gala
2006-04-05 5:10 ` [PATCH 09/15] powerpc: move asm/hydra.h sfr
2006-04-05 5:10 ` [PATCH 10/15] powerpc: move asm/mpc83xx.h sfr
2006-04-05 14:17 ` Kumar Gala
2006-04-05 5:10 ` [PATCH 11/15] powerpc: move asm/ocp.h sfr
2006-04-05 14:07 ` Kumar Gala
2006-04-05 5:10 ` [PATCH 12/15] powerpc: move asm/ocp_ids.h sfr
2006-04-05 14:07 ` Kumar Gala
2006-04-05 5:10 ` [PATCH 13/15] powerpc: move asm/reg_booke.h sfr
2006-04-05 5:10 ` [PATCH 14/15] powerpc: move asm/mpc85xx.h sfr
2006-04-05 14:17 ` Kumar Gala
2006-04-05 5:10 ` [PATCH 15/15] powerpc: remove include hack sfr
2006-04-05 14:28 ` [PATCH 00/15] powerpc: move some header files Kumar Gala
2006-04-05 16:03 ` Stephen Rothwell
2006-04-05 16:15 ` Kumar Gala
2006-04-05 17:07 ` Stephen Rothwell
2006-04-05 22:28 ` Paul Mackerras
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