From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id 3F0D9679E9 for ; Fri, 21 Apr 2006 08:41:18 +1000 (EST) Subject: Re: Not coherent cache DMA for G3/G4 CPUs: clarification needed From: Benjamin Herrenschmidt To: Eugene Surovegin In-Reply-To: <20060420213316.GD25755@gate.ebshome.net> References: <28892.1145559466@www088.gmx.net> <20060420203848.GA23192@gate.ebshome.net> <1145567174.4517.1.camel@localhost.localdomain> <20060420213316.GD25755@gate.ebshome.net> Content-Type: text/plain Date: Fri, 21 Apr 2006 08:41:09 +1000 Message-Id: <1145572869.4517.12.camel@localhost.localdomain> Mime-Version: 1.0 Cc: debian-powerpc@lists.debian.org, linuxppc-dev@ozlabs.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Thu, 2006-04-20 at 14:33 -0700, Eugene Surovegin wrote: > On Fri, Apr 21, 2006 at 07:06:13AM +1000, Benjamin Herrenschmidt wrote: > > (On 6xx this is deadly even if you don't access those cacheable pages > > because the CPU prefetch may do it for you). > > Here is another thought if this "prefetch" theory is correct. > > You guys seems to focus on > dma_alloc_coherent()/pci_alloc_consistent(), but forgeting about so > called "streaming" mappings. > > You cannot just flush/invalidate cache any more, because "CPU can > prefetch this data back". So, to be completely correct (if you insist > on "6xx can prefetch"-theory), you have to actually _copy_ data to > your consistent memory on dma_map_single(). You can imagine > performance implications. I suspect even 440 will be faster in this > case than G4 :). Yes. Ben.