RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Zang Roy-r61911]

On May 17, 2006, at 5:13 AM, Zang Roy-r61911 wrote:

> Add support for Freescale mpcc7448 (Taiga) board support
>
> Signed-off-by: Roy Zang  <tie-fei.zang@freescale.com>
>
> ---
>
>  arch/powerpc/Kconfig                       |   24 +++
>  arch/powerpc/kernel/legacy_serial.c        |   39 ++++

These board port should live in platforms/embedded6xx.

Kumar, what does you mean? 
All my board support code should be live in platforms/embedded6xx? 
How about the legacy serial support?

>  arch/powerpc/platforms/74xx/Makefile       |    4
>  arch/powerpc/platforms/74xx/misc.c         |   38 ++++
>  arch/powerpc/platforms/74xx/mpc7448_hpc2.c |  257 +++++++++++++++++ 
> +++++++++++
>  arch/powerpc/platforms/74xx/mpc7448_hpc2.h |   80 +++++++++
>  arch/powerpc/platforms/74xx/pci.c          |  103 +++++++++++
>  arch/powerpc/platforms/Makefile            |    1
>  8 files changed, 545 insertions(+), 1 deletions(-)
>  create mode 100644 arch/powerpc/platforms/74xx/Makefile
>  create mode 100644 arch/powerpc/platforms/74xx/misc.c
>  create mode 100644 arch/powerpc/platforms/74xx/mpc7448_hpc2.c
>  create mode 100644 arch/powerpc/platforms/74xx/mpc7448_hpc2.h
>  create mode 100644 arch/powerpc/platforms/74xx/pci.c
>
> 13c16416da4fa51ec771bd4863d94344d139b2f5
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 6729c98..abeac1f 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -332,6 +332,27 @@ config APUS
>  	  Select APUS if configuring for a PowerUP Amiga.
>  	  More information is available at:
>  	  <http://linux-apus.sourceforge.net/>.
> +
> +config MPC7448HPC2
> +	bool "Freescale MPC7448HPC2(Taiga)"
> +	select DEFAULT_UIMAGE
> +	select PPC_UDBG_16550
> +	help
> +	  Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2  
> (Taiga)
> +	  platform
> +
> +config 74xx
> +	bool
> +	depends on MPC7448HPC2
> +	default y
> +	help
> +	  Select 74xx support
> +

What is the config option used for?  We should get ride of.

> +config TSI108_BRIDGE
> +	bool
> +	depends on MPC7448HPC2
> +	default y
> +	
>  endchoice
>
>  config PPC_PSERIES
> @@ -798,7 +819,8 @@ config MCA
>  	bool
>
>  config PCI
> -	bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx ||  
> PPC_MPC52xx || (EMBEDDED && PPC_ISERIES)
> +	bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx ||  
> PPC_MPC52xx || (EMBEDDED && PPC_ISERIES) \
> +				  || MPC7448HPC2
>  	default y if !40x && !CPM2 && !8xx && !APUS && !PPC_83xx && ! 
> PPC_85xx
>  	default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS
>  	default PCI_QSPAN if !4xx && !CPM2 && 8xx
> diff --git a/arch/powerpc/kernel/legacy_serial.c b/arch/powerpc/ 
> kernel/legacy_serial.c
> index 6e67b5b..f99238d 100644
> --- a/arch/powerpc/kernel/legacy_serial.c
> +++ b/arch/powerpc/kernel/legacy_serial.c
> @@ -134,6 +134,34 @@ static int __init add_legacy_soc_port(st
>  	return add_legacy_port(np, -1, UPIO_MEM, addr, addr, NO_IRQ, flags);
>  }
>
> +static int __init add_legacy_tsi_port(struct device_node *np,
> +				      struct device_node *tsi_dev)
> +{
> +	phys_addr_t addr;
> +	u32 *addrp;
> +	upf_t flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
> +
> +	/* We only support ports that have a clock frequency properly
> +	 * encoded in the device-tree.
> +	 */
> +	if (get_property(np, "clock-frequency", NULL) == NULL)
> +		return -1;
> +
> +	/* Get the address */
> +	addrp = of_get_address(tsi_dev, 0, NULL, NULL);
> +	if (addrp == NULL)
> +		return -1;
> +
> +	addr = of_translate_address(tsi_dev, addrp);
> +
> +	/* Add port, irq will be dealt with later. We passed a translated
> +	 * IO port value. It will be fixed up later along with the irq
> +	 */
> +	return add_legacy_port(np, -1, UPIO_MEM, addr, addr, NO_IRQ, flags);
> +}
> +

This looks like its duplicating add_legacy_soc_port, why not use that  
instead?

> +
> +
>  static int __init add_legacy_isa_port(struct device_node *np,
>  				      struct device_node *isa_brg)
>  {
> @@ -302,6 +330,17 @@ void __init find_legacy_serial_ports(voi
>  		of_node_put(isa);
>  	}
>
> +	/* First fill our array with tsi-bridge ports */
> +	for (np = NULL; (np = of_find_compatible_node(np, "serial",  
> "ns16550")) != NULL;) {
> +		struct device_node *tsi = of_get_parent(np);
> +		if (tsi && !strcmp(tsi->type, "tsi-bridge")) {
> +			index = add_legacy_tsi_port(np, np);
> +			if (index >= 0 && np == stdout)
> +				legacy_serial_console = index;
> +		}
> +		of_node_put(tsi);
> +	}
> +	
>  #ifdef CONFIG_PCI
>  	/* Next, try to locate PCI ports */
>  	for (np = NULL; (np = of_find_all_nodes(np));) {
> diff --git a/arch/powerpc/platforms/74xx/Makefile b/arch/powerpc/ 
> platforms/74xx/Makefile
> new file mode 100644
> index 0000000..ed5648c
> --- /dev/null
> +++ b/arch/powerpc/platforms/74xx/Makefile
> @@ -0,0 +1,4 @@
> +#
> +# Makefile for the PowerPC 74xx linux kernel.
> +#
> +obj-$(CONFIG_MPC7448HPC2)	+= mpc7448_hpc2.o pci.o misc.o
> diff --git a/arch/powerpc/platforms/74xx/misc.c b/arch/powerpc/ 
> platforms/74xx/misc.c
> new file mode 100644
> index 0000000..6228875
> --- /dev/null
> +++ b/arch/powerpc/platforms/74xx/misc.c
> @@ -0,0 +1,38 @@
> +
> +/*
> + * MPC74xx generic code.
> + *
> + * Maintained by Roy Zang
> + *
> + * Copyright 2006 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute  it and/or  
> modify it
> + * under  the terms of  the GNU General  Public License as  
> published by the
> + * Free Software Foundation;  either version 2 of the  License, or  
> (at your
> + * option) any later version.
> + */
> +#include <linux/irq.h>
> +#include <linux/module.h>
> +#include <asm/irq.h>
> +extern void _nmask_and_or_msr(unsigned long nmask, unsigned long  
> or_val);
> +
> +void mpc7448_hpc2_restart(char *cmd)
> +{
> +	local_irq_disable();
> +
> +	/* Set exception prefix high - to the firmware */
> +	_nmask_and_or_msr(0, MSR_IP);
> +
> +	for (;;) ;		/* Spin until reset happens */
> +}
> +
> +void mpc7448_hpc2_power_off(void)
> +{
> +	local_irq_disable();
> +	for (;;) ;		/* No way to shut power off with software */
> +}
> +
> +void mpc7448_hpc2_halt(void)
> +{
> +	mpc7448_hpc2_power_off();
> +}

Move these back into mpc7448_hpc2.c.  They are to specific to hpc2.

> diff --git a/arch/powerpc/platforms/74xx/mpc7448_hpc2.c b/arch/ 
> powerpc/platforms/74xx/mpc7448_hpc2.c
> new file mode 100644
> index 0000000..b060ae1
> --- /dev/null
> +++ b/arch/powerpc/platforms/74xx/mpc7448_hpc2.c
> @@ -0,0 +1,257 @@
> +/*
> + * mpc7448_hpc2.c
> + *
> + * Board setup routines for the Freescale Taiga platform
> + *
> + * Author: Jacob Pan
> + *	 jacob.pan@freescale.com
> + * Author: Xianghua Xiao
> + *       updated for taiga board from emulation platform 2005.5
> + *       x.xiao@freescale.com
> + * Maintainer: Roy Zang <tie-fei.zang@freescale.com>
> + *
> + * Copyright 2004-2006 Freescale Semiconductor, Inc.
> + *
> + * This file is licensed under
> + * the terms of the GNU General Public License version 2.  This  
> program
> + * is licensed "as is" without any warranty of any kind, whether  
> express
> + * or implied.
> + */
> +
> +#include <linux/config.h>
> +#include <linux/stddef.h>
> +#include <linux/kernel.h>
> +#include <linux/pci.h>
> +#include <linux/kdev_t.h>
> +#include <linux/console.h>
> +#include <linux/delay.h>
> +#include <linux/irq.h>
> +#include <linux/ide.h>
> +#include <linux/seq_file.h>
> +#include <linux/root_dev.h>
> +#include <linux/serial.h>
> +#include <linux/tty.h>
> +#include <linux/serial_core.h>
> +
> +#include <asm/system.h>
> +#include <asm/time.h>
> +#include <asm/machdep.h>
> +#include <asm/prom.h>
> +#include <asm/udbg.h>
> +#include <asm/tsi108.h>
> +#include <asm/pci-bridge.h>
> +#include <asm/reg.h>
> +#include <mm/mmu_decl.h>
> +#include "mpc7448_hpc2.h"
> +#include <asm/tsi108_pic.h>
> +
> +#ifndef CONFIG_PCI
> +isa_io_base = MPC7448_HPC2_ISA_IO_BASE;
> +isa_mem_base = MPC7448_HPC2_ISA_MEM_BASE;
> +pci_dram_offset = MPC7448_HPC2_PCI_MEM_OFFSET;
> +#endif
> +
> +extern int add_bridge(struct device_node *dev);
> +extern void mpc7448_hpc2_restart(char *cmd);
> +extern void mpc7448_hpc2_power_off(void);
> +extern void mpc7448_hpc2_halt(void);
> +
> +#ifdef TSI108_ETH
> +hw_info hw_info_table[TSI108_ETH_MAX_PORTS + 1] = {
> +	{TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
> +	 TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
> +	 TSI108_PHY0_ADDR, IRQ_TSI108_GIGE0},
> +
> +	{TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET + 0x400,
> +	 TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
> +	 TSI108_PHY1_ADDR, IRQ_TSI108_GIGE1},
> +
> +	{TBL_END, TBL_END, TBL_END, TBL_END}
> +};
> +#endif

This table looks problematic.  Look at using something like a  
platform device.

> +
> +/*
> + * Define all of the IRQ senses and polarities.  Taken from the
> + * mpc7448hpc  manual.
> + * Note:  Likely, this table and the following function should be
> + *        obtained and derived from the OF Device Tree.
> + */
> +
> +static u_char mpc7448_hpc2_pic_initsenses[] __initdata = {
> +	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* INT[0] XINT0 from  
> FPGA */
> +	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* INT[1] XINT1 from  
> FPGA */
> +	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* INT[2] PHY_INT from  
> both GIGE */
> +	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* INT[3] RESERVED */
> +};
> +
> +/*
> + * mpc7448hpc2 PCI interrupt routing. all PCI interrupt comes from
> + * external PCI source at 23. need to program pci interrupt  
> control registers
> + * to route per slot IRQs.
> + */
> +
> +static inline int
> +mpc7448_hpc2_map_irq(struct pci_dev *dev, unsigned char idsel,
> +		     unsigned char pin)
> +{
> +	static char pci_irq_table[][4] =
> +	    /*
> +	     *      PCI IDSEL/INTPIN->INTLINE
> +	     *         A     B     C     D
> +	     */
> +	{
> +		{IRQ_PCI_INTA, IRQ_PCI_INTB, IRQ_PCI_INTC, IRQ_PCI_INTD},	/* A  
> SLOT 1 IDSEL 17 */
> +		{IRQ_PCI_INTB, IRQ_PCI_INTC, IRQ_PCI_INTD, IRQ_PCI_INTA},	/* B  
> SLOT 2 IDSEL 18 */
> +		{IRQ_PCI_INTC, IRQ_PCI_INTD, IRQ_PCI_INTA, IRQ_PCI_INTB},	/* C  
> SATA IDSEL 19 */
> +		{IRQ_PCI_INTD, IRQ_PCI_INTA, IRQ_PCI_INTB, IRQ_PCI_INTC},	/* D  
> USB IDSEL 20 */
> +	};
> +
> +	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
> +	return PCI_IRQ_TABLE_LOOKUP;
> +}
> +
> +int mpc7448_hpc2_exclude_device(u_char bus, u_char devfn)
> +{
> +	if (bus == 0 && PCI_SLOT(devfn) == 0)
> +		return PCIBIOS_DEVICE_NOT_FOUND;
> +	else
> +		return PCIBIOS_SUCCESSFUL;
> +}
> +
> +static __inline__ void mpc7448_hpc2_l2cr_prefetch_enable(void)
> +{
> +	unsigned long msscr0;
> +	__asm__ __volatile__("mfspr %0, 0x3f6\n \
> +		ori %0,%0,0x3\n	         \
> +		sync \n                  \
> +		mtspr 0x3f6,%0\n   \
> +		sync\n			 \
> +		isync ":"=r"(msscr0));
> +}
> +
> +static void __init mpc7448_hpc2_setup_arch(void)
> +{
> +	struct device_node *cpu;
> +	struct device_node *np;
> +	if (ppc_md.progress)
> +		ppc_md.progress("mpc7448_hpc2_setup_arch():set_bridge", 0);
> +
> +	cpu = of_find_node_by_type(NULL, "cpu");
> +	if (cpu != 0) {
> +		unsigned int *fp;
> +
> +		fp = (int *)get_property(cpu, "clock-frequency", NULL);
> +		if (fp != 0)
> +			loops_per_jiffy = *fp / HZ;
> +		else
> +			loops_per_jiffy = 50000000 / HZ;
> +		of_node_put(cpu);
> +	}
> +
> +#ifdef	CONFIG_ROOT_NFS
> +	ROOT_DEV = Root_NFS;
> +#else
> +	ROOT_DEV = Root_HDA1;
> +#endif
> +
> +#ifdef CONFIG_BLK_DEV_INITRD
> +	ROOT_DEV = Root_RAM0;
> +#endif
> +
> +	/* setup PCI host bridge */
> +
> +#ifdef CONFIG_PCI
> +
> +	for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
> +		add_bridge(np);
> +
> +	ppc_md.pci_swizzle = common_swizzle;
> +	ppc_md.pci_map_irq = mpc7448_hpc2_map_irq;
> +	ppc_md.pci_exclude_device = mpc7448_hpc2_exclude_device;
> +	if (ppc_md.progress)
> +		ppc_md.progress("tsi108: resources set", 0x100);
> +#endif
> +
> +#ifdef CONFIG_DUMMY_CONSOLE
> +	conswitchp = &dummy_con;
> +#endif
> +
> +	printk(KERN_INFO "MPC7448HPC2 (TAIGA) Platform\n");
> +	printk(KERN_INFO
> +	       "Jointly ported by Freescale and Tundra Semiconductor\n");
> +	printk(KERN_INFO
> +	       "Enabling L2 cache then enabling the HID0 prefetch engine. 
> \n");
> +	_set_L2CR(L2CR_L2E);
> +	mpc7448_hpc2_l2cr_prefetch_enable();

Hmm, can't remember what happens with the L2 setup on 74xx.

> +}
> +
> +/*
> + * Interrupt setup and service.  Interrrupts on the mpc7448_hpc2 come
> + * from the four external INT pins, PCI interrupts are routed via
> + * PCI interrupt control registers, it generates internal IRQ23
> + *
> + * Interrupt routing on the Taiga Board:
> + * TSI108:PB_INT[0] -> CPU0:INT#
> + * TSI108:PB_INT[1] -> CPU0:MCP#
> + * TSI108:PB_INT[2] -> N/C
> + * TSI108:PB_INT[3] -> N/C
> + */
> +static void __init mpc7448_hpc2_init_IRQ(void)
> +{
> +
> +	tsi108_pic_init(mpc7448_hpc2_pic_initsenses);
> +
> +	/* Configure MPIC outputs to CPU0 */
> +	tsi108_pic_set_output(0, IRQ_SENSE_EDGE, IRQ_POLARITY_NEGATIVE);
> +}
> +
> +static void __init mpc7448_hpc2_map_io(void)
> +{
> +	/* PCI IO  mapping */
> +	io_block_mapping(MPC7448_HPC2_PCI_IO_BASE_VIRT,
> +			 MPC7448_HPC2_PCI_IO_BASE_PHYS, 0x00800000, _PAGE_IO);
> +	/* Tsi108 CSR mapping */
> +	io_block_mapping(TSI108_CSR_ADDR_VIRT, TSI108_CSR_ADDR_PHYS,
> +			 0x100000, _PAGE_IO);
> +
> +	/* PCI Config mapping */
> +	io_block_mapping(MPC7448_HPC2_PCI_CFG_BASE_VIRT,
> +			 MPC7448_HPC2_PCI_CFG_BASE_PHYS,
> +			 MPC7448_HPC2_PCI_CFG_SIZE, _PAGE_IO);
> +
> +	tsi108_pci_cfg_base = MPC7448_HPC2_PCI_CFG_BASE_VIRT;
> +	/* NVRAM mapping */
> +	io_block_mapping(MPC7448_HPC2_NVRAM_BASE_ADDR,
> +			 MPC7448_HPC2_NVRAM_BASE_ADDR, MPC7448_HPC2_NVRAM_SIZE,
> +			 _PAGE_IO);
> +}

You need to do this another way, we are trying to avoid using  
io_block_mapping()

> +
> +void mpc7448_hpc2_show_cpuinfo(struct seq_file *m)
> +{
> +	seq_printf(m, "vendor\t\t: Freescale Semiconductor\n");
> +	seq_printf(m, "machine\t\t: MPC7448hpc2\n");
> +}
> +
> +/*
> + * Called very early, device-tree isn't unflattened
> + */
> +static int __init mpc7448_hpc2_probe(void)
> +{
> +	/* We always match for now, eventually we should look at the flat
> +	   dev tree to ensure this is the board we are suppose to run on
> +	 */
> +	return 1;
> +}
> +
> +define_machine(mpc7448_hpc2){
> +	.name 			= "MPC7448 HPC2",
> +	.probe 			= mpc7448_hpc2_probe,
> +	.setup_arch 		= mpc7448_hpc2_setup_arch,
> +	.init_IRQ 		= mpc7448_hpc2_init_IRQ,
> +	.show_cpuinfo 		= mpc7448_hpc2_show_cpuinfo,
> +	.get_irq 		= tsi108_pic_get_irq,
> +	.restart 		= mpc7448_hpc2_restart,
> +	.calibrate_decr 	= generic_calibrate_decr,
> +	.setup_io_mappings 	= mpc7448_hpc2_map_io,
> +	.progress 		= udbg_progress,
> +};
> diff --git a/arch/powerpc/platforms/74xx/mpc7448_hpc2.h b/arch/ 
> powerpc/platforms/74xx/mpc7448_hpc2.h
> new file mode 100644
> index 0000000..8833520
> --- /dev/null
> +++ b/arch/powerpc/platforms/74xx/mpc7448_hpc2.h
> @@ -0,0 +1,80 @@
> +/*
> + * mpc7448_hpc2.h
> + *
> + * Definitions for Freescale MPC7448_HPC2 platform
> + *
> + * Author: Jacob Pan
> + *         jacob.pan@freescale.com
> + * Maintainer: Roy Zang <roy.zang@freescale.com>
> + *
> + * 2006 (c) Freescale Semiconductor, Inc.  This file is licensed  
> under
> + * the terms of the GNU General Public License version 2.  This  
> program
> + * is licensed "as is" without any warranty of any kind, whether  
> express
> + * or implied.
> + */
> +
> +#ifndef __PPC_PLATFORMS_MPC7448_HPC2_H
> +#define __PPC_PLATFORMS_MPC7448_HPC2_H
> +
> +#include <asm/ppcboot.h>
> +
> +/* Ethernet defines
> + */
> +#define TSI108_ETH
> +#define TSI108_ETH_MAX_PORTS	(2)	/* TSI108 Ethernet block has 2  
> ports */
> +#define TSI108_PHY0_ADDR	(8)	/* PHY address for GIGE port 0 */
> +#define TSI108_PHY1_ADDR	(9)	/* PHY address for GIGE port 1 */
> +
> +/* Base Addresses for the PCI bus
> + * HOST_PCI initiator (outbound) window to PCI bus
> + */
> +#define MPC7448_HPC2_PCI_MEM_OFFSET	(0x00000000)
> +#define MPC7448_HPC2_PCI_IO_BASE_PHYS	(0xfa000000)
> +#define MPC7448_HPC2_PCI_IO_BASE_VIRT	(MPC7448_HPC2_PCI_IO_BASE_PHYS)
> +#define MPC7448_HPC2_PCI_MEM_BASE	(0xe0000000)
> +#define MPC7448_HPC2_ISA_IO_BASE	(0x00000000)
> +#define MPC7448_HPC2_ISA_MEM_BASE	(0x00000000)
> +
> +#define MPC7448_HPC2_PCI_CFG_BASE_PHYS	(0xfb000000)
> +#define MPC7448_HPC2_PCI_CFG_BASE_VIRT	 
> (MPC7448_HPC2_PCI_CFG_BASE_PHYS)
> +#define MPC7448_HPC2_PCI_CFG_SIZE	(0x01000000)
> +
> +#define MPC7448_HPC2_PCI_MEM_START	(0xE0000000)
> +#define MPC7448_HPC2_PCI_MEM_END	(0xF9FFFFFF)
> +
> +#define MPC7448_HPC2_PCI_IO_START	(0xFA000000)
> +#define MPC7448_HPC2_PCI_IO_END	(0xFA00FFFF)
> +
> +#define MPC7448_HPC2_PCI_CFG_OFFSET	(0xFB000000)
> +#define MPC7448_HPC2_PCI_IO_OFFSET	(0xFA000000)
> +
> +#define MPC7448_HPC2_PCI_MEM32_OFFSET	0x00000000	/* PCI MEM32  
> space offset within
> +							   the PCI window */
> +#define MPC7448_HPC2_PCI_PFM_OFFSET	0x10000000	/* PCI PFM1 space  
> offset within
> +							   the PCI window */

Can you not determine these from your flat device tree?

> +
> +/* Memory-mapped CIU resources (CPU view)
> + * The memory map is set by initialization code in monitor
> + */
> +
> +#define TSI108_CSR_ADDR_PHYS	(0xC0000000)	/* Physical Tsi108 CSR  
> Base Address */
> +#define TSI108_CSR_ADDR_VIRT	(0xF0000000)	/* Virtual Tsi108 CSR  
> Base Address */

Don't use hard coded VIRT addresses.

> +
> +#define FLASH_BASE_ADDR		(0xFF000000)	/* Boot FLASH Base Address */
> +
> +#define SDRAM_BASE_ADDR		0x00000000	/* SDRAM base address */
> +#define BOARD_SDRAM_SIZE	0x20000000	/* Default value: 512MB */
> +
> +/* Size of SDRAM space reserved for user space. This limits space  
> available
> + * for dynamic allocation.
> + */
> +#define USER_RESERVED_MEM	(BOARD_SDRAM_SIZE - 0x02000000)
> +
> +#define USER_RESERVED_BASE  \
> +  (SDRAM_BASE_ADDR + (BOARD_SDRAM_SIZE - USER_RESERVED_MEM)
> +
> +/* Memory mapped NVRAM/RTC */
> +#define MPC7448_HPC2_NVRAM_BASE_ADDR	(0xFC000000)
> +#define MPC7448_HPC2_NVRAM_SIZE	(0x8000)
> +
> +#endif				/* __PPC_PLATFORMS_MPC7448_HPC2_H */
> diff --git a/arch/powerpc/platforms/74xx/pci.c b/arch/powerpc/ 
> platforms/74xx/pci.c
> new file mode 100644
> index 0000000..fd822ed
> --- /dev/null
> +++ b/arch/powerpc/platforms/74xx/pci.c

If this is generic to the tsi108 rename to something like  
tsi108_pci.c as its not generic to 74xx or embedded6xx.

> @@ -0,0 +1,103 @@
> +/*
> + * TSI 108 PCI hose setup up code
> + *
> + * Maintained by Roy Zang
> + *
> + * This program is free software; you can redistribute  it and/or  
> modify it
> + * under  the terms of  the GNU General  Public License as  
> published by the
> + * Free Software Foundation;  either version 2 of the  License, or  
> (at your
> + * option) any later version.
> + */
> +
> +#include <linux/config.h>
> +#include <linux/stddef.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <linux/pci.h>
> +#include <linux/delay.h>
> +#include <linux/irq.h>
> +#include <linux/module.h>
> +
> +#include <asm/system.h>
> +#include <asm/atomic.h>
> +#include <asm/io.h>
> +#include <asm/pci-bridge.h>
> +#include <asm/prom.h>
> +#include <asm/tsi108.h>
> +#include "mpc7448_hpc2.h"

What's this included needed for?

> +
> +#undef DEBUG
> +
> +#ifdef DEBUG
> +#define DBG(x...) printk(x)
> +#else
> +#define DBG(x...)
> +#endif
> +
> +extern int tsi108_direct_write_config(struct pci_bus *bus,  
> unsigned int devfn,
> +				      int offset, int len, u32 val);
> +extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned  
> int devfn,
> +				     int offset, int len, u32 * val);
> +

Can you not use indirect pci support that already exists?

> +void tsi108_clear_pci_error(u32 pci_cfg_base);
> +
> +extern int
> +tsi108_read_config(int bus, unsigned int devfn, int offset, int  
> len, u32 * val);
> +#ifdef CONFIG_PCI
> +static struct pci_ops direct_pci_ops = {
> +	tsi108_direct_read_config,
> +	tsi108_direct_write_config
> +};
> +
> +void tsi108_clear_pci_cfg_error(void)
> +{
> +	tsi108_clear_pci_error(MPC7448_HPC2_PCI_CFG_BASE_PHYS);
> +}
> +
> +int __init add_bridge(struct device_node *dev)
> +{
> +	int len;
> +	struct pci_controller *hose;
> +	struct resource rsrc;
> +	int *bus_range;
> +	int primary = 0, has_address = 0;
> +
> +	DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
> +	    tsi108_pci_cfg_base);
> +
> +	/* Fetch host bridge registers address */
> +	has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
> +
> +	/* Get bus range if any */
> +	bus_range = (int *)get_property(dev, "bus-range", &len);
> +	if (bus_range == NULL || len < 2 * sizeof(int)) {
> +		printk(KERN_WARNING "Can't get bus-range for %s, assume"
> +		       " bus 0\n", dev->full_name);
> +	}
> +
> +	hose = pcibios_alloc_controller();
> +
> +	if (!hose) {
> +		printk("PCI Host bridge init failed\n");
> +		return -ENOMEM;
> +	}
> +	hose->arch_data = dev;
> +	hose->set_cfg_type = 1;
> +
> +	hose->first_busno = bus_range ? bus_range[0] : 0;
> +	hose->last_busno = bus_range ? bus_range[1] : 0xff;
> +
> +	(hose)->ops = &direct_pci_ops;
> +
> +	printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08lx. "
> +	       "Firmware bus number: %d->%d\n",
> +	       rsrc.start, hose->first_busno, hose->last_busno);
> +
> +	/* Interpret the "ranges" property */
> +	/* This also maps the I/O region and sets isa_io/mem_base */
> +	pci_process_bridge_OF_ranges(hose, dev, primary);
> +	return 0;
> +
> +}
> +#endif
> diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/ 
> platforms/Makefile
> index c4f6b0d..71ca0e0 100644
> --- a/arch/powerpc/platforms/Makefile
> +++ b/arch/powerpc/platforms/Makefile
> @@ -9,6 +9,7 @@ obj-$(CONFIG_PPC_CHRP)		+= chrp/
>  obj-$(CONFIG_4xx)		+= 4xx/
>  obj-$(CONFIG_PPC_83xx)		+= 83xx/
>  obj-$(CONFIG_PPC_85xx)		+= 85xx/
> +obj-$(CONFIG_74xx)		+= 74xx/
>  obj-$(CONFIG_PPC_PSERIES)	+= pseries/
>  obj-$(CONFIG_PPC_ISERIES)	+= iseries/
>  obj-$(CONFIG_PPC_MAPLE)		+= maple/
> -- 
> 1.3.0
>
>
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Zang Roy-r61911]

 
> 
> On May 17, 2006, at 5:13 AM, Zang Roy-r61911 wrote:
> 
> > Add support for Freescale mpcc7448 (Taiga) board support
> >
> > Signed-off-by: Roy Zang  <tie-fei.zang@freescale.com>
> >
> > ---
> >
> >  arch/powerpc/Kconfig                       |   24 +++
> >  arch/powerpc/kernel/legacy_serial.c        |   39 ++++
> 
> These board port should live in platforms/embedded6xx.

Should the mpc7448hpc2 board support code be moved to
embedded6xx?

> 
> >  arch/powerpc/platforms/74xx/Makefile       |    4
> >  arch/powerpc/platforms/74xx/misc.c         |   38 ++++
> >  arch/powerpc/platforms/74xx/mpc7448_hpc2.c |  257 
> +++++++++++++++++ 
> > +++++++++++
> >  arch/powerpc/platforms/74xx/mpc7448_hpc2.h |   80 +++++++++
> >  arch/powerpc/platforms/74xx/pci.c          |  103 +++++++++++
> >  arch/powerpc/platforms/Makefile            |    1
> >  8 files changed, 545 insertions(+), 1 deletions(-)
> >  create mode 100644 arch/powerpc/platforms/74xx/Makefile
> >  create mode 100644 arch/powerpc/platforms/74xx/misc.c
> >  create mode 100644 arch/powerpc/platforms/74xx/mpc7448_hpc2.c
> >  create mode 100644 arch/powerpc/platforms/74xx/mpc7448_hpc2.h
> >  create mode 100644 arch/powerpc/platforms/74xx/pci.c
> >
> > 13c16416da4fa51ec771bd4863d94344d139b2f5
> > diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> > index 6729c98..abeac1f 100644
> > --- a/arch/powerpc/Kconfig
> > +++ b/arch/powerpc/Kconfig
> > @@ -332,6 +332,27 @@ config APUS
> >  	  Select APUS if configuring for a PowerUP Amiga.
> >  	  More information is available at:
> >  	  <http://linux-apus.sourceforge.net/>.
> > +
> > +config MPC7448HPC2
> > +	bool "Freescale MPC7448HPC2(Taiga)"
> > +	select DEFAULT_UIMAGE
> > +	select PPC_UDBG_16550
> > +	help
> > +	  Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2  
> > (Taiga)
> > +	  platform
> > +
> > +config 74xx
> > +	bool
> > +	depends on MPC7448HPC2
> > +	default y
> > +	help
> > +	  Select 74xx support
> > +
> 
> What is the config option used for?  We should get ride of.

This config option is used to build the directory arch/powerpc/platforms/74xx
If the board support code will move to embedded6xx, this option can be removed.

> 
> > +config TSI108_BRIDGE
> > +	bool
> > +	depends on MPC7448HPC2
> > +	default y
> > +	
> >  endchoice
> >
> >  config PPC_PSERIES
> > @@ -798,7 +819,8 @@ config MCA
> >  	bool
> >
> >  config PCI
> > -	bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx ||  
> > PPC_MPC52xx || (EMBEDDED && PPC_ISERIES)
> > +	bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx ||  
> > PPC_MPC52xx || (EMBEDDED && PPC_ISERIES) \
> > +				  || MPC7448HPC2
> >  	default y if !40x && !CPM2 && !8xx && !APUS && !PPC_83xx && ! 
> > PPC_85xx
> >  	default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS
> >  	default PCI_QSPAN if !4xx && !CPM2 && 8xx
> > diff --git a/arch/powerpc/kernel/legacy_serial.c b/arch/powerpc/ 
> > kernel/legacy_serial.c
> > index 6e67b5b..f99238d 100644
> > --- a/arch/powerpc/kernel/legacy_serial.c
> > +++ b/arch/powerpc/kernel/legacy_serial.c
> > @@ -134,6 +134,34 @@ static int __init add_legacy_soc_port(st
> >  	return add_legacy_port(np, -1, UPIO_MEM, addr, addr, 
> NO_IRQ, flags);
> >  }
> >
> > +static int __init add_legacy_tsi_port(struct device_node *np,
> > +				      struct device_node *tsi_dev)
> > +{
> > +	phys_addr_t addr;
> > +	u32 *addrp;
> > +	upf_t flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
> > +
> > +	/* We only support ports that have a clock frequency properly
> > +	 * encoded in the device-tree.
> > +	 */
> > +	if (get_property(np, "clock-frequency", NULL) == NULL)
> > +		return -1;
> > +
> > +	/* Get the address */
> > +	addrp = of_get_address(tsi_dev, 0, NULL, NULL);
> > +	if (addrp == NULL)
> > +		return -1;
> > +
> > +	addr = of_translate_address(tsi_dev, addrp);
> > +
> > +	/* Add port, irq will be dealt with later. We passed a 
> translated
> > +	 * IO port value. It will be fixed up later along with the irq
> > +	 */
> > +	return add_legacy_port(np, -1, UPIO_MEM, addr, addr, 
> NO_IRQ, flags);
> > +}
> > +
> 
> This looks like its duplicating add_legacy_soc_port, why not 
> use that  
> instead?

The tsi108 serial port is not a sub node of "soc".  well, any way,
I can try soc!

> 
> > +
> > +
> >  static int __init add_legacy_isa_port(struct device_node *np,
> >  				      struct device_node *isa_brg)
> >  {
> > @@ -302,6 +330,17 @@ void __init find_legacy_serial_ports(voi
> >  		of_node_put(isa);
> >  	}
> >
> > +	/* First fill our array with tsi-bridge ports */
> > +	for (np = NULL; (np = of_find_compatible_node(np, "serial",  
> > "ns16550")) != NULL;) {
> > +		struct device_node *tsi = of_get_parent(np);
> > +		if (tsi && !strcmp(tsi->type, "tsi-bridge")) {
> > +			index = add_legacy_tsi_port(np, np);
> > +			if (index >= 0 && np == stdout)
> > +				legacy_serial_console = index;
> > +		}
> > +		of_node_put(tsi);
> > +	}
> > +	
> >  #ifdef CONFIG_PCI
> >  	/* Next, try to locate PCI ports */
> >  	for (np = NULL; (np = of_find_all_nodes(np));) {
> > diff --git a/arch/powerpc/platforms/74xx/Makefile b/arch/powerpc/ 
> > platforms/74xx/Makefile
> > new file mode 100644
> > index 0000000..ed5648c
> > --- /dev/null
> > +++ b/arch/powerpc/platforms/74xx/Makefile
> > @@ -0,0 +1,4 @@
> > +#
> > +# Makefile for the PowerPC 74xx linux kernel.
> > +#
> > +obj-$(CONFIG_MPC7448HPC2)	+= mpc7448_hpc2.o pci.o misc.o
> > diff --git a/arch/powerpc/platforms/74xx/misc.c b/arch/powerpc/ 
> > platforms/74xx/misc.c
> > new file mode 100644
> > index 0000000..6228875
> > --- /dev/null
> > +++ b/arch/powerpc/platforms/74xx/misc.c
> > @@ -0,0 +1,38 @@
> > +
> > +/*
> > + * MPC74xx generic code.
> > + *
> > + * Maintained by Roy Zang
> > + *
> > + * Copyright 2006 Freescale Semiconductor Inc.
> > + *
> > + * This program is free software; you can redistribute  it and/or  
> > modify it
> > + * under  the terms of  the GNU General  Public License as  
> > published by the
> > + * Free Software Foundation;  either version 2 of the  
> License, or  
> > (at your
> > + * option) any later version.
> > + */
> > +#include <linux/irq.h>
> > +#include <linux/module.h>
> > +#include <asm/irq.h>
> > +extern void _nmask_and_or_msr(unsigned long nmask, unsigned long  
> > or_val);
> > +
> > +void mpc7448_hpc2_restart(char *cmd)
> > +{
> > +	local_irq_disable();
> > +
> > +	/* Set exception prefix high - to the firmware */
> > +	_nmask_and_or_msr(0, MSR_IP);
> > +
> > +	for (;;) ;		/* Spin until reset happens */
> > +}
> > +
> > +void mpc7448_hpc2_power_off(void)
> > +{
> > +	local_irq_disable();
> > +	for (;;) ;		/* No way to shut power off 
> with software */
> > +}
> > +
> > +void mpc7448_hpc2_halt(void)
> > +{
> > +	mpc7448_hpc2_power_off();
> > +}
> 
> Move these back into mpc7448_hpc2.c.  They are to specific to hpc2.
 
OK!

> 
> > diff --git a/arch/powerpc/platforms/74xx/mpc7448_hpc2.c b/arch/ 
> > powerpc/platforms/74xx/mpc7448_hpc2.c
> > new file mode 100644
> > index 0000000..b060ae1
> > --- /dev/null
> > +++ b/arch/powerpc/platforms/74xx/mpc7448_hpc2.c
> > @@ -0,0 +1,257 @@
> > +/*
> > + * mpc7448_hpc2.c
> > + *
> > + * Board setup routines for the Freescale Taiga platform
> > + *
> > + * Author: Jacob Pan
> > + *	 jacob.pan@freescale.com
> > + * Author: Xianghua Xiao
> > + *       updated for taiga board from emulation platform 2005.5
> > + *       x.xiao@freescale.com
> > + * Maintainer: Roy Zang <tie-fei.zang@freescale.com>
> > + *
> > + * Copyright 2004-2006 Freescale Semiconductor, Inc.
> > + *
> > + * This file is licensed under
> > + * the terms of the GNU General Public License version 2.  This  
> > program
> > + * is licensed "as is" without any warranty of any kind, whether  
> > express
> > + * or implied.
> > + */
> > +
> > +#include <linux/config.h>
> > +#include <linux/stddef.h>
> > +#include <linux/kernel.h>
> > +#include <linux/pci.h>
> > +#include <linux/kdev_t.h>
> > +#include <linux/console.h>
> > +#include <linux/delay.h>
> > +#include <linux/irq.h>
> > +#include <linux/ide.h>
> > +#include <linux/seq_file.h>
> > +#include <linux/root_dev.h>
> > +#include <linux/serial.h>
> > +#include <linux/tty.h>
> > +#include <linux/serial_core.h>
> > +
> > +#include <asm/system.h>
> > +#include <asm/time.h>
> > +#include <asm/machdep.h>
> > +#include <asm/prom.h>
> > +#include <asm/udbg.h>
> > +#include <asm/tsi108.h>
> > +#include <asm/pci-bridge.h>
> > +#include <asm/reg.h>
> > +#include <mm/mmu_decl.h>
> > +#include "mpc7448_hpc2.h"
> > +#include <asm/tsi108_pic.h>
> > +
> > +#ifndef CONFIG_PCI
> > +isa_io_base = MPC7448_HPC2_ISA_IO_BASE;
> > +isa_mem_base = MPC7448_HPC2_ISA_MEM_BASE;
> > +pci_dram_offset = MPC7448_HPC2_PCI_MEM_OFFSET;
> > +#endif
> > +
> > +extern int add_bridge(struct device_node *dev);
> > +extern void mpc7448_hpc2_restart(char *cmd);
> > +extern void mpc7448_hpc2_power_off(void);
> > +extern void mpc7448_hpc2_halt(void);
> > +
> > +#ifdef TSI108_ETH
> > +hw_info hw_info_table[TSI108_ETH_MAX_PORTS + 1] = {
> > +	{TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
> > +	 TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
> > +	 TSI108_PHY0_ADDR, IRQ_TSI108_GIGE0},
> > +
> > +	{TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET + 0x400,
> > +	 TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
> > +	 TSI108_PHY1_ADDR, IRQ_TSI108_GIGE1},
> > +
> > +	{TBL_END, TBL_END, TBL_END, TBL_END}
> > +};
> > +#endif
> 
> This table looks problematic.  Look at using something like a  
> platform device.

I will try it! 

> 
> > +
> > +/*
> > + * Define all of the IRQ senses and polarities.  Taken from the
> > + * mpc7448hpc  manual.
> > + * Note:  Likely, this table and the following function should be
> > + *        obtained and derived from the OF Device Tree.
> > + */
> > +
> > +static u_char mpc7448_hpc2_pic_initsenses[] __initdata = {
> > +	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* 
> INT[0] XINT0 from  
> > FPGA */
> > +	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* 
> INT[1] XINT1 from  
> > FPGA */
> > +	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* 
> INT[2] PHY_INT from  
> > both GIGE */
> > +	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* 
> INT[3] RESERVED */
> > +};
> > +
> > +/*
> > + * mpc7448hpc2 PCI interrupt routing. all PCI interrupt comes from
> > + * external PCI source at 23. need to program pci interrupt  
> > control registers
> > + * to route per slot IRQs.
> > + */
> > +
> > +static inline int
> > +mpc7448_hpc2_map_irq(struct pci_dev *dev, unsigned char idsel,
> > +		     unsigned char pin)
> > +{
> > +	static char pci_irq_table[][4] =
> > +	    /*
> > +	     *      PCI IDSEL/INTPIN->INTLINE
> > +	     *         A     B     C     D
> > +	     */
> > +	{
> > +		{IRQ_PCI_INTA, IRQ_PCI_INTB, IRQ_PCI_INTC, 
> IRQ_PCI_INTD},	/* A  
> > SLOT 1 IDSEL 17 */
> > +		{IRQ_PCI_INTB, IRQ_PCI_INTC, IRQ_PCI_INTD, 
> IRQ_PCI_INTA},	/* B  
> > SLOT 2 IDSEL 18 */
> > +		{IRQ_PCI_INTC, IRQ_PCI_INTD, IRQ_PCI_INTA, 
> IRQ_PCI_INTB},	/* C  
> > SATA IDSEL 19 */
> > +		{IRQ_PCI_INTD, IRQ_PCI_INTA, IRQ_PCI_INTB, 
> IRQ_PCI_INTC},	/* D  
> > USB IDSEL 20 */
> > +	};
> > +
> > +	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
> > +	return PCI_IRQ_TABLE_LOOKUP;
> > +}
> > +
> > +int mpc7448_hpc2_exclude_device(u_char bus, u_char devfn)
> > +{
> > +	if (bus == 0 && PCI_SLOT(devfn) == 0)
> > +		return PCIBIOS_DEVICE_NOT_FOUND;
> > +	else
> > +		return PCIBIOS_SUCCESSFUL;
> > +}
> > +
> > +static __inline__ void mpc7448_hpc2_l2cr_prefetch_enable(void)
> > +{
> > +	unsigned long msscr0;
> > +	__asm__ __volatile__("mfspr %0, 0x3f6\n \
> > +		ori %0,%0,0x3\n	         \
> > +		sync \n                  \
> > +		mtspr 0x3f6,%0\n   \
> > +		sync\n			 \
> > +		isync ":"=r"(msscr0));
> > +}
> > +
> > +static void __init mpc7448_hpc2_setup_arch(void)
> > +{
> > +	struct device_node *cpu;
> > +	struct device_node *np;
> > +	if (ppc_md.progress)
> > +		
> ppc_md.progress("mpc7448_hpc2_setup_arch():set_bridge", 0);
> > +
> > +	cpu = of_find_node_by_type(NULL, "cpu");
> > +	if (cpu != 0) {
> > +		unsigned int *fp;
> > +
> > +		fp = (int *)get_property(cpu, "clock-frequency", NULL);
> > +		if (fp != 0)
> > +			loops_per_jiffy = *fp / HZ;
> > +		else
> > +			loops_per_jiffy = 50000000 / HZ;
> > +		of_node_put(cpu);
> > +	}
> > +
> > +#ifdef	CONFIG_ROOT_NFS
> > +	ROOT_DEV = Root_NFS;
> > +#else
> > +	ROOT_DEV = Root_HDA1;
> > +#endif
> > +
> > +#ifdef CONFIG_BLK_DEV_INITRD
> > +	ROOT_DEV = Root_RAM0;
> > +#endif
> > +
> > +	/* setup PCI host bridge */
> > +
> > +#ifdef CONFIG_PCI
> > +
> > +	for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
> > +		add_bridge(np);
> > +
> > +	ppc_md.pci_swizzle = common_swizzle;
> > +	ppc_md.pci_map_irq = mpc7448_hpc2_map_irq;
> > +	ppc_md.pci_exclude_device = mpc7448_hpc2_exclude_device;
> > +	if (ppc_md.progress)
> > +		ppc_md.progress("tsi108: resources set", 0x100);
> > +#endif
> > +
> > +#ifdef CONFIG_DUMMY_CONSOLE
> > +	conswitchp = &dummy_con;
> > +#endif
> > +
> > +	printk(KERN_INFO "MPC7448HPC2 (TAIGA) Platform\n");
> > +	printk(KERN_INFO
> > +	       "Jointly ported by Freescale and Tundra 
> Semiconductor\n");
> > +	printk(KERN_INFO
> > +	       "Enabling L2 cache then enabling the HID0 
> prefetch engine. 
> > \n");
> > +	_set_L2CR(L2CR_L2E);
> > +	mpc7448_hpc2_l2cr_prefetch_enable();
> 
> Hmm, can't remember what happens with the L2 setup on 74xx.

I will check it!

> 
> > +}
> > +
> > +/*
> > + * Interrupt setup and service.  Interrrupts on the 
> mpc7448_hpc2 come
> > + * from the four external INT pins, PCI interrupts are routed via
> > + * PCI interrupt control registers, it generates internal IRQ23
> > + *
> > + * Interrupt routing on the Taiga Board:
> > + * TSI108:PB_INT[0] -> CPU0:INT#
> > + * TSI108:PB_INT[1] -> CPU0:MCP#
> > + * TSI108:PB_INT[2] -> N/C
> > + * TSI108:PB_INT[3] -> N/C
> > + */
> > +static void __init mpc7448_hpc2_init_IRQ(void)
> > +{
> > +
> > +	tsi108_pic_init(mpc7448_hpc2_pic_initsenses);
> > +
> > +	/* Configure MPIC outputs to CPU0 */
> > +	tsi108_pic_set_output(0, IRQ_SENSE_EDGE, IRQ_POLARITY_NEGATIVE);
> > +}
> > +
> > +static void __init mpc7448_hpc2_map_io(void)
> > +{
> > +	/* PCI IO  mapping */
> > +	io_block_mapping(MPC7448_HPC2_PCI_IO_BASE_VIRT,
> > +			 MPC7448_HPC2_PCI_IO_BASE_PHYS, 
> 0x00800000, _PAGE_IO);
> > +	/* Tsi108 CSR mapping */
> > +	io_block_mapping(TSI108_CSR_ADDR_VIRT, TSI108_CSR_ADDR_PHYS,
> > +			 0x100000, _PAGE_IO);
> > +
> > +	/* PCI Config mapping */
> > +	io_block_mapping(MPC7448_HPC2_PCI_CFG_BASE_VIRT,
> > +			 MPC7448_HPC2_PCI_CFG_BASE_PHYS,
> > +			 MPC7448_HPC2_PCI_CFG_SIZE, _PAGE_IO);
> > +
> > +	tsi108_pci_cfg_base = MPC7448_HPC2_PCI_CFG_BASE_VIRT;
> > +	/* NVRAM mapping */
> > +	io_block_mapping(MPC7448_HPC2_NVRAM_BASE_ADDR,
> > +			 MPC7448_HPC2_NVRAM_BASE_ADDR, 
> MPC7448_HPC2_NVRAM_SIZE,
> > +			 _PAGE_IO);
> > +}
> 
> You need to do this another way, we are trying to avoid using  
> io_block_mapping()

OK! I will abandon io_block_mapping() :).

> 
> > +
> > +void mpc7448_hpc2_show_cpuinfo(struct seq_file *m)
> > +{
> > +	seq_printf(m, "vendor\t\t: Freescale Semiconductor\n");
> > +	seq_printf(m, "machine\t\t: MPC7448hpc2\n");
> > +}
> > +
> > +/*
> > + * Called very early, device-tree isn't unflattened
> > + */
> > +static int __init mpc7448_hpc2_probe(void)
> > +{
> > +	/* We always match for now, eventually we should look 
> at the flat
> > +	   dev tree to ensure this is the board we are suppose to run on
> > +	 */
> > +	return 1;
> > +}
> > +
> > +define_machine(mpc7448_hpc2){
> > +	.name 			= "MPC7448 HPC2",
> > +	.probe 			= mpc7448_hpc2_probe,
> > +	.setup_arch 		= mpc7448_hpc2_setup_arch,
> > +	.init_IRQ 		= mpc7448_hpc2_init_IRQ,
> > +	.show_cpuinfo 		= mpc7448_hpc2_show_cpuinfo,
> > +	.get_irq 		= tsi108_pic_get_irq,
> > +	.restart 		= mpc7448_hpc2_restart,
> > +	.calibrate_decr 	= generic_calibrate_decr,
> > +	.setup_io_mappings 	= mpc7448_hpc2_map_io,
> > +	.progress 		= udbg_progress,
> > +};
> > diff --git a/arch/powerpc/platforms/74xx/mpc7448_hpc2.h b/arch/ 
> > powerpc/platforms/74xx/mpc7448_hpc2.h
> > new file mode 100644
> > index 0000000..8833520
> > --- /dev/null
> > +++ b/arch/powerpc/platforms/74xx/mpc7448_hpc2.h
> > @@ -0,0 +1,80 @@
> > +/*
> > + * mpc7448_hpc2.h
> > + *
> > + * Definitions for Freescale MPC7448_HPC2 platform
> > + *
> > + * Author: Jacob Pan
> > + *         jacob.pan@freescale.com
> > + * Maintainer: Roy Zang <roy.zang@freescale.com>
> > + *
> > + * 2006 (c) Freescale Semiconductor, Inc.  This file is licensed  
> > under
> > + * the terms of the GNU General Public License version 2.  This  
> > program
> > + * is licensed "as is" without any warranty of any kind, whether  
> > express
> > + * or implied.
> > + */
> > +
> > +#ifndef __PPC_PLATFORMS_MPC7448_HPC2_H
> > +#define __PPC_PLATFORMS_MPC7448_HPC2_H
> > +
> > +#include <asm/ppcboot.h>
> > +
> > +/* Ethernet defines
> > + */
> > +#define TSI108_ETH
> > +#define TSI108_ETH_MAX_PORTS	(2)	/* TSI108 
> Ethernet block has 2  
> > ports */
> > +#define TSI108_PHY0_ADDR	(8)	/* PHY address for GIGE 
> port 0 */
> > +#define TSI108_PHY1_ADDR	(9)	/* PHY address for GIGE 
> port 1 */
> > +
> > +/* Base Addresses for the PCI bus
> > + * HOST_PCI initiator (outbound) window to PCI bus
> > + */
> > +#define MPC7448_HPC2_PCI_MEM_OFFSET	(0x00000000)
> > +#define MPC7448_HPC2_PCI_IO_BASE_PHYS	(0xfa000000)
> > +#define MPC7448_HPC2_PCI_IO_BASE_VIRT	
> (MPC7448_HPC2_PCI_IO_BASE_PHYS)
> > +#define MPC7448_HPC2_PCI_MEM_BASE	(0xe0000000)
> > +#define MPC7448_HPC2_ISA_IO_BASE	(0x00000000)
> > +#define MPC7448_HPC2_ISA_MEM_BASE	(0x00000000)
> > +
> > +#define MPC7448_HPC2_PCI_CFG_BASE_PHYS	(0xfb000000)
> > +#define MPC7448_HPC2_PCI_CFG_BASE_VIRT	 
> > (MPC7448_HPC2_PCI_CFG_BASE_PHYS)
> > +#define MPC7448_HPC2_PCI_CFG_SIZE	(0x01000000)
> > +
> > +#define MPC7448_HPC2_PCI_MEM_START	(0xE0000000)
> > +#define MPC7448_HPC2_PCI_MEM_END	(0xF9FFFFFF)
> > +
> > +#define MPC7448_HPC2_PCI_IO_START	(0xFA000000)
> > +#define MPC7448_HPC2_PCI_IO_END	(0xFA00FFFF)
> > +
> > +#define MPC7448_HPC2_PCI_CFG_OFFSET	(0xFB000000)
> > +#define MPC7448_HPC2_PCI_IO_OFFSET	(0xFA000000)
> > +
> > +#define MPC7448_HPC2_PCI_MEM32_OFFSET	0x00000000	
> /* PCI MEM32  
> > space offset within
> > +							   the 
> PCI window */
> > +#define MPC7448_HPC2_PCI_PFM_OFFSET	0x10000000	
> /* PCI PFM1 space  
> > offset within
> > +							   the 
> PCI window */
> 
> Can you not determine these from your flat device tree?

I can !

> 
> > +
> > +/* Memory-mapped CIU resources (CPU view)
> > + * The memory map is set by initialization code in monitor
> > + */
> > +
> > +#define TSI108_CSR_ADDR_PHYS	(0xC0000000)	/* 
> Physical Tsi108 CSR  
> > Base Address */
> > +#define TSI108_CSR_ADDR_VIRT	(0xF0000000)	/* 
> Virtual Tsi108 CSR  
> > Base Address */
> 
> Don't use hard coded VIRT addresses.

OK!

> 
> > +
> > +#define FLASH_BASE_ADDR		(0xFF000000)	/* Boot 
> FLASH Base Address */
> > +
> > +#define SDRAM_BASE_ADDR		0x00000000	/* 
> SDRAM base address */
> > +#define BOARD_SDRAM_SIZE	0x20000000	/* Default 
> value: 512MB */
> > +
> > +/* Size of SDRAM space reserved for user space. This limits space  
> > available
> > + * for dynamic allocation.
> > + */
> > +#define USER_RESERVED_MEM	(BOARD_SDRAM_SIZE - 0x02000000)
> > +
> > +#define USER_RESERVED_BASE  \
> > +  (SDRAM_BASE_ADDR + (BOARD_SDRAM_SIZE - USER_RESERVED_MEM)
> > +
> > +/* Memory mapped NVRAM/RTC */
> > +#define MPC7448_HPC2_NVRAM_BASE_ADDR	(0xFC000000)
> > +#define MPC7448_HPC2_NVRAM_SIZE	(0x8000)
> > +
> > +#endif				/* 
> __PPC_PLATFORMS_MPC7448_HPC2_H */
> > diff --git a/arch/powerpc/platforms/74xx/pci.c b/arch/powerpc/ 
> > platforms/74xx/pci.c
> > new file mode 100644
> > index 0000000..fd822ed
> > --- /dev/null
> > +++ b/arch/powerpc/platforms/74xx/pci.c
> 
> If this is generic to the tsi108 rename to something like  
> tsi108_pci.c as its not generic to 74xx or embedded6xx.

OK!

> 
> > @@ -0,0 +1,103 @@
> > +/*
> > + * TSI 108 PCI hose setup up code
> > + *
> > + * Maintained by Roy Zang
> > + *
> > + * This program is free software; you can redistribute  it and/or  
> > modify it
> > + * under  the terms of  the GNU General  Public License as  
> > published by the
> > + * Free Software Foundation;  either version 2 of the  
> License, or  
> > (at your
> > + * option) any later version.
> > + */
> > +
> > +#include <linux/config.h>
> > +#include <linux/stddef.h>
> > +#include <linux/kernel.h>
> > +#include <linux/init.h>
> > +#include <linux/errno.h>
> > +#include <linux/pci.h>
> > +#include <linux/delay.h>
> > +#include <linux/irq.h>
> > +#include <linux/module.h>
> > +
> > +#include <asm/system.h>
> > +#include <asm/atomic.h>
> > +#include <asm/io.h>
> > +#include <asm/pci-bridge.h>
> > +#include <asm/prom.h>
> > +#include <asm/tsi108.h>
> > +#include "mpc7448_hpc2.h"
> 
> What's this included needed for?
> 
> > +
> > +#undef DEBUG
> > +
> > +#ifdef DEBUG
> > +#define DBG(x...) printk(x)
> > +#else
> > +#define DBG(x...)
> > +#endif
> > +
> > +extern int tsi108_direct_write_config(struct pci_bus *bus,  
> > unsigned int devfn,
> > +				      int offset, int len, u32 val);
> > +extern int tsi108_direct_read_config(struct pci_bus *bus, 
> unsigned  
> > int devfn,
> > +				     int offset, int len, u32 * val);
> > +
> 
> Can you not use indirect pci support that already exists?

I am not sure, I will  have a try.

> 
> > +void tsi108_clear_pci_error(u32 pci_cfg_base);
> > +
> > +extern int
> > +tsi108_read_config(int bus, unsigned int devfn, int offset, int  
> > len, u32 * val);
> > +#ifdef CONFIG_PCI
> > +static struct pci_ops direct_pci_ops = {
> > +	tsi108_direct_read_config,
> > +	tsi108_direct_write_config
> > +};
> > +
> > +void tsi108_clear_pci_cfg_error(void)
> > +{
> > +	tsi108_clear_pci_error(MPC7448_HPC2_PCI_CFG_BASE_PHYS);
> > +}
> > +
> > +int __init add_bridge(struct device_node *dev)
> > +{
> > +	int len;
> > +	struct pci_controller *hose;
> > +	struct resource rsrc;
> > +	int *bus_range;
> > +	int primary = 0, has_address = 0;
> > +
> > +	DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
> > +	    tsi108_pci_cfg_base);
> > +
> > +	/* Fetch host bridge registers address */
> > +	has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
> > +
> > +	/* Get bus range if any */
> > +	bus_range = (int *)get_property(dev, "bus-range", &len);
> > +	if (bus_range == NULL || len < 2 * sizeof(int)) {
> > +		printk(KERN_WARNING "Can't get bus-range for %s, assume"
> > +		       " bus 0\n", dev->full_name);
> > +	}
> > +
> > +	hose = pcibios_alloc_controller();
> > +
> > +	if (!hose) {
> > +		printk("PCI Host bridge init failed\n");
> > +		return -ENOMEM;
> > +	}
> > +	hose->arch_data = dev;
> > +	hose->set_cfg_type = 1;
> > +
> > +	hose->first_busno = bus_range ? bus_range[0] : 0;
> > +	hose->last_busno = bus_range ? bus_range[1] : 0xff;
> > +
> > +	(hose)->ops = &direct_pci_ops;
> > +
> > +	printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08lx. "
> > +	       "Firmware bus number: %d->%d\n",
> > +	       rsrc.start, hose->first_busno, hose->last_busno);
> > +
> > +	/* Interpret the "ranges" property */
> > +	/* This also maps the I/O region and sets isa_io/mem_base */
> > +	pci_process_bridge_OF_ranges(hose, dev, primary);
> > +	return 0;
> > +
> > +}
> > +#endif
> > diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/ 
> > platforms/Makefile
> > index c4f6b0d..71ca0e0 100644
> > --- a/arch/powerpc/platforms/Makefile
> > +++ b/arch/powerpc/platforms/Makefile
> > @@ -9,6 +9,7 @@ obj-$(CONFIG_PPC_CHRP)		+= chrp/
> >  obj-$(CONFIG_4xx)		+= 4xx/
> >  obj-$(CONFIG_PPC_83xx)		+= 83xx/
> >  obj-$(CONFIG_PPC_85xx)		+= 85xx/
> > +obj-$(CONFIG_74xx)		+= 74xx/
> >  obj-$(CONFIG_PPC_PSERIES)	+= pseries/
> >  obj-$(CONFIG_PPC_ISERIES)	+= iseries/
> >  obj-$(CONFIG_PPC_MAPLE)		+= maple/
> > -- 
> > 1.3.0
> >
> >
> >
> >
> > _______________________________________________
> > Linuxppc-dev mailing list
> > Linuxppc-dev@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-dev
> 

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Zang Roy-r61911]

 
> On Wed, 2006-05-17 at 08:45 -0500, Kumar Gala wrote:
> 
> > > +#ifdef TSI108_ETH
> > > +hw_info hw_info_table[TSI108_ETH_MAX_PORTS + 1] = {
> > > +	{TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
> > > +	 TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
> > > +	 TSI108_PHY0_ADDR, IRQ_TSI108_GIGE0},
> > > +
> > > +	{TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET + 0x400,
> > > +	 TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
> > > +	 TSI108_PHY1_ADDR, IRQ_TSI108_GIGE1},
> > > +
> > > +	{TBL_END, TBL_END, TBL_END, TBL_END}
> > > +};
> > > +#endif
> > 
> > This table looks problematic.  Look at using something like a  
> > platform device.
> 
> Bzzzt ... wrong answer :) That's a textbook example of stuff 
> that should
> be provided via the device-tree.
> 
> 

Well , should I register this data to a platform device or the Ethernet 
driver get the information from device-tree directly?
Roy

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Benjamin Herrenschmidt]

> The tsi108 serial port is not a sub node of "soc".  well, any way,
> I can try soc!

What is it ? Where is it ? "soc" is a bit of a generic name for
something in the device-tree in fact... we might want to define a way to
expose any bus via some kind of soc mecanism even if it's not a root
bus.

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Zang Roy-r61911]

> I'm not repeating Kumar's comments about that CONFIG_7xxx 
> thing and that
> 7xxx/ directory, it should all go.
> 

Should I move my code to embedded6xx?

> Some more bits:
> 
> > +static u_char mpc7448_hpc2_pic_initsenses[] __initdata = {
> > +	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* 
> INT[0] XINT0 from FPGA */
> > +	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* 
> INT[1] XINT1 from FPGA */
> > +	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* 
> INT[2] PHY_INT from both GIGE */
> > +	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* 
> INT[3] RESERVED */
> > +};
> > +
> > +/*
> > + * mpc7448hpc2 PCI interrupt routing. all PCI interrupt comes from
> > + * external PCI source at 23. need to program pci 
> interrupt control registers
> > + * to route per slot IRQs.
> > + */
> > +
> > +static inline int
> > +mpc7448_hpc2_map_irq(struct pci_dev *dev, unsigned char idsel,
> > +		     unsigned char pin)
> > +{
> > +	static char pci_irq_table[][4] =
> > +	    /*
> > +	     *      PCI IDSEL/INTPIN->INTLINE
> > +	     *         A     B     C     D
> > +	     */
> > +	{
> > +		{IRQ_PCI_INTA, IRQ_PCI_INTB, IRQ_PCI_INTC, 
> IRQ_PCI_INTD},	/* A SLOT 1 IDSEL 17 */
> > +		{IRQ_PCI_INTB, IRQ_PCI_INTC, IRQ_PCI_INTD, 
> IRQ_PCI_INTA},	/* B SLOT 2 IDSEL 18 */
> > +		{IRQ_PCI_INTC, IRQ_PCI_INTD, IRQ_PCI_INTA, 
> IRQ_PCI_INTB},	/* C SATA IDSEL 19 */
> > +		{IRQ_PCI_INTD, IRQ_PCI_INTA, IRQ_PCI_INTB, 
> IRQ_PCI_INTC},	/* D USB IDSEL 20 */
> > +	};
> > +
> > +	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
> > +	return PCI_IRQ_TABLE_LOOKUP;
> > +}
> 
> This whole irq map stuff is excactly what the device-tree is 
> there for .
> Please implement proper interrupt maps in the device-tree and 
> get rid of
> those tables.

I will get rid of those tables.  I can see that in file
 arch/powerpc/platforms/85xx/mpc85xx_ads.c (2.6.17-rc4), there is
a similar table. Should it be removed in future :)?

> 
> > +static void __init mpc7448_hpc2_map_io(void)
> > +{
> > +	/* PCI IO  mapping */
> > +	io_block_mapping(MPC7448_HPC2_PCI_IO_BASE_VIRT,
> > +			 MPC7448_HPC2_PCI_IO_BASE_PHYS, 
> 0x00800000, _PAGE_IO);
> > +	/* Tsi108 CSR mapping */
> > +	io_block_mapping(TSI108_CSR_ADDR_VIRT, TSI108_CSR_ADDR_PHYS,
> > +			 0x100000, _PAGE_IO);
> > +
> > +	/* PCI Config mapping */
> > +	io_block_mapping(MPC7448_HPC2_PCI_CFG_BASE_VIRT,
> > +			 MPC7448_HPC2_PCI_CFG_BASE_PHYS,
> > +			 MPC7448_HPC2_PCI_CFG_SIZE, _PAGE_IO);
> > +
> > +	tsi108_pci_cfg_base = MPC7448_HPC2_PCI_CFG_BASE_VIRT;
> > +	/* NVRAM mapping */
> > +	io_block_mapping(MPC7448_HPC2_NVRAM_BASE_ADDR,
> > +			 MPC7448_HPC2_NVRAM_BASE_ADDR, 
> MPC7448_HPC2_NVRAM_SIZE,
> > +			 _PAGE_IO);
> > +}
> 
> io_block_mapping is bad ! see endless discussions in the archives of
> why ... Use ioremap.

OK!

> 
> > +static int __init mpc7448_hpc2_probe(void)
> > +{
> > +	/* We always match for now, eventually we should look 
> at the flat
> > +	   dev tree to ensure this is the board we are suppose to run on
> > +	 */
> > +	return 1;
> > +}
> 
> Yes, please do so, we will not accept a board that does the above :)

I just do the same thing as 85xx :).

> 
> > +extern int tsi108_direct_write_config(struct pci_bus *bus, 
> unsigned int devfn,
> > +				      int offset, int len, u32 val);
> > +extern int tsi108_direct_read_config(struct pci_bus *bus, 
> unsigned int devfn,
> > +				     int offset, int len, u32 * val);
> >
> > +void tsi108_clear_pci_error(u32 pci_cfg_base);
> > +
> > +extern int
> > +tsi108_read_config(int bus, unsigned int devfn, int 
> offset, int len, u32 * val);
> > +#ifdef CONFIG_PCI
> > +static struct pci_ops direct_pci_ops = {
> > +	tsi108_direct_read_config,
> > +	tsi108_direct_write_config
> > +};
> 
> That sounds bogus. You should instead have a tsi108_pci.c file that
> contains all of the functions _and_ the pci_ops structure 
> (with a better
> name please) and exports some kind of setup_tsi108_pci(device_node *).
> 

OK!

> > +void tsi108_clear_pci_cfg_error(void)
> > +{
> > +	tsi108_clear_pci_error(MPC7448_HPC2_PCI_CFG_BASE_PHYS);
> > +}
> > +
> > +int __init add_bridge(struct device_node *dev)
> > +{
> > +	int len;
> > +	struct pci_controller *hose;
> > +	struct resource rsrc;
> > +	int *bus_range;
> > +	int primary = 0, has_address = 0;
> > +
> > +	DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
> > +	    tsi108_pci_cfg_base);
> > +
> > +	/* Fetch host bridge registers address */
> > +	has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
> > +
> > +	/* Get bus range if any */
> > +	bus_range = (int *)get_property(dev, "bus-range", &len);
> > +	if (bus_range == NULL || len < 2 * sizeof(int)) {
> > +		printk(KERN_WARNING "Can't get bus-range for %s, assume"
> > +		       " bus 0\n", dev->full_name);
> > +	}
> > +
> > +	hose = pcibios_alloc_controller();
> > +
> > +	if (!hose) {
> > +		printk("PCI Host bridge init failed\n");
> > +		return -ENOMEM;
> > +	}
> > +	hose->arch_data = dev;
> > +	hose->set_cfg_type = 1;
> > +
> > +	hose->first_busno = bus_range ? bus_range[0] : 0;
> > +	hose->last_busno = bus_range ? bus_range[1] : 0xff;
> > +
> > +	(hose)->ops = &direct_pci_ops;
> > +
> > +	printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08lx. "
> > +	       "Firmware bus number: %d->%d\n",
> > +	       rsrc.start, hose->first_busno, hose->last_busno);
> > +
> > +	/* Interpret the "ranges" property */
> > +	/* This also maps the I/O region and sets isa_io/mem_base */
> > +	pci_process_bridge_OF_ranges(hose, dev, primary);
> > +	return 0;
> > +
> > +}
> 
> We need a generic add_bridge that goes through PCI bridges and
> instanciate based on their type as provided by the device-tree. You
> should try to work in that direction...
OK!

 
 

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Benjamin Herrenschmidt]

> Well , should I register this data to a platform device or the Ethernet 
> driver get the information from device-tree directly?

You probably want to define a bus structure (/soc might work even if
it's not strictly a /soc) or use of_platform device to link a
device-tree node to a driver instance. You can create as many nodes as
you have devices and provide all the additional infos you need including
interrupt routing via the device-tree.

Ben.

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Benjamin Herrenschmidt]

On Thu, 2006-05-18 at 15:12 +0800, Zang Roy-r61911 wrote:
> > I'm not repeating Kumar's comments about that CONFIG_7xxx 
> > thing and that
> > 7xxx/ directory, it should all go.
> > 
> 
> Should I move my code to embedded6xx?

Probably for now yes.

> I will get rid of those tables.  I can see that in file
>  arch/powerpc/platforms/85xx/mpc85xx_ads.c (2.6.17-rc4), there is
> a similar table. Should it be removed in future :)?

Yes. And somebody beaten up for letting that stuff leak into
arch/powerpc :)

> > Yes, please do so, we will not accept a board that does the above :)
> 
> I just do the same thing as 85xx :).

Yes and I intend to LART Kumar seriously for that next time I meet
him :)

> > We need a generic add_bridge that goes through PCI bridges and
> > instanciate based on their type as provided by the device-tree. You
> > should try to work in that direction...

I suggest you also read my comments to Mark A. Greer as most of that
stuff overlaps... I wish I had more times to work myself on that but I'm
fairly overflowed at the moment...

Ben

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Zang Roy-r61911]

> 
> > The tsi108 serial port is not a sub node of "soc".  well, any way,
> > I can try soc!
> 
> What is it ? Where is it ? "soc" is a bit of a generic name for
> something in the device-tree in fact... we might want to 
> define a way to
> expose any bus via some kind of soc mecanism even if it's not a root
> bus.
> 
> 
Should I just use add_legacy_soc_port() instead of a new function
add_legacy_tsi_port()?
--- arch/powerpc/kernel/legacy_serial.c.orig	Thu May 18 15:35:19 2006
+++ arch/powerpc/kernel/legacy_serial.c	Thu May 18 15:50:38 2006
@@ -302,6 +302,17 @@ void __init find_legacy_serial_ports(voi
 		of_node_put(isa);
 	}
 
+	/* First fill our array with tsi-bridge ports */
+	for (np = NULL; (np = of_find_compatible_node(np, "serial", "ns16550")) != NULL;) {
+		struct device_node *tsi = of_get_parent(np);
+		if (tsi && !strcmp(tsi->type, "tsi-bridge")) {
+			index = add_legacy_soc_port(np, np);
+			if (index >= 0 && np == stdout)
+				legacy_serial_console = index;
+		}
+		of_node_put(tsi);
+	}
+	
 #ifdef CONFIG_PCI
 	/* Next, try to locate PCI ports */
 	for (np = NULL; (np = of_find_all_nodes(np));) 

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Zang Roy-r61911]

 
> On Thu, 2006-05-18 at 15:12 +0800, Zang Roy-r61911 wrote:
> > > I'm not repeating Kumar's comments about that CONFIG_7xxx 
> > > thing and that
> > > 7xxx/ directory, it should all go.
> > > 
> > 
> > Should I move my code to embedded6xx?
> 
> Probably for now yes.

I can migrate my code to embedded6xx technically. In fact, 
I can move it into anywhere in the arch/powerpc/platforms. 
While for mpc7448hpc2(taiga) board, it is not a embedded 
application board. It is a high performance server! It seems
odd to put code there :). What's your opinion?

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Benjamin Herrenschmidt]

On Thu, 2006-05-18 at 18:21 +0800, Zang Roy-r61911 wrote:
>  > On Thu, 2006-05-18 at 15:12 +0800, Zang Roy-r61911 wrote:
> > > > I'm not repeating Kumar's comments about that CONFIG_7xxx 
> > > > thing and that
> > > > 7xxx/ directory, it should all go.
> > > > 
> > > 
> > > Should I move my code to embedded6xx?
> > 
> > Probably for now yes.
> 
> I can migrate my code to embedded6xx technically. In fact, 
> I can move it into anywhere in the arch/powerpc/platforms. 
> While for mpc7448hpc2(taiga) board, it is not a embedded 
> application board. It is a high performance server! It seems
> odd to put code there :). What's your opinion?

I think we should do a platform/generic for boards that don't need more
than a single platform file, which I think will be the case once we are
done with your port ;)

Ben.

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Paul Mackerras]

Zang Roy-r61911 writes:

> I can migrate my code to embedded6xx technically. In fact, 
> I can move it into anywhere in the arch/powerpc/platforms. 
> While for mpc7448hpc2(taiga) board, it is not a embedded 
> application board. It is a high performance server! It seems
> odd to put code there :). What's your opinion?

What sort of machine(s) is this board used in?  Or what machines will
it be in?

Paul.

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Zang Roy-r61911]

 
> On Thu, 2006-05-18 at 18:21 +0800, Zang Roy-r61911 wrote:
> >  > On Thu, 2006-05-18 at 15:12 +0800, Zang Roy-r61911 wrote:
> > > > > I'm not repeating Kumar's comments about that CONFIG_7xxx 
> > > > > thing and that
> > > > > 7xxx/ directory, it should all go.
> > > > > 
> > > > 
> > > > Should I move my code to embedded6xx?
> > > 
> > > Probably for now yes.
> > 
> > I can migrate my code to embedded6xx technically. In fact, 
> > I can move it into anywhere in the arch/powerpc/platforms. 
> > While for mpc7448hpc2(taiga) board, it is not a embedded 
> > application board. It is a high performance server! It seems
> > odd to put code there :). What's your opinion?
> 
> I think we should do a platform/generic for boards that don't 
> need more
> than a single platform file, which I think will be the case 
> once we are
> done with your port ;)
> 
> Ben.
> 
> 
I will implement my board port as early as I can  
according to the feedback :).

Re: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Kumar Gala]

On May 18, 2006, at 5:39 AM, Paul Mackerras wrote:

> Zang Roy-r61911 writes:
>
>> I can migrate my code to embedded6xx technically. In fact,
>> I can move it into anywhere in the arch/powerpc/platforms.
>> While for mpc7448hpc2(taiga) board, it is not a embedded
>> application board. It is a high performance server! It seems
>> odd to put code there :). What's your opinion?
>
> What sort of machine(s) is this board used in?  Or what machines will
> it be in?

Its a reference board from Freescale with a MPC7448 + TSI108.   
Similar in concept to sandpoint.

- kumar

Re: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Kumar Gala]

On May 18, 2006, at 5:21 AM, Zang Roy-r61911 wrote:

>
>> On Thu, 2006-05-18 at 15:12 +0800, Zang Roy-r61911 wrote:
>>>> I'm not repeating Kumar's comments about that CONFIG_7xxx
>>>> thing and that
>>>> 7xxx/ directory, it should all go.
>>>>
>>>
>>> Should I move my code to embedded6xx?
>>
>> Probably for now yes.
>
> I can migrate my code to embedded6xx technically. In fact,
> I can move it into anywhere in the arch/powerpc/platforms.
> While for mpc7448hpc2(taiga) board, it is not a embedded
> application board. It is a high performance server! It seems
> odd to put code there :). What's your opinion?

We should rename the files so they are 7448 specific.  I dont see any  
reason if FSL comes up with a 7449 that it wouldn't run on the same  
board.

- k

Re: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Kumar Gala]

On May 18, 2006, at 3:05 AM, Zang Roy-r61911 wrote:

>>
>>> The tsi108 serial port is not a sub node of "soc".  well, any way,
>>> I can try soc!
>>
>> What is it ? Where is it ? "soc" is a bit of a generic name for
>> something in the device-tree in fact... we might want to
>> define a way to
>> expose any bus via some kind of soc mecanism even if it's not a root
>> bus.
>>
>>
> Should I just use add_legacy_soc_port() instead of a new function
> add_legacy_tsi_port()?

I think seeing your dts will help here.  We need to have a concept of  
a "bridge" that may be similar to an "soc".

> --- arch/powerpc/kernel/legacy_serial.c.orig	Thu May 18 15:35:19 2006
> +++ arch/powerpc/kernel/legacy_serial.c	Thu May 18 15:50:38 2006
> @@ -302,6 +302,17 @@ void __init find_legacy_serial_ports(voi
>  		of_node_put(isa);
>  	}
>
> +	/* First fill our array with tsi-bridge ports */
> +	for (np = NULL; (np = of_find_compatible_node(np, "serial",  
> "ns16550")) != NULL;) {
> +		struct device_node *tsi = of_get_parent(np);
> +		if (tsi && !strcmp(tsi->type, "tsi-bridge")) {
> +			index = add_legacy_soc_port(np, np);
> +			if (index >= 0 && np == stdout)
> +				legacy_serial_console = index;
> +		}
> +		of_node_put(tsi);
> +	}
> +	
>  #ifdef CONFIG_PCI
>  	/* Next, try to locate PCI ports */
>  	for (np = NULL; (np = of_find_all_nodes(np));)

Re: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Kumar Gala]

>> I will get rid of those tables.  I can see that in file
>>  arch/powerpc/platforms/85xx/mpc85xx_ads.c (2.6.17-rc4), there is
>> a similar table. Should it be removed in future :)?
>
> Yes. And somebody beaten up for letting that stuff leak into
> arch/powerpc :)
>
>>> Yes, please do so, we will not accept a board that does the above :)
>>
>> I just do the same thing as 85xx :).
>
> Yes and I intend to LART Kumar seriously for that next time I meet
> him :)

Get in line ;) [lets be fair, I didn't actually do the 85xx/ads.c  
port, but it was based on the 83xx which I did do]

The problem with the irq mapping is we dont have any code yet that  
handles the "static" tables.

>>> We need a generic add_bridge that goes through PCI bridges and
>>> instanciate based on their type as provided by the device-tree. You
>>> should try to work in that direction...
>
> I suggest you also read my comments to Mark A. Greer as most of that
> stuff overlaps... I wish I had more times to work myself on that  
> but I'm
> fairly overflowed at the moment...
>
> Ben
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev

Re: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Kumar Gala]

On May 18, 2006, at 1:57 AM, Zang Roy-r61911 wrote:

>
>> On Wed, 2006-05-17 at 08:45 -0500, Kumar Gala wrote:
>>
>>>> +#ifdef TSI108_ETH
>>>> +hw_info hw_info_table[TSI108_ETH_MAX_PORTS + 1] = {
>>>> +	{TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
>>>> +	 TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
>>>> +	 TSI108_PHY0_ADDR, IRQ_TSI108_GIGE0},
>>>> +
>>>> +	{TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET + 0x400,
>>>> +	 TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
>>>> +	 TSI108_PHY1_ADDR, IRQ_TSI108_GIGE1},
>>>> +
>>>> +	{TBL_END, TBL_END, TBL_END, TBL_END}
>>>> +};
>>>> +#endif
>>>
>>> This table looks problematic.  Look at using something like a
>>> platform device.
>>
>> Bzzzt ... wrong answer :) That's a textbook example of stuff
>> that should
>> be provided via the device-tree.
>>
>>
>
> Well , should I register this data to a platform device or the  
> Ethernet
> driver get the information from device-tree directly?

I'd say the later.  Ben mentioned use of of_device which will allow  
you to do that more directly.  I used platform_device to maintain the  
fact that we had existing drivers to support that were using it already.

- k

Re: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Andy Fleming]

On May 18, 2006, at 02:22, Benjamin Herrenschmidt wrote:

> On Thu, 2006-05-18 at 15:12 +0800, Zang Roy-r61911 wrote:
>>> I'm not repeating Kumar's comments about that CONFIG_7xxx
>>> thing and that
>>> 7xxx/ directory, it should all go.
>>>
>>
>> Should I move my code to embedded6xx?
>
> Probably for now yes.
>
>> I will get rid of those tables.  I can see that in file
>>  arch/powerpc/platforms/85xx/mpc85xx_ads.c (2.6.17-rc4), there is
>> a similar table. Should it be removed in future :)?
>
> Yes. And somebody beaten up for letting that stuff leak into
> arch/powerpc :)
>
>>> Yes, please do so, we will not accept a board that does the above :)
>>
>> I just do the same thing as 85xx :).
>
> Yes and I intend to LART Kumar seriously for that next time I meet
> him :)


So some of this needs to be moved into u-boot (look at my patches to  
u-boot for the 85xx CDS support, and support in the current  
powerpc.git tree).  A lot of the PCI initialization is now there.   
However, the interrupt maps, while properly setup in the current 85xx  
u-boot oftree.dts files, is currently meaningless.  I may be wrong,  
but I thought support for getting the map from the flat-dev tree was  
still pending....

Re: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Benjamin Herrenschmidt]

On Thu, 2006-05-18 at 11:41 -0500, Kumar Gala wrote:
> >> I will get rid of those tables.  I can see that in file
> >>  arch/powerpc/platforms/85xx/mpc85xx_ads.c (2.6.17-rc4), there is
> >> a similar table. Should it be removed in future :)?
> >
> > Yes. And somebody beaten up for letting that stuff leak into
> > arch/powerpc :)
> >
> >>> Yes, please do so, we will not accept a board that does the above :)
> >>
> >> I just do the same thing as 85xx :).
> >
> > Yes and I intend to LART Kumar seriously for that next time I meet
> > him :)
> 
> Get in line ;) [lets be fair, I didn't actually do the 85xx/ads.c  
> port, but it was based on the 83xx which I did do]
> 
> The problem with the irq mapping is we dont have any code yet that  
> handles the "static" tables.

We do, though right now it doesn't do much good if you don't have device
nodes for PCI devices indeed :) Fix real soon now !

Ben.

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Zang Roy-r61911]

> Zang Roy-r61911 writes:
> 
> > I can migrate my code to embedded6xx technically. In fact, 
> > I can move it into anywhere in the arch/powerpc/platforms. 
> > While for mpc7448hpc2(taiga) board, it is not a embedded 
> > application board. It is a high performance server! It seems
> > odd to put code there :). What's your opinion?
> 
> What sort of machine(s) is this board used in?  Or what machines will
> it be in?
> 
> Paul.
> 
mpc7448hpc2 (taiga) board is a high-performance PowerPC 
server reference design,which is optimized for high speed throughput
between the processor (mpc7448 or 7447A) and the memory, disk drive 
and Ethernet port subsystems.

mpc7448hpc2 (taiga) is designed to the micro-ATX chassis, 
allowing it to be used in 1U or 2U rack-mount chassis' , as well as 
in standard ATX/Micro-ATX chassis.

Roy

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Zang Roy-r61911]

> On May 18, 2006, at 3:05 AM, Zang Roy-r61911 wrote:
> 
> >>
> >>> The tsi108 serial port is not a sub node of "soc".  well, 
> any way, I 
> >>> can try soc!
> >>
> >> What is it ? Where is it ? "soc" is a bit of a generic name for 
> >> something in the device-tree in fact... we might want to 
> define a way 
> >> to expose any bus via some kind of soc mecanism even if it's not a 
> >> root bus.
> >>
> >>
> > Should I just use add_legacy_soc_port() instead of a new function 
> > add_legacy_tsi_port()?
> 
> I think seeing your dts will help here.  We need to have a 
> concept of a "bridge" that may be similar to an "soc".
mpc7448hpc2 dts :
/*
 * MPC7448HPC2 (Taiga) board Device Tree Source
 *
 * Copyright 2006 Freescale Semiconductor Inc.
 * 2006 Roy Zang <Roy Zang at freescale.com>.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */


/ {
	model = "mpc7448hpc2";
	compatible = "mpc74xx";
	#address-cells = <1>;
	#size-cells = <1>;
	linux,phandle = <100>;

	cpus {
		#cpus = <1>;
		#address-cells = <1>;
		#size-cells =<0>;
		linux,phandle = <200>;
				
		PowerPC,7448@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <20>;	// 32 bytes
			i-cache-line-size = <20>;	// 32 bytes
			d-cache-size = <8000>;		// L1, 32K bytes
			i-cache-size = <8000>;		// L1, 32K bytes
			timebase-frequency = <0>;	// 33 MHz, from uboot
			clock-frequency = <0>;		// From U-Boot
			bus-frequency = <0>;		// From U-Boot
			32-bit;
			linux,phandle = <201>;
			linux,boot-cpu;
		};
	};

	memory {
		device_type = "memory";
		linux,phandle = <300>;
		reg = <00000000 20000000	// DDR2   512M at 0
		       >;
	};

  	tsi108@c0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <2>;
		device_type = "tsi-bridge";
		ranges = <00000000 c0000000 00010000>;
		reg = <c0000000 00010000>;
		bus-frequency = <0>;

		i2c@7000 {
			interrupt-parent = <7400>;
			interrupts = <E 3>;
			reg = <7000 400>;
			device_type = "i2c";
			compatible  = "tsi-i2c";
		};

		mdio@6000 {
			device_type = "mdio";
			compatible = "tsi-ethernet";	// FIXME

			ethernet-phy@6000 {
				linux,phandle = <6000>;
				interrupt-parent = <7400>;
				interrupts = <2 1>;
				reg = <6000 50>;
				device_type = "ethernet-phy";
			};

			ethernet-phy@6400 {
				linux,phandle = <6400>;
				interrupt-parent = <7400>;
				interrupts = <2 1>;
				reg = <6400 50>;
				device_type = "ethernet-phy";
			};

		};

		ethernet@6200 {
			#size-cells = <0>;
			device_type = "network";
			model = "TSI-ETH";		// FIXME
			compatible = "tsi-ethernet";	// FIXME
			reg = <6200 200>;
			address = [ 00 06 D2 00 00 01 ];
			interrupts = <10 3 10 3 10 3>;
			interrupt-parent = <7400>;
			phy-handle = <6000>;
		};

		ethernet@6600 {
			#address-cells = <1>;
			#size-cells = <0>;
			device_type = "network";
			model = "TSI-ETH";		// FIXME
			compatible = "tsi-ethernet";	// FIXME
			reg = <6600 200>;
			address = [ 00 06 D2 00 00 02 ];
			interrupts = <11 3 11 3 11 3>;
			interrupt-parent = <7400>;
			phy-handle = <6400>;
		};

		serial@7808 {
			device_type = "serial";
			compatible = "ns16550";
			reg = <7808 200>;
			clock-frequency = <3f6b5a00>;
			interrupts = <c 3>;
			interrupt-parent = <7400>;
		};

		serial@7c08 {
			device_type = "serial";
			compatible = "ns16550";
			reg = <7c08 200>;
			clock-frequency = <3f6b5a00>;
			interrupts = <d 3>;
			interrupt-parent = <7400>;
		};

	  	pic@7400 {
			linux,phandle = <7400>;
			clock-frequency = <0>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <7400 400>;
			built-in;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
                       	big-endian;
		};
		pci@1000 {
			compatible = "tsi10x";
			device_type = "pci";
			linux,phandle = <1000>;
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = <1000 1000>;
			bus-range = <0 0>;
			ranges = <02000000 0 e0000000 e0000000 0 1A000000	
				  01000000 0 00000000 fa000000 0 00010000>;
			clock-frequency = <7f28154>;
			interrupt-parent = <7400>;
			interrupts = <8 0>;
			interrupt-map-mask = <f800 0 0 7>;
			interrupt-map = <

				/* IDSEL 0x11 */
				8800 0 0 1 7400 24 0
				8800 0 0 2 7400 25 0
				8800 0 0 3 7400 26 0
				8800 0 0 4 7400 27 0

				/* IDSEL 0x12 */
				9000 0 0 1 7400 25 0
				9000 0 0 2 7400 26 0
				9000 0 0 3 7400 27 0
				9000 0 0 4 7400 24 0

				/* IDSEL 0x13 */
				9800 0 0 1 7400 26 0
				9800 0 0 2 7400 27 0
				9800 0 0 3 7400 24 0
				9800 0 0 4 7400 25 0

				/* IDSEL 0x14 */
				a000 0 0 1 7400 27 0
				a000 0 0 2 7400 24 0
				a000 0 0 3 7400 25 0
				a000 0 0 4 7400 26 0
				>;
		};
	};

};

 

Re: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Benjamin Herrenschmidt]

On Thu, 2006-05-18 at 15:49 -0500, Andy Fleming wrote:
> 
> 
> So some of this needs to be moved into u-boot (look at my patches to  
> u-boot for the 85xx CDS support, and support in the current  
> powerpc.git tree).  A lot of the PCI initialization is now there.   
> However, the interrupt maps, while properly setup in the current
> 85xx  
> u-boot oftree.dts files, is currently meaningless.  I may be wrong,  
> but I thought support for getting the map from the flat-dev tree was  
> still pending....

Well, the kernel does get the map from the tree but can't use it if the
device itself doesn't have a device-node. I'll fix that for 2.6.18
hopefully.

Ben.

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Zang Roy-r61911]

> 
> On Thu, 2006-05-18 at 15:49 -0500, Andy Fleming wrote:
> > 
> > 
> > So some of this needs to be moved into u-boot (look at my 
> patches to 
> > u-boot for the 85xx CDS support, and support in the current
> > powerpc.git tree).  A lot of the PCI initialization is now there.   
> > However, the interrupt maps, while properly setup in the 
> current 85xx 
> > u-boot oftree.dts files, is currently meaningless.  I may be wrong, 
> > but I thought support for getting the map from the flat-dev 
> tree was 
> > still pending....
> 
> Well, the kernel does get the map from the tree but can't use 
> it if the device itself doesn't have a device-node. I'll fix 
> that for 2.6.18 hopefully.
> 
> Ben.
> 

What should  we do? 
Can we  keep the map table unitl your code 
is OK?

Roy
 

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Benjamin Herrenschmidt]

> What should  we do? 
> Can we  keep the map table unitl your code 
> is OK?

Or you could have your platform-specific fixup_irq walk the
interrupt-map property in the tree, still better than a table and allows
you to validate the tree. When my code is fixed, you can then just
remove your fixup.

Ben.

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Zang Roy-r61911]

> > +static void __init mpc7448_hpc2_map_io(void) {
> > +	/* PCI IO  mapping */
> > +	io_block_mapping(MPC7448_HPC2_PCI_IO_BASE_VIRT,
> > +			 MPC7448_HPC2_PCI_IO_BASE_PHYS, 
> 0x00800000, _PAGE_IO);
> > +	/* Tsi108 CSR mapping */
> > +	io_block_mapping(TSI108_CSR_ADDR_VIRT, TSI108_CSR_ADDR_PHYS,
> > +			 0x100000, _PAGE_IO);
> > +
> > +	/* PCI Config mapping */
> > +	io_block_mapping(MPC7448_HPC2_PCI_CFG_BASE_VIRT,
> > +			 MPC7448_HPC2_PCI_CFG_BASE_PHYS,
> > +			 MPC7448_HPC2_PCI_CFG_SIZE, _PAGE_IO);
> > +
> > +	tsi108_pci_cfg_base = MPC7448_HPC2_PCI_CFG_BASE_VIRT;
> > +	/* NVRAM mapping */
> > +	io_block_mapping(MPC7448_HPC2_NVRAM_BASE_ADDR,
> > +			 MPC7448_HPC2_NVRAM_BASE_ADDR, 
> MPC7448_HPC2_NVRAM_SIZE,
> > +			 _PAGE_IO);
> > +}
> 
> io_block_mapping is bad ! see endless discussions in the 
> archives of why ... Use ioremap.

If I really need to use bat0 or bat1( I see that the general mmu use bat2 and bat3, 
where should I set up them?

For tsi108 pci configuration access, I need to map 16Mbyte 
physical address.  If I do not use an extra bat, I can not get the correct 
virtual address use ioremap.

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Benjamin Herrenschmidt]

> If I really need to use bat0 or bat1( I see that the general mmu use bat2 and bat3, 
> where should I set up them?
> 
> For tsi108 pci configuration access, I need to map 16Mbyte 
> physical address.  If I do not use an extra bat, I can not get the correct 
> virtual address use ioremap.

What do you mean ? An ioremap will work, it will give you any virtual
address, you just have to store that in a global instead of hard coding
it. Hard coded virtual addresses are bad. Especially for things like PCI
config space that really isn't performance sensitive.

Ben.

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Liu Dave-r63238]

> > If I really need to use bat0 or bat1( I see that the 
> general mmu use 
> > bat2 and bat3,
> > where should I set up them?
> > 
> > For tsi108 pci configuration access, I need to map 16Mbyte
> > physical address.  If I do not use an extra bat, I can not 
> get the correct 
> > virtual address use ioremap.
> 
> What do you mean ? An ioremap will work, it will give you any 
> virtual address, you just have to store that in a global 
> instead of hard coding it. Hard coded virtual addresses are 
> bad. Especially for things like PCI config space that really 
> isn't performance sensitive.
> 

I agree ben about PCI config space, It should use ioremap
 to get virtual address. No performace indeed. 

I think we need find the root cause that the ioremap failed.

Dave

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Zang Roy-r61911]

> 
> > If I really need to use bat0 or bat1( I see that the 
> general mmu use 
> > bat2 and bat3, where should I set up them?
> > 
> > For tsi108 pci configuration access, I need to map 16Mbyte physical 
> > address.  If I do not use an extra bat, I can not get the correct 
> > virtual address use ioremap.
> 
> What do you mean ? An ioremap will work, it will give you any 
> virtual address, you just have to store that in a global 
> instead of hard coding it. Hard coded virtual addresses are 
> bad. Especially for things like PCI config space that really 
> isn't performance sensitive.
> 
> Ben.
> 
>
 

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Zang Roy-r61911]

> > If I really need to use bat0 or bat1( I see that the 
> general mmu use 
> > bat2 and bat3, where should I set up them?
> > 
> > For tsi108 pci configuration access, I need to map 16Mbyte physical 
> > address.  If I do not use an extra bat, I can not get the correct 
> > virtual address use ioremap.
> 
> What do you mean ? An ioremap will work, it will give you any 
> virtual address, you just have to store that in a global 
> instead of hard coding it. Hard coded virtual addresses are 
> bad. Especially for things like PCI config space that really 
> isn't performance sensitive.
> 
> Ben.
> 

I had hoped to get the pci configure base address by ioremap, but failed.
the tsi108 register locates at 0xc000,0000 ~0xC001,0000. It is OK to 
access them by ioremap. While pci configure access need to ioremap 
0xfb00,0000 ~0xfc00,0000. 
I traced my code, when I do ioremap, there is no bat match, I get the virtual
address from ioremap_bot. the init ioremap_bot is 0xfe000000. When I do
tsi108_csr_vir_base = ioremap(0xfb000000,0x1000000), 
the ioremap_bot is 0xfdffe000 ( I get the serial port ioremap steal some space), 
tsi108_csr_vir_base = 0xfdfee000, I can not access the configure space with this
address.
While if I use bat0 or bat1 to map my tsi108 register space, the ioremap_bot will keep
to 0xfe000000 until I do 
tsi108_csr_vir_base = ioremap(0xfb000000,0x1000000)
then I get  tsi108_csr_vir_base = 0xfd000000. Everything is OK.

Roy

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Benjamin Herrenschmidt]

On Fri, 2006-06-02 at 15:38 +0800, Liu Dave-r63238 wrote:
> > > If I really need to use bat0 or bat1( I see that the 
> > general mmu use 
> > > bat2 and bat3,
> > > where should I set up them?
> > > 
> > > For tsi108 pci configuration access, I need to map 16Mbyte
> > > physical address.  If I do not use an extra bat, I can not 
> > get the correct 
> > > virtual address use ioremap.
> > 
> > What do you mean ? An ioremap will work, it will give you any 
> > virtual address, you just have to store that in a global 
> > instead of hard coding it. Hard coded virtual addresses are 
> > bad. Especially for things like PCI config space that really 
> > isn't performance sensitive.
> > 
> 
> I agree ben about PCI config space, It should use ioremap
>  to get virtual address. No performace indeed. 
> 
> I think we need find the root cause that the ioremap failed.

How much RAM do you have ? Maybe you are running out of virtual space ?

Ben.

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Benjamin Herrenschmidt]

On Fri, 2006-06-02 at 16:05 +0800, Zang Roy-r61911 wrote:
> > > If I really need to use bat0 or bat1( I see that the 
> > general mmu use 
> > > bat2 and bat3, where should I set up them?
> > > 
> > > For tsi108 pci configuration access, I need to map 16Mbyte physical 
> > > address.  If I do not use an extra bat, I can not get the correct 
> > > virtual address use ioremap.
> > 
> > What do you mean ? An ioremap will work, it will give you any 
> > virtual address, you just have to store that in a global 
> > instead of hard coding it. Hard coded virtual addresses are 
> > bad. Especially for things like PCI config space that really 
> > isn't performance sensitive.
> > 
> > Ben.
> > 
> 
> I had hoped to get the pci configure base address by ioremap, but failed.
> the tsi108 register locates at 0xc000,0000 ~0xC001,0000. It is OK to 
> access them by ioremap. While pci configure access need to ioremap 
> 0xfb00,0000 ~0xfc00,0000. 
> I traced my code, when I do ioremap, there is no bat match, I get the virtual
> address from ioremap_bot. the init ioremap_bot is 0xfe000000. When I do
> tsi108_csr_vir_base = ioremap(0xfb000000,0x1000000), 
> the ioremap_bot is 0xfdffe000 ( I get the serial port ioremap steal some space), 
> tsi108_csr_vir_base = 0xfdfee000, I can not access the configure space with this
> address.

What happens if you try ?

> While if I use bat0 or bat1 to map my tsi108 register space, the ioremap_bot will keep
> to 0xfe000000 until I do 
> tsi108_csr_vir_base = ioremap(0xfb000000,0x1000000)
> then I get  tsi108_csr_vir_base = 0xfd000000. Everything is OK.

Both should work fine

Ben.

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Zang Roy-r61911]

> How much RAM do you have ? Maybe you are running out of 
> virtual space ?
> 
> Ben.
> 
> 

512MBytes

Roy

RE: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Liu Dave-r63238]

> > I had hoped to get the pci configure base address by ioremap, but 
> > failed. the tsi108 register locates at 0xc000,0000 
> ~0xC001,0000. It is 
> > OK to access them by ioremap. While pci configure access need to 
> > ioremap 0xfb00,0000 ~0xfc00,0000. I traced my code, when I 
> do ioremap, 
> > there is no bat match, I get the virtual address from 
> ioremap_bot. the 
> > init ioremap_bot is 0xfe000000. When I do tsi108_csr_vir_base = 
> > ioremap(0xfb000000,0x1000000), the ioremap_bot is 
> 0xfdffe000 ( I get 
> > the serial port ioremap steal some space), tsi108_csr_vir_base = 
> > 0xfdfee000, I can not access the configure space with this address.
> 
> What happens if you try ?
> 
> > While if I use bat0 or bat1 to map my tsi108 register space, the 
> > ioremap_bot will keep to 0xfe000000 until I do 
> tsi108_csr_vir_base = 
> > ioremap(0xfb000000,0x1000000) then I get  tsi108_csr_vir_base = 
> > 0xfd000000. Everything is OK.
> 
> Both should work fine
> 
> Ben.
> 

The smallest BAT size of 74xx is 128KB, but the MPC7448_HPC2_NVRAM_SIZE
Is 0x8000 (32KB) you set in your code. I suggest you set the
MPC7448_HPC2_NVRAM_SIZE is 0x20000, try it.

Dave

Re: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Kumar Gala]

On Jun 2, 2006, at 3:20 AM, Zang Roy-r61911 wrote:

>
>> How much RAM do you have ? Maybe you are running out of
>> virtual space ?
>>
>> Ben.
>>
>>
>
> 512MBytes

If I understand things, there is a 16M region for PCI config space.   
You could look at just doing the ioremap for each chunk when its  
needed via the low level calls.

- kumar

Re: [PATCH/2.6.17-rc4 1/10] Powerpc: Add general support for mpc7 448h pc2 (Taiga) platform

[Benjamin Herrenschmidt]

On Fri, 2006-06-02 at 09:50 -0500, Kumar Gala wrote:
> On Jun 2, 2006, at 3:20 AM, Zang Roy-r61911 wrote:
> 
> >
> >> How much RAM do you have ? Maybe you are running out of
> >> virtual space ?
> >>
> >> Ben.
> >>
> >>
> >
> > 512MBytes
> 
> If I understand things, there is a 16M region for PCI config space.   
> You could look at just doing the ioremap for each chunk when its  
> needed via the low level calls.

PCI config access is called with locks held, it can't ioremap.

Ben.