From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id 9DFC8679FF for ; Thu, 22 Jun 2006 22:09:57 +1000 (EST) Subject: Re: [PATCH] Don't access HID registers if running on a Hypervisor. From: Benjamin Herrenschmidt To: Jimi Xenidis In-Reply-To: <6BBF4F7C-1375-41FF-8D42-43BEC67194CC@watson.ibm.com> References: <20060621235156.GA5414@pb15.lixom.net> <6BBF4F7C-1375-41FF-8D42-43BEC67194CC@watson.ibm.com> Content-Type: text/plain Date: Thu, 22 Jun 2006 22:09:43 +1000 Message-Id: <1150978183.3633.49.camel@localhost.localdomain> Mime-Version: 1.0 Cc: Olof Johansson , linuxppc-dev@ozlabs.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Thu, 2006-06-22 at 06:58 -0400, Jimi Xenidis wrote: > 970s consider this a no-op (I believe an expensive one) especially > when you consider some of the synchronization issues around the mtspr > HIDx. > And though this is 970 specific code, Cell and future processors, > will no longer allow writing to to these registers if !(MSR[0]=1 && > MSR[PR]=0) Fair enough, let's fix it. Ben.