# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.1.02 Build EDK_I.20.4
# Fri Nov 24 09:51:11 2006
# Target Board:  Memec Virtex-4 FX12 LC Development Board Rev 1
# Family:	 virtex4
# Device:	 XC4VFX12
# Package:	 FF668
# Speed Grade:	 -10
# Processor: PPC 405
# Processor clock frequency: 100.000000 MHz
# Bus clock frequency: 100.000000 MHz
# Debug interface: FPGA JTAG
# On Chip Memory :  32 KB
# Total Off Chip Memory :  68 MB
# - FLASH2Mx16 =   4 MB
# - DDR_SDRAM_32Mx16 =  64 MB
# ##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_sin_pin = fpga_0_RS232_sin, DIR = I
 PORT fpga_0_RS232_sout_pin = fpga_0_RS232_sout, DIR = O
 PORT fpga_0_RS232_rtsN_pin = fpga_0_RS232_rtsN, DIR = O
 PORT fpga_0_LEDs_4Bit_GPIO_d_out_pin = fpga_0_LEDs_4Bit_GPIO_d_out, DIR = O, VEC = [0:3]
 PORT fpga_0_Push_Buttons_3Bit_GPIO_in_pin = fpga_0_Push_Buttons_3Bit_GPIO_in, DIR = I, VEC = [0:2]
 PORT fpga_0_DIP_Switches_8Bit_GPIO_in_pin = fpga_0_DIP_Switches_8Bit_GPIO_in, DIR = I, VEC = [0:7]
 PORT fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_Clk, DIR = O
 PORT fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn, DIR = O
 PORT fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_Addr, DIR = O, VEC = [0:12]
 PORT fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr, DIR = O, VEC = [0:1]
 PORT fpga_0_DDR_SDRAM_32Mx16_DDR_CASn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_CASn, DIR = O
 PORT fpga_0_DDR_SDRAM_32Mx16_DDR_CKE_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_CKE, DIR = O
 PORT fpga_0_DDR_SDRAM_32Mx16_DDR_CSn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_CSn, DIR = O
 PORT fpga_0_DDR_SDRAM_32Mx16_DDR_RASn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_RASn, DIR = O
 PORT fpga_0_DDR_SDRAM_32Mx16_DDR_WEn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_WEn, DIR = O
 PORT fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_DM, DIR = O, VEC = [0:1]
 PORT fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_DQS, DIR = IO, VEC = [0:1]
 PORT fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_DQ, DIR = IO, VEC = [0:15]
 PORT fpga_0_FLASH_2Mx16_Mem_A_pin = fpga_0_FLASH_2Mx16_Mem_A, DIR = O, VEC = [10:30]
 PORT fpga_0_FLASH_2Mx16_Mem_DQ_pin = fpga_0_FLASH_2Mx16_Mem_DQ, DIR = IO, VEC = [0:15]
 PORT fpga_0_FLASH_2Mx16_Mem_OEN_pin = fpga_0_FLASH_2Mx16_Mem_OEN, DIR = O, VEC = [0:0]
 PORT fpga_0_Flash_And_Gate_Res_pin = fpga_0_Flash_And_Gate_Res, DIR = O
 PORT fpga_0_FLASH_2Mx16_Mem_WEN_pin = fpga_0_FLASH_2Mx16_Mem_WEN, DIR = O
 PORT fpga_0_FLASH_2Mx16_vpp_dummy_pin = net_vcc, DIR = O
 PORT fpga_0_FLASH_2Mx16_Mem_RPN_pin = fpga_0_FLASH_2Mx16_Mem_RPN, DIR = O
 PORT fpga_0_FLASH_READY_GPIO_in_pin = fpga_0_FLASH_READY_GPIO_in, DIR = I, VEC = [0:0]
 PORT fpga_0_Ethernet_MAC_PHY_tx_er_pin = fpga_0_Ethernet_MAC_PHY_tx_er, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_Mii_clk_pin = fpga_0_Ethernet_MAC_PHY_Mii_clk, DIR = IO
 PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_Mii_data_pin = fpga_0_Ethernet_MAC_PHY_Mii_data, DIR = IO
 PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = DCMCLK
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = DCMCLK
 PORT sys_rst_pin = sys_rst_s, DIR = I


BEGIN ppc405_virtex4
 PARAMETER INSTANCE = ppc405_0
 PARAMETER HW_VER = 1.01.a
 BUS_INTERFACE JTAGPPC = jtagppc_0_0
 BUS_INTERFACE IPLB = plb
 BUS_INTERFACE DPLB = plb
 PORT PLBCLK = sys_clk_s
 PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
 PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
 PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
 PORT RSTC405RESETCHIP = RSTC405RESETCHIP
 PORT RSTC405RESETCORE = RSTC405RESETCORE
 PORT RSTC405RESETSYS = RSTC405RESETSYS
 PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
 PORT CPMC405CLOCK = sys_clk_s
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_0
 PARAMETER HW_VER = 2.00.a
 BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = reset_block
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT Ext_Reset_In = sys_rst_s
 PORT Slowest_sync_clk = sys_clk_s
 PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
 PORT Core_Reset_Req = C405RSTCORERESETREQ
 PORT System_Reset_Req = C405RSTSYSRESETREQ
 PORT Rstc405resetchip = RSTC405RESETCHIP
 PORT Rstc405resetcore = RSTC405RESETCORE
 PORT Rstc405resetsys = RSTC405RESETSYS
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Dcm_locked = dcm_1_lock
END

BEGIN plb_v34
 PARAMETER INSTANCE = plb
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_bus_reset
 PORT PLB_Clk = sys_clk_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_bus_reset
 PORT OPB_Clk = sys_clk_s
END

BEGIN plb2opb_bridge
 PARAMETER INSTANCE = plb2opb
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_NUM_ADDR_RNG = 1
 PARAMETER C_RNG0_BASEADDR = 0x00000000
 PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE MOPB = opb
 PORT PLB_Clk = sys_clk_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_uart16550
 PARAMETER INSTANCE = RS232
 PARAMETER HW_VER = 1.00.d
 PARAMETER C_IS_A_16550 = 0
 PARAMETER C_BASEADDR = 0x40400000
 PARAMETER C_HIGHADDR = 0x4040ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_s
 PORT IP2INTC_Irpt = RS232_IP2INTC_Irpt
 PORT sin = fpga_0_RS232_sin
 PORT sout = fpga_0_RS232_sout
 PORT rtsN = fpga_0_RS232_rtsN
END

BEGIN plb_ethernet
 PARAMETER INSTANCE = Ethernet_MAC
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_DMA_PRESENT = 1
 PARAMETER C_IPIF_FIFO_DEPTH = 32768
 PARAMETER C_PLB_CLK_PERIOD_PS = 10000
 PARAMETER C_BASEADDR = 0x80400000
 PARAMETER C_HIGHADDR = 0x8040ffff
 BUS_INTERFACE SPLB = plb
 PORT PLB_Clk = sys_clk_s
 PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
 PORT PHY_tx_er = fpga_0_Ethernet_MAC_PHY_tx_er
 PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
 PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
 PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
 PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
 PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
 PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
 PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
 PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
 PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
 PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk
 PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
 PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_4Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_s
 PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt
 PORT GPIO_d_out = fpga_0_LEDs_4Bit_GPIO_d_out
END

BEGIN opb_gpio
 PARAMETER INSTANCE = Push_Buttons_3Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 3
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x40020000
 PARAMETER C_HIGHADDR = 0x4002ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_s
 PORT IP2INTC_Irpt = Push_Buttons_3Bit_IP2INTC_Irpt
 PORT GPIO_in = fpga_0_Push_Buttons_3Bit_GPIO_in
END

BEGIN opb_gpio
 PARAMETER INSTANCE = DIP_Switches_8Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x40040000
 PARAMETER C_HIGHADDR = 0x4004ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_s
 PORT IP2INTC_Irpt = DIP_Switches_8Bit_IP2INTC_Irpt
 PORT GPIO_in = fpga_0_DIP_Switches_8Bit_GPIO_in
END

BEGIN opb_gpio
 PARAMETER INSTANCE = FLASH_READY
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 1
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_BASEADDR = 0x40060000
 PARAMETER C_HIGHADDR = 0x4006ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_s
 PORT IP2INTC_Irpt = FLASH_READY_IP2INTC_Irpt
 PORT GPIO_in = fpga_0_FLASH_READY_GPIO_in
END

BEGIN plb_emc
 PARAMETER INSTANCE = FLASH_2Mx16
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_PLB_CLK_PERIOD_PS = 10000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1
 PARAMETER C_SYNCH_MEM_0 = 0
 PARAMETER C_MEM0_WIDTH = 16
 PARAMETER C_MAX_MEM_WIDTH = 16
 PARAMETER C_TCEDV_PS_MEM_0 = 90000
 PARAMETER C_TWC_PS_MEM_0 = 40000
 PARAMETER C_TAVDV_PS_MEM_0 = 90000
 PARAMETER C_TWP_PS_MEM_0 = 40000
 PARAMETER C_THZCE_PS_MEM_0 = 10000
 PARAMETER C_TLZWE_PS_MEM_0 = 10000
 PARAMETER C_MEM0_BASEADDR = 0xff800000
 PARAMETER C_MEM0_HIGHADDR = 0xffbfffff
 BUS_INTERFACE SPLB = plb
 PORT PLB_Clk = sys_clk_s
 PORT Mem_A = fpga_0_FLASH_2Mx16_Mem_A_split
 PORT Mem_DQ = fpga_0_FLASH_2Mx16_Mem_DQ
 PORT Mem_WEN = fpga_0_FLASH_2Mx16_Mem_WEN
 PORT Mem_OEN = fpga_0_FLASH_2Mx16_Mem_OEN
 PORT Mem_BEN = FLASH_2Mx16_Mem_BEN_Flash_And_Gate_Op1
 PORT Mem_RPN = fpga_0_FLASH_2Mx16_Mem_RPN
END

BEGIN opb_ddr
 PARAMETER INSTANCE = DDR_SDRAM_32Mx16
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_REG_DIMM = 0
 PARAMETER C_DDR_TMRD = 15000
 PARAMETER C_DDR_TWR = 15000
 PARAMETER C_DDR_TWTR = 1
 PARAMETER C_DDR_TRAS = 40000
 PARAMETER C_DDR_TRC = 65000
 PARAMETER C_DDR_TRFC = 75000
 PARAMETER C_DDR_TRCD = 20000
 PARAMETER C_DDR_TRRD = 15000
 PARAMETER C_DDR_TRP = 20000
 PARAMETER C_DDR_TREFC = 70300
 PARAMETER C_DDR_TREFI = 7800000
 PARAMETER C_DDR_DWIDTH = 16
 PARAMETER C_DDR_AWIDTH = 13
 PARAMETER C_DDR_COL_AWIDTH = 10
 PARAMETER C_DDR_BANK_AWIDTH = 2
 PARAMETER C_MEM0_BASEADDR = 0x00000000
 PARAMETER C_MEM0_HIGHADDR = 0x03ffffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_s
 PORT DDR_Clk = fpga_0_DDR_SDRAM_32Mx16_DDR_Clk
 PORT DDR_Clkn = fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn
 PORT DDR_Addr = fpga_0_DDR_SDRAM_32Mx16_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr
 PORT DDR_CASn = fpga_0_DDR_SDRAM_32Mx16_DDR_CASn
 PORT DDR_CKE = fpga_0_DDR_SDRAM_32Mx16_DDR_CKE
 PORT DDR_CSn = fpga_0_DDR_SDRAM_32Mx16_DDR_CSn
 PORT DDR_RASn = fpga_0_DDR_SDRAM_32Mx16_DDR_RASn
 PORT DDR_WEn = fpga_0_DDR_SDRAM_32Mx16_DDR_WEn
 PORT DDR_DM = fpga_0_DDR_SDRAM_32Mx16_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_SDRAM_32Mx16_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_SDRAM_32Mx16_DDR_DQ
 PORT Device_Clk90_in = clk_90_s
 PORT Device_Clk90_in_n = clk_90_n_s
 PORT Device_Clk = sys_clk_s
 PORT Device_Clk_n = sys_clk_n_s
 PORT DDR_Clk90_in = ddr_clk_90_s
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END

BEGIN plb_bram_if_cntlr
 PARAMETER INSTANCE = plb_bram_if_cntlr_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER c_plb_clk_period_ps = 10000
 PARAMETER c_baseaddr = 0xffff8000
 PARAMETER c_highaddr = 0xffffffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
 PORT PLB_Clk = sys_clk_s
END

BEGIN bram_block
 PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE SOPB = opb
 PORT Irq = EICC405EXTINPUTIRQ
 PORT Intr = RS232_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt & Push_Buttons_3Bit_IP2INTC_Irpt & DIP_Switches_8Bit_IP2INTC_Irpt & FLASH_READY_IP2INTC_Irpt & Ethernet_MAC_IP2INTC_Irpt
END

BEGIN util_reduced_logic
 PARAMETER INSTANCE = Flash_And_Gate
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_OPERATION = and
 PARAMETER C_SIZE = 2
 PORT Op1 = FLASH_2Mx16_Mem_BEN_Flash_And_Gate_Op1
 PORT Res = fpga_0_Flash_And_Gate_Res
END

BEGIN util_bus_split
 PARAMETER INSTANCE = FLASH_2Mx16_util_bus_split_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 10
 PARAMETER C_SPLIT = 31
 PORT Sig = fpga_0_FLASH_2Mx16_Mem_A_split
 PORT Out1 = fpga_0_FLASH_2Mx16_Mem_A
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = sysclk_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = sys_clk_s
 PORT Res = sys_clk_n_s
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = clk_90_s
 PORT Res = clk_90_n_s
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = ddr_clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = ddr_clk_90_s
 PORT Res = ddr_clk_90_n_s
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLK90 = clk_90_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT CLKIN = ddr_feedback_s
 PORT CLK90 = ddr_clk_90_s
 PORT CLK0 = dcm_1_FB
 PORT CLKFB = dcm_1_FB
 PORT RST = dcm_0_lock
 PORT LOCKED = dcm_1_lock
END