/******************************************************************* * * CAUTION: This file is automatically generated by libgen. * Version: Xilinx EDK 8.1.02 EDK_I.20.4 * DO NOT EDIT. * * Copyright (c) 2005 Xilinx, Inc. All rights reserved. * * Description: Driver parameters * *******************************************************************/ #define XPAR_XPLBARB_NUM_INSTANCES 1 #define XPAR_PLB_BASEADDR 0x00000000 #define XPAR_PLB_HIGHADDR 0x00000000 #define XPAR_PLB_DEVICE_ID 0 #define XPAR_PLB_PLB_NUM_MASTERS 2 /******************************************************************/ #define XPAR_XOPBARB_NUM_INSTANCES 1 #define XPAR_OPB_BASEADDR 0xFFFFFFFF #define XPAR_OPB_HIGHADDR 0x00000000 #define XPAR_OPB_DEVICE_ID 0 #define XPAR_OPB_NUM_MASTERS 1 /******************************************************************/ #define XPAR_XUARTNS550_NUM_INSTANCES 1 #define XPAR_XUARTNS550_CLOCK_HZ 100000000 #define XPAR_RS232_BASEADDR 0x40400000 #define XPAR_RS232_HIGHADDR 0x4040FFFF #define XPAR_RS232_DEVICE_ID 0 /******************************************************************/ #define XPAR_XGPIO_NUM_INSTANCES 4 #define XPAR_LEDS_4BIT_BASEADDR 0x40000000 #define XPAR_LEDS_4BIT_HIGHADDR 0x4000FFFF #define XPAR_LEDS_4BIT_DEVICE_ID 0 #define XPAR_PUSH_BUTTONS_3BIT_BASEADDR 0x40020000 #define XPAR_PUSH_BUTTONS_3BIT_HIGHADDR 0x4002FFFF #define XPAR_PUSH_BUTTONS_3BIT_DEVICE_ID 1 #define XPAR_DIP_SWITCHES_8BIT_BASEADDR 0x40040000 #define XPAR_DIP_SWITCHES_8BIT_HIGHADDR 0x4004FFFF #define XPAR_DIP_SWITCHES_8BIT_DEVICE_ID 2 #define XPAR_FLASH_READY_BASEADDR 0x40060000 #define XPAR_FLASH_READY_HIGHADDR 0x4006FFFF #define XPAR_FLASH_READY_DEVICE_ID 3 /******************************************************************/ #define XPAR_DDR_SDRAM_32MX16_MEM0_BASEADDR 0x00000000 #define XPAR_DDR_SDRAM_32MX16_MEM0_HIGHADDR 0x03FFFFFF /******************************************************************/ #define XPAR_INTC_MAX_NUM_INTR_INPUTS 6 #define XPAR_XINTC_HAS_IPR 1 #define XPAR_XINTC_USE_DCR 0 #define XPAR_XINTC_NUM_INSTANCES 1 #define XPAR_OPB_INTC_0_BASEADDR 0x41200000 #define XPAR_OPB_INTC_0_HIGHADDR 0x4120FFFF #define XPAR_OPB_INTC_0_DEVICE_ID 0 #define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000 /******************************************************************/ #define XPAR_INTC_SINGLE_BASEADDR 0x41200000 #define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF #define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID #define XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK 0X000001 #define XPAR_OPB_INTC_0_ETHERNET_MAC_IP2INTC_IRPT_INTR 0 #define XPAR_FLASH_READY_IP2INTC_IRPT_MASK 0X000002 #define XPAR_OPB_INTC_0_FLASH_READY_IP2INTC_IRPT_INTR 1 #define XPAR_DIP_SWITCHES_8BIT_IP2INTC_IRPT_MASK 0X000004 #define XPAR_OPB_INTC_0_DIP_SWITCHES_8BIT_IP2INTC_IRPT_INTR 2 #define XPAR_PUSH_BUTTONS_3BIT_IP2INTC_IRPT_MASK 0X000008 #define XPAR_OPB_INTC_0_PUSH_BUTTONS_3BIT_IP2INTC_IRPT_INTR 3 #define XPAR_LEDS_4BIT_IP2INTC_IRPT_MASK 0X000010 #define XPAR_OPB_INTC_0_LEDS_4BIT_IP2INTC_IRPT_INTR 4 #define XPAR_RS232_IP2INTC_IRPT_MASK 0X000020 #define XPAR_OPB_INTC_0_RS232_IP2INTC_IRPT_INTR 5 /******************************************************************/ #define XPAR_XEMAC_NUM_INSTANCES 1 #define XPAR_ETHERNET_MAC_BASEADDR 0x80400000 #define XPAR_ETHERNET_MAC_HIGHADDR 0x8040FFFF #define XPAR_ETHERNET_MAC_DEVICE_ID 0 #define XPAR_ETHERNET_MAC_ERR_COUNT_EXIST 1 #define XPAR_ETHERNET_MAC_DMA_PRESENT 1 #define XPAR_ETHERNET_MAC_MII_EXIST 1 /******************************************************************/ #define XPAR_FLASH_2MX16_NUM_BANKS_MEM 1 /* copied from xparameters_2vpx.h.orig file */ #define XPAR_XEMC_NUM_INSTANCES 1 #define XPAR_FLASH_2MX32_BASEADDR 0xFE804000 #define XPAR_FLASH_2MX32_HIGHADDR 0xFE80401F #define XPAR_FLASH_2MX32_DEVICE_ID 0 #define XPAR_FLASH_2MX32_NUM_BANKS_MEM 1 /******************************************************************/ #define XPAR_FLASH_2MX16_MEM0_BASEADDR 0xFF800000 #define XPAR_FLASH_2MX16_MEM0_HIGHADDR 0xFFBFFFFF /******************************************************************/ #define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xffff8000 #define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff /******************************************************************/ #define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 100000000 /******************************************************************/ /******************************************************************/ /* Linux Redefines */ /******************************************************************/ #define XPAR_UARTNS550_0_BASEADDR (XPAR_RS232_BASEADDR+0x1000) #define XPAR_UARTNS550_0_HIGHADDR XPAR_RS232_HIGHADDR #define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ #define XPAR_UARTNS550_0_DEVICE_ID XPAR_RS232_DEVICE_ID /******************************************************************/ #define XPAR_EMAC_0_BASEADDR XPAR_ETHERNET_MAC_BASEADDR #define XPAR_EMAC_0_HIGHADDR XPAR_ETHERNET_MAC_HIGHADDR #define XPAR_EMAC_0_DMA_PRESENT XPAR_ETHERNET_MAC_DMA_PRESENT #define XPAR_EMAC_0_MII_EXIST XPAR_ETHERNET_MAC_MII_EXIST #define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_ETHERNET_MAC_ERR_COUNT_EXIST #define XPAR_EMAC_0_DEVICE_ID XPAR_ETHERNET_MAC_DEVICE_ID /******************************************************************/ #define XPAR_GPIO_0_BASEADDR XPAR_LEDS_4BIT_BASEADDR #define XPAR_GPIO_0_HIGHADDR XPAR_LEDS_4BIT_HIGHADDR #define XPAR_GPIO_0_DEVICE_ID XPAR_LEDS_4BIT_DEVICE_ID #define XPAR_GPIO_1_BASEADDR XPAR_PUSH_BUTTONS_3BIT_BASEADDR #define XPAR_GPIO_1_HIGHADDR XPAR_PUSH_BUTTONS_3BIT_HIGHADDR #define XPAR_GPIO_1_DEVICE_ID XPAR_PUSH_BUTTONS_3BIT_DEVICE_ID #define XPAR_GPIO_2_BASEADDR XPAR_DIP_SWITCHES_8BIT_BASEADDR #define XPAR_GPIO_2_HIGHADDR XPAR_DIP_SWITCHES_8BIT_HIGHADDR #define XPAR_GPIO_2_DEVICE_ID XPAR_DIP_SWITCHES_8BIT_DEVICE_ID #define XPAR_GPIO_3_BASEADDR XPAR_FLASH_READY_BASEADDR #define XPAR_GPIO_3_HIGHADDR XPAR_FLASH_READY_HIGHADDR #define XPAR_GPIO_3_DEVICE_ID XPAR_FLASH_READY_DEVICE_ID /******************************************************************/ #define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR #define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR #define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR #define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID /******************************************************************/ #define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_OPB_INTC_0_ETHERNET_MAC_IP2INTC_IRPT_INTR #define XPAR_INTC_0_GPIO_3_VEC_ID XPAR_OPB_INTC_0_FLASH_READY_IP2INTC_IRPT_INTR #define XPAR_INTC_0_GPIO_2_VEC_ID XPAR_OPB_INTC_0_DIP_SWITCHES_8BIT_IP2INTC_IRPT_INTR #define XPAR_INTC_0_GPIO_1_VEC_ID XPAR_OPB_INTC_0_PUSH_BUTTONS_3BIT_IP2INTC_IRPT_INTR #define XPAR_INTC_0_GPIO_0_VEC_ID XPAR_OPB_INTC_0_LEDS_4BIT_IP2INTC_IRPT_INTR #define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_OPB_INTC_0_RS232_IP2INTC_IRPT_INTR /******************************************************************/ #define XPAR_PLB_CLOCK_FREQ_HZ 100000000 #define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ #define XPAR_DDR_0_SIZE 0x4000000 /******************************************************************/ #define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400 #define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF #define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0 /******************************************************************/ #define XPAR_PCI_0_CLOCK_FREQ_HZ 0 /******************************************************************/ /******************************************************************/ /*added by oliv*/ /*#define XPAR_OPB_LCD_INTERFACE_0_BASEADDR 0xFE804800 #define XPAR_OPB_LCD_INTERFACE_0_HIGHADDR 0xFE8048FF #define XPAR_FLASH_2MX32_MEM0_BASEADDR 0xFE000000 #define XPAR_FLASH_2MX32_MEM0_HIGHADDR 0xFE7FFFFF*/ /******************************************************************/