From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: Chenging 2 bits in MSR in ppc6xx_idle() with 1 command?
Date: Wed, 27 Dec 2006 10:48:54 +1100 [thread overview]
Message-ID: <1167176934.3522.15.camel@localhost.localdomain> (raw)
In-Reply-To: <Pine.LNX.4.60.0612252053410.3424@poirot.grange>
On Mon, 2006-12-25 at 21:07 +0100, Guennadi Liakhovetski wrote:
> Hi
>
> Here's a code fragment from ppc6xx_idle(), which should send the CPU into
> a powersaving mode (DOZE or NAP) and re-enable interrupts after a
> local_irq_disable():
>
> mfmsr r7
> ori r7,r7,MSR_EE
> oris r7,r7,MSR_POW@h
> 1: sync
> mtmsr r7
> isync
> b 1b
>
> Whereas MPC8245's user manual says, that when setting the MSR_POW bit in
> the MSR one may not set any other bit in it with the same instruction.
> Does this mean that the above does not actually work on those (and
> similar) CPUs or does it work because of the loop?
That doc bit looks a bit strange. The kernel pretty much relies on
setting MSR:EE and MSR:POW atomicaly.
Ben.
next prev parent reply other threads:[~2006-12-26 23:48 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-12-25 20:07 Chenging 2 bits in MSR in ppc6xx_idle() with 1 command? Guennadi Liakhovetski
2006-12-26 23:48 ` Benjamin Herrenschmidt [this message]
2006-12-26 23:56 ` Guennadi Liakhovetski
2006-12-27 20:44 ` Guennadi Liakhovetski
2006-12-27 21:15 ` Benjamin Herrenschmidt
2006-12-28 2:30 ` Segher Boessenkool
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