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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: Chenging 2 bits in MSR in ppc6xx_idle() with 1 command?
Date: Thu, 28 Dec 2006 08:15:16 +1100	[thread overview]
Message-ID: <1167254116.23340.14.camel@localhost.localdomain> (raw)
In-Reply-To: <Pine.LNX.4.60.0612272135470.13342@poirot.grange>


> Hm, wouldn't it just work? In ppc6xx_idle() the _TLF_NAPPING bit is set. 
> If as a result of mtmsr only the EE bit is set and we get an interrupt, we 
> end up in transfer_to_handler(), check the flag, it is set, so we branch 
> to power_save_6xx_restore(). There we clear NAP/DOZE and just jump to 
> transfer_to_handler_cont(). Why did you say we'd miss the check for 
> need_resched (on IRC)? How is this case difference from if we really did 
> go to NAP / DOZE?
> 
> Are there other places in the kernel where we rely on setting MSR:POW and 
> some other bit atomically?

Indeed, the napping "recovery" code might save us here... funny, as it
wasn't implemented to handle that case at all...

Ben.

  reply	other threads:[~2006-12-27 21:15 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-12-25 20:07 Chenging 2 bits in MSR in ppc6xx_idle() with 1 command? Guennadi Liakhovetski
2006-12-26 23:48 ` Benjamin Herrenschmidt
2006-12-26 23:56   ` Guennadi Liakhovetski
2006-12-27 20:44   ` Guennadi Liakhovetski
2006-12-27 21:15     ` Benjamin Herrenschmidt [this message]
2006-12-28  2:30     ` Segher Boessenkool

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