From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id 20FB7DDDF5 for ; Wed, 7 Mar 2007 08:04:57 +1100 (EST) Subject: Re: Clearing the interrupt From: Benjamin Herrenschmidt To: mohan@in.ibm.com In-Reply-To: <20070306173941.GE7476@in.ibm.com> References: <20070306173941.GE7476@in.ibm.com> Content-Type: text/plain Date: Tue, 06 Mar 2007 22:04:47 +0100 Message-Id: <1173215087.9349.17.camel@localhost.localdomain> Mime-Version: 1.0 Cc: linuxppc-dev@ozlabs.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , > Is there any problem with the above approach? Is there any restriction > such that a cpu which acknowledged the interrupt only should send the eoi > signal? While I don't think there -should- be any restriction, I also seem to remember that the xics "emulation" done by the firmware on things like JS20 requires the eoi to be done from the CPU where the interrupt originated. Ben.