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Subject: Re: Try to Disable PPC Interrupt
From: Josh Boyer <jwboyer@linux.vnet.ibm.com>
To: Kumar Gala <galak@kernel.crashing.org>
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	<38067FD3-F201-4373-A067-CFED1589D6C3@kernel.crashing.org>
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Date: Thu, 29 Mar 2007 14:23:11 -0500
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On Thu, 2007-03-29 at 13:41 -0500, Kumar Gala wrote:
> > It seems the 16th bit (EE) has been set to 0, but what should I do  
> > to make sure whether the external interrupt is disabled or not?  
> > Thank you very much.
> 
> What exactly are you asking?  If MSR[EE] = 0, interrupts are disabled.

Since you're on a 405, you can actually test this from within your code
still.  Use the SRS bits in the UICs to generate a spurious interrupt at
the UIC level for something that is currently enabled in the ER
register.  If you still get an interrupt at the CPU with MSR[EE] == 0,
then you've found a very odd bug indeed.

But as Kumar says, if MSR[EE] == 0, external interrupts are disabled.
Of course, that doesn't mean that debug, machine check, or critical
interrupts are.

(How to use the SRS bits in the UICs is an exercise left up to the
reader.)

josh