From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id BF907DDF58 for ; Fri, 13 Apr 2007 12:43:57 +1000 (EST) Subject: Re: qla_wxyz pci_set_mwi question From: Benjamin Herrenschmidt To: Randy Dunlap In-Reply-To: <461EEDAA.7090503@oracle.com> References: <20070411221507.69c97257.randy.dunlap@oracle.com> <20070412172038.GG10124@andrew-vasquezs-computer.local> <20070412185347.GL26692@parisc-linux.org> <20070412193713.GB14510@andrew-vasquezs-computer.local> <20070412200438.GM26692@parisc-linux.org> <1176431662.5764.56.camel@localhost.localdomain> <461EEDAA.7090503@oracle.com> Content-Type: text/plain Date: Fri, 13 Apr 2007 12:43:43 +1000 Message-Id: <1176432224.5764.59.camel@localhost.localdomain> Mime-Version: 1.0 Cc: scsi , Matthew Wilcox , gregkh , David Somayajulu , linuxppc-dev@ozlabs.org, Andrew Vasquez , linux-driver@qlogic.com, PCI List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , > Willy was referring to this from include/asm-powerpc/pci.h: > > #ifdef CONFIG_PPC64 > > /* > * We want to avoid touching the cacheline size or MWI bit. > * pSeries firmware sets the cacheline size (which is not the cpu cacheline > * size in all cases) and hardware treats MWI the same as memory write. > */ > #define PCI_DISABLE_MWI > > > which makes pci_set_mwi() do nothing other than return 0; Interesting... I think I missed that we had that bit for some time :-) Well, I suppose that on pSeries and probably pmac too, the firmware will set the MWI bit for us anyway, but that's a bit dodgy to apply that to all ppc64... they aren't all pSeries. I'll have to look into that again one of these days. Cheers, Ben.