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Subject: Re: fsl booke MM vs. SMP questions
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Dave Liu <r63238@freescale.com>
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Date: Wed, 23 May 2007 08:42:22 +1000
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On Tue, 2007-05-22 at 18:56 +0800, Dave Liu wrote:
> On Tue, 2007-05-22 at 13:09 +1000, Benjamin Herrenschmidt wrote:
> > In the end, the best solution might still be to simply not do any of
> > this and instead send an IPI on invalidations. That's the method used by
> > most architectures in linux (if not all) that do software TLB load on
> > SMP. Basically, the invalidate code path then does:
> > 
> > 	- Update the linux PTE
> > 	- write barrier
> > 	- send IPI interrupt to all CPUs in mm->cpu_vm_mask
> > 	- local TLB flush
> > 
> > And the IPI does a local TLB flush on all affected CPUs.
> 
> How to avoid IPI interrupt missing if the IPI interrupt is edge-
> triggered?
> 
> or How to make sure TLB flushed on the else all affected CPUs?

The IPIs should be buffered by the PIC ... delivered only once but
still. Also, IPI handling in linux is synchronous, there is an ack to
wait for the remote function to complete.

Ben.