* [PATCH]: Add 8548 pcie bus number workaround
@ 2007-06-07 3:13 Zang Roy-r61911
0 siblings, 0 replies; 5+ messages in thread
From: Zang Roy-r61911 @ 2007-06-07 3:13 UTC (permalink / raw)
To: linuxppc-dev list; +Cc: Paul Mackerras
From: Zang Roy-r61911 <tie-fei.zang@freescale.com>
Remove legacy pcie support for 8641 chip.
General PCI code can fully support 8641 Rev2.0 chip.
For 8548 PEX controller, PCIE host controller configure
space can only be accessed as "bus->number = 0" in
the PCI architecture. So "bus->number == hose->bus_offset"
judgment is added.
Some minor space indentation clean up.
---
arch/powerpc/sysdev/fsl_pcie.c | 28 ++++++++++++++--------------
1 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pcie.c b/arch/powerpc/sysdev/fsl_pcie.c
index 041c07e..79e9546 100644
--- a/arch/powerpc/sysdev/fsl_pcie.c
+++ b/arch/powerpc/sysdev/fsl_pcie.c
@@ -47,16 +47,16 @@ indirect_read_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,
return PCIBIOS_DEVICE_NOT_FOUND;
PCIE_FIX;
- if (bus->number == 0xff) {
+ if (bus->number == hose->bus_offset) {
PCI_CFG_OUT(hose->cfg_addr,
- (0x80000000 | ((offset & 0xf00) << 16) |
- ((bus->number - hose->bus_offset) << 16)
- | (devfn << 8) | ((offset & 0xfc) )));
+ (0x80000000 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
} else {
PCI_CFG_OUT(hose->cfg_addr,
- (0x80000001 | ((offset & 0xf00) << 16) |
- ((bus->number - hose->bus_offset) << 16)
- | (devfn << 8) | ((offset & 0xfc) )));
+ (0x80000000 | ((offset & 0xf00) << 16) |
+ (bus->number << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
}
/*
@@ -98,16 +98,16 @@ indirect_write_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,
return PCIBIOS_DEVICE_NOT_FOUND;
PCIE_FIX;
- if (bus->number == 0xff) {
+ if (bus->number == hose->bus_offset) {
PCI_CFG_OUT(hose->cfg_addr,
- (0x80000000 | ((offset & 0xf00) << 16) |
- ((bus->number - hose->bus_offset) << 16)
- | (devfn << 8) | ((offset & 0xfc) )));
+ (0x80000000 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
} else {
PCI_CFG_OUT(hose->cfg_addr,
- (0x80000001 | ((offset & 0xf00) << 16) |
- ((bus->number - hose->bus_offset) << 16)
- | (devfn << 8) | ((offset & 0xfc) )));
+ (0x80000000 | ((offset & 0xf00) << 16) |
+ (bus->number << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
}
/*
--
1.5.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH]: Add 8548 pcie bus number workaround
@ 2007-06-07 3:19 Zang Roy-r61911
2007-06-07 6:48 ` Kumar Gala
0 siblings, 1 reply; 5+ messages in thread
From: Zang Roy-r61911 @ 2007-06-07 3:19 UTC (permalink / raw)
To: linuxppc-dev list; +Cc: Paul Mackerras
From: Zang Roy-r61911 <tie-fei.zang@freescale.com>
Remove legacy pcie support for 8641 chip.
General PCI code can fully support 8641 Rev2.0 chip.
For 8548 PEX controller, PCIE host controller configure
space can only be accessed as "bus->number = 0" in
the PCI architecture. So "bus->number == hose->bus_offset"
judgment is added.
Some minor space indentation clean up.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
Please ignore the previous and pick up this one.
Sorry for it!
arch/powerpc/sysdev/fsl_pcie.c | 28 ++++++++++++++--------------
1 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pcie.c b/arch/powerpc/sysdev/fsl_pcie.c
index 041c07e..79e9546 100644
--- a/arch/powerpc/sysdev/fsl_pcie.c
+++ b/arch/powerpc/sysdev/fsl_pcie.c
@@ -47,16 +47,16 @@ indirect_read_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,
return PCIBIOS_DEVICE_NOT_FOUND;
PCIE_FIX;
- if (bus->number == 0xff) {
+ if (bus->number == hose->bus_offset) {
PCI_CFG_OUT(hose->cfg_addr,
- (0x80000000 | ((offset & 0xf00) << 16) |
- ((bus->number - hose->bus_offset) << 16)
- | (devfn << 8) | ((offset & 0xfc) )));
+ (0x80000000 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
} else {
PCI_CFG_OUT(hose->cfg_addr,
- (0x80000001 | ((offset & 0xf00) << 16) |
- ((bus->number - hose->bus_offset) << 16)
- | (devfn << 8) | ((offset & 0xfc) )));
+ (0x80000000 | ((offset & 0xf00) << 16) |
+ (bus->number << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
}
/*
@@ -98,16 +98,16 @@ indirect_write_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,
return PCIBIOS_DEVICE_NOT_FOUND;
PCIE_FIX;
- if (bus->number == 0xff) {
+ if (bus->number == hose->bus_offset) {
PCI_CFG_OUT(hose->cfg_addr,
- (0x80000000 | ((offset & 0xf00) << 16) |
- ((bus->number - hose->bus_offset) << 16)
- | (devfn << 8) | ((offset & 0xfc) )));
+ (0x80000000 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
} else {
PCI_CFG_OUT(hose->cfg_addr,
- (0x80000001 | ((offset & 0xf00) << 16) |
- ((bus->number - hose->bus_offset) << 16)
- | (devfn << 8) | ((offset & 0xfc) )));
+ (0x80000000 | ((offset & 0xf00) << 16) |
+ (bus->number << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
}
/*
--
1.5.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH]: Add 8548 pcie bus number workaround
2007-06-07 3:19 [PATCH]: Add 8548 pcie bus number workaround Zang Roy-r61911
@ 2007-06-07 6:48 ` Kumar Gala
2007-06-07 8:54 ` Zhang Wei-r63237
2007-06-07 9:04 ` Zang Roy-r61911
0 siblings, 2 replies; 5+ messages in thread
From: Kumar Gala @ 2007-06-07 6:48 UTC (permalink / raw)
To: Zang Roy-r61911; +Cc: linuxppc-dev list, Paul Mackerras
On Jun 6, 2007, at 10:19 PM, Zang Roy-r61911 wrote:
>
> From: Zang Roy-r61911 <tie-fei.zang@freescale.com>
>
> Remove legacy pcie support for 8641 chip.
> General PCI code can fully support 8641 Rev2.0 chip.
> For 8548 PEX controller, PCIE host controller configure
> space can only be accessed as "bus->number = 0" in
> the PCI architecture. So "bus->number == hose->bus_offset"
> judgment is added.
Uugh, I'm completely confused. Does 8548 rev 2.x have some errata
(or 'feature') that 8641 doesn't have?
- k
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH]: Add 8548 pcie bus number workaround
2007-06-07 6:48 ` Kumar Gala
@ 2007-06-07 8:54 ` Zhang Wei-r63237
2007-06-07 9:04 ` Zang Roy-r61911
1 sibling, 0 replies; 5+ messages in thread
From: Zhang Wei-r63237 @ 2007-06-07 8:54 UTC (permalink / raw)
To: Kumar Gala, Zang Roy-r61911; +Cc: linuxppc-dev list, Paul Mackerras
MPC8641 v2.0 have fixed the errata. And v1.0 is not supported.
Wei.
> -----Original Message-----
> From: linuxppc-dev-bounces+wei.zhang=3Dfreescale.com@ozlabs.org=20
> [mailto:linuxppc-dev-bounces+wei.zhang=3Dfreescale.com@ozlabs.or
> g] On Behalf Of Kumar Gala
> Sent: Thursday, June 07, 2007 2:49 PM
> To: Zang Roy-r61911
> Cc: linuxppc-dev list; Paul Mackerras
> Subject: Re: [PATCH]: Add 8548 pcie bus number workaround
>=20
>=20
> On Jun 6, 2007, at 10:19 PM, Zang Roy-r61911 wrote:
>=20
> >
> > From: Zang Roy-r61911 <tie-fei.zang@freescale.com>
> >
> > Remove legacy pcie support for 8641 chip.
> > General PCI code can fully support 8641 Rev2.0 chip.
> > For 8548 PEX controller, PCIE host controller configure
> > space can only be accessed as "bus->number =3D 0" in
> > the PCI architecture. So "bus->number =3D=3D hose->bus_offset"
> > judgment is added.
>=20
> Uugh, I'm completely confused. Does 8548 rev 2.x have some errata =20
> (or 'feature') that 8641 doesn't have?
>=20
> - k
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>=20
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH]: Add 8548 pcie bus number workaround
2007-06-07 6:48 ` Kumar Gala
2007-06-07 8:54 ` Zhang Wei-r63237
@ 2007-06-07 9:04 ` Zang Roy-r61911
1 sibling, 0 replies; 5+ messages in thread
From: Zang Roy-r61911 @ 2007-06-07 9:04 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev list, Paul Mackerras
On Thu, 2007-06-07 at 14:48, Kumar Gala wrote:
> On Jun 6, 2007, at 10:19 PM, Zang Roy-r61911 wrote:
>
> >
> > From: Zang Roy-r61911 <tie-fei.zang@freescale.com>
> >
> > Remove legacy pcie support for 8641 chip.
> > General PCI code can fully support 8641 Rev2.0 chip.
> > For 8548 PEX controller, PCIE host controller configure
> > space can only be accessed as "bus->number = 0" in
> > the PCI architecture. So "bus->number == hose->bus_offset"
> > judgment is added.
>
> Uugh, I'm completely confused. Does 8548 rev 2.x have some errata
> (or 'feature') that 8641 doesn't have?
NO! I do not think so!
It is a story about the 85xx/86xx pcie road map.
Originally, fsl_pcie.c is based on the pcie support code for 86xx (1.x
or later).
Jdl and I separate this part of code for the purpose to support both
85xx/86xx pcie. So this part of code contains some garbage code for
legacy 86xx pcie support or debug information. I have discussed this
with the original developer.
So in this patch I remove the unused code. Is it wrong?
Now this file is target to support 8548 rev 1.x and 2.x pcie controller.
Now, I am working to put some common code to support 85xx/86xx pcie in
this file, such as atmu init and link status check.
Moer patches will be posted to provide a completely pcie support for
85xx/86xx.
Thanks.
Roy
^ permalink raw reply [flat|nested] 5+ messages in thread
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2007-06-07 3:19 [PATCH]: Add 8548 pcie bus number workaround Zang Roy-r61911
2007-06-07 6:48 ` Kumar Gala
2007-06-07 8:54 ` Zhang Wei-r63237
2007-06-07 9:04 ` Zang Roy-r61911
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