From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id A51B0DDF1F for ; Thu, 28 Jun 2007 19:13:55 +1000 (EST) Subject: Re: [RFC/PATCH] powerpc: MPC7450 L2 HW cache flush feature utilization From: Benjamin Herrenschmidt To: Segher Boessenkool In-Reply-To: References: <1181729973.25586.31.camel@dolphin.spb.rtsoft.ru> <467176EB.7060404@ru.mvista.com> <6c416bf9f79a648fc82f64619aca86de@kernel.crashing.org> <20070615212016.GB18055@mag.az.mvista.com> <1182429443.24740.8.camel@localhost.localdomain> <467BE91F.1030003@ru.mvista.com> <3372b921591ca9731d2703f04e6c35f1@kernel.crashing.org> <467FCC9D.6010904@ru.mvista.com> Content-Type: text/plain Date: Thu, 28 Jun 2007 19:13:46 +1000 Message-Id: <1183022026.5521.269.camel@localhost.localdomain> Mime-Version: 1.0 Cc: linuxppc-dev list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , > > The erratum says nothing about any HW bugs with L3 cache flush. I just > > mentioned that the L3 cache flush operation described in MPC7450 > > Reference manual is similar to the L2 using the L3 cache hardware > > flushing mechanism. For instance, it requires a complete L3 locking > > before flushing. > > Then I think we should use that mechanism in the Linux kernel. > Anything else is waiting for bugs to bite. I just figured out ... we actually already have all of that cache flush code :-) I wrote most of it in fact. It's just that for some (bad) reasons, it's somewhat hidden in arch/powerpc/platforms/powermac/cache.S So I think best would be to take it from there and make it more generic ... Cheers, Ben.