PCI IO range limitation

PCI IO range limitation

[Marian Balakowicz]

Hi,

Trying to change PCI IO window base for 52xx target I found that
we are pretty much limited to a "0" offset only.

pci_process_bridge_OF_ranges() will not process any IO range that has
addresses set to anything else.

956:      case 1:         /* I/O space */
957:               if (ranges[2] != 0)
958:                       break;

When this range[2] checking is removed from
pci_process_bridge_OF_ranges() kernel boots ok with the non-zero PCI IO
base, but the PCI device I am using (e100) will not work.

I guess that with the above dropping of non-zero based PCI IO ranges
this is not supposed to be working. But does anyone know why?

Thanks,
Marian

Re: PCI IO range limitation

[Benjamin Herrenschmidt]

On Thu, 2007-06-28 at 12:20 +0200, Marian Balakowicz wrote:
> Hi,
> 
> Trying to change PCI IO window base for 52xx target I found that
> we are pretty much limited to a "0" offset only.
> 
> pci_process_bridge_OF_ranges() will not process any IO range that has
> addresses set to anything else.
> 
> 956:      case 1:         /* I/O space */
> 957:               if (ranges[2] != 0)
> 958:                       break;
> 
> When this range[2] checking is removed from
> pci_process_bridge_OF_ranges() kernel boots ok with the non-zero PCI IO
> base, but the PCI device I am using (e100) will not work.
> 
> I guess that with the above dropping of non-zero based PCI IO ranges
> this is not supposed to be working. But does anyone know why?

We just fixed that for 64 bits but 32 bits still has the limitation.
Note that it's not a very good idea to have your IO range at !0 if
you're going to use anything ISA-like, such as a VGA video card or other
legacy devices behind a PCI southbridge or SuperIO.

Ben.

Re: PCI IO range limitation

[Matt Sealey]

Benjamin Herrenschmidt wrote:
> On Thu, 2007-06-28 at 12:20 +0200, Marian Balakowicz wrote:
>> Hi,
>>
>> Trying to change PCI IO window base for 52xx target I found that
>> we are pretty much limited to a "0" offset only.
> 
> We just fixed that for 64 bits but 32 bits still has the limitation.
> Note that it's not a very good idea to have your IO range at !0 if
> you're going to use anything ISA-like, such as a VGA video card or other
> legacy devices behind a PCI southbridge or SuperIO.

The chances of that on an MPC52xx platform are practically zero, aren't
they?

-- 
Matt Sealey <matt@genesi-usa.com>
Genesi, Manager, Developer Relations

Re: PCI IO range limitation

[Benjamin Herrenschmidt]

On Fri, 2007-06-29 at 00:38 +0100, Matt Sealey wrote:
> Benjamin Herrenschmidt wrote:
> > On Thu, 2007-06-28 at 12:20 +0200, Marian Balakowicz wrote:
> >> Hi,
> >>
> >> Trying to change PCI IO window base for 52xx target I found that
> >> we are pretty much limited to a "0" offset only.
> > 
> > We just fixed that for 64 bits but 32 bits still has the limitation.
> > Note that it's not a very good idea to have your IO range at !0 if
> > you're going to use anything ISA-like, such as a VGA video card or other
> > legacy devices behind a PCI southbridge or SuperIO.
> 
> The chances of that on an MPC52xx platform are practically zero, aren't
> they?

Euh... don't you use VGA video cards on Efika ? :-)

Ben.

Re: PCI IO range limitation

[Matt Sealey]

Benjamin Herrenschmidt wrote:

> On Fri, 2007-06-29 at 00:38 +0100, Matt Sealey wrote:
>> Benjamin Herrenschmidt wrote:
>>> On Thu, 2007-06-28 at 12:20 +0200, Marian Balakowicz wrote:
>>>> Hi,
>>>>
>>>> Trying to change PCI IO window base for 52xx target I found that
>>>> we are pretty much limited to a "0" offset only.
>>> We just fixed that for 64 bits but 32 bits still has the limitation.
>>> Note that it's not a very good idea to have your IO range at !0 if
>>> you're going to use anything ISA-like, such as a VGA video card or other
>>> legacy devices behind a PCI southbridge or SuperIO.
>> The chances of that on an MPC52xx platform are practically zero, aren't
>> they?
> 
> Euh... don't you use VGA video cards on Efika ? :-)

Define "legacy device"? What should that entail? You mean like mapping
most of those registers to the first couple of kilobytes of "IO"?

If they're just left as their own on their own as PCI devices, why would
it matter what the window was?

-- 
Matt Sealey <matt@genesi-usa.com>
Genesi, Manager, Developer Relations

Re: PCI IO range limitation

[Benjamin Herrenschmidt]

> Define "legacy device"? What should that entail? You mean like mapping
> most of those registers to the first couple of kilobytes of "IO"?

Anything that hard-decodes IOs in the low ISA range yes. That includes
VGA video cards.

> If they're just left as their own on their own as PCI devices, why would
> it matter what the window was?

Because quite a few of those things hard decodes (can't be moved around,
so -have- to be able to generate cycles to those low addresses to hit
them) and sometimes don't even fully decode the 32 bits addresses
(though that's more rare).

For example, a VGA video card in text mode hard decodes both IO and
Memory at the legacy VGA ranges.

Ben.

Re: PCI IO range limitation

[Marian Balakowicz]

Benjamin Herrenschmidt wrote:
> On Thu, 2007-06-28 at 12:20 +0200, Marian Balakowicz wrote:
>> I guess that with the above dropping of non-zero based PCI IO ranges
>> this is not supposed to be working. But does anyone know why?
> 
> We just fixed that for 64 bits but 32 bits still has the limitation.
> Note that it's not a very good idea to have your IO range at !0 if
> you're going to use anything ISA-like, such as a VGA video card or other
> legacy devices behind a PCI southbridge or SuperIO.

Agree with the zero-based IO range for ISA devices. But, knowing we don't have any ISA stuff on board it should be possible to change the IO base. Are you planning on modifications for 32 bits as well?

Marian

Re: PCI IO range limitation

[Benjamin Herrenschmidt]

On Tue, 2007-07-03 at 11:24 +0200, Marian Balakowicz wrote:
> Benjamin Herrenschmidt wrote:
> > On Thu, 2007-06-28 at 12:20 +0200, Marian Balakowicz wrote:
> >> I guess that with the above dropping of non-zero based PCI IO ranges
> >> this is not supposed to be working. But does anyone know why?
> > 
> > We just fixed that for 64 bits but 32 bits still has the limitation.
> > Note that it's not a very good idea to have your IO range at !0 if
> > you're going to use anything ISA-like, such as a VGA video card or other
> > legacy devices behind a PCI southbridge or SuperIO.
> 
> Agree with the zero-based IO range for ISA devices. But, knowing we don't
> have any ISA stuff on board it should be possible to change the IO base.

And you don't plan to ever have a VGA video card ?

> Are you planning on modifications for 32 bits as well?

Not right now, but you are welcome to send a patch :-) Though I fail to
see why you want to do it.

Ben

Re: PCI IO range limitation

[Marian Balakowicz]

Benjamin Herrenschmidt wrote:
> On Tue, 2007-07-03 at 11:24 +0200, Marian Balakowicz wrote:
>> Benjamin Herrenschmidt wrote:
>>> On Thu, 2007-06-28 at 12:20 +0200, Marian Balakowicz wrote:
>>>> I guess that with the above dropping of non-zero based PCI IO ranges
>>>> this is not supposed to be working. But does anyone know why?
>>> We just fixed that for 64 bits but 32 bits still has the limitation.
>>> Note that it's not a very good idea to have your IO range at !0 if
>>> you're going to use anything ISA-like, such as a VGA video card or other
>>> legacy devices behind a PCI southbridge or SuperIO.
>> Agree with the zero-based IO range for ISA devices. But, knowing we don't
>> have any ISA stuff on board it should be possible to change the IO base.
> 
> And you don't plan to ever have a VGA video card ?

You definitely got a point, but still, I tend to think that if someone wants to shoot himself in a foot he should be free to do it.

>> Are you planning on modifications for 32 bits as well?
> 
> Not right now, but you are welcome to send a patch :-) Though I fail to
> see why you want to do it.

I don't necessarily need that, I was rather wondering what were the reasons for such modification. This used to be allowed in 2.4, while 2.6 kernel with the legacy setup will silently reset. Kernel booting and issuing a big warning instead would be much nicer if we are to stick to the 0 based IO ranges.

Marian