[patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[Zang Roy-r61911]

From: Roy Zang <tie-fei.zang@freescale.com>

Add 8548 CDS PCI express controller node and PCI-X device node.
The current  dts file is suitable for 8548 Rev 2.0 board with
Arcadia 3.1.
This kind of board combination is the most popular.

Indentify pci, pcie host by compatible property "fsl,mpc85xx-pci"
and "fsl, mpc85xx-pciex".

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
 arch/powerpc/boot/dts/mpc8548cds.dts |  156 +++++++++++++++++++++++-----------
 1 files changed, 105 insertions(+), 51 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 9d0b84b..d60821b 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -1,5 +1,5 @@
 /*
- * MPC8555 CDS Device Tree Source
+ * MPC8548 CDS Device Tree Source
  *
  * Copyright 2006 Freescale Semiconductor Inc.
  *
@@ -186,67 +186,96 @@
 		pci1: pci@8000 {
 			interrupt-map-mask = <1f800 0 0 7>;
 			interrupt-map = <
+				/* IDSEL 0x4 (PCIX Slot 2) */
+				02000 0 0 1 &mpic 0 1
+				02000 0 0 2 &mpic 1 1
+				02000 0 0 3 &mpic 2 1
+				02000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0x5 (PCIX Slot 3) */
+				02800 0 0 1 &mpic 1 1
+				02800 0 0 2 &mpic 2 1
+				02800 0 0 3 &mpic 3 1
+				02800 0 0 4 &mpic 0 1
+
+				/* IDSEL 0x6 (PCIX Slot 4) */
+				03000 0 0 1 &mpic 2 1
+				03000 0 0 2 &mpic 3 1
+				03000 0 0 3 &mpic 0 1
+				03000 0 0 4 &mpic 1 1
+
+				/* IDSEL 0x8 (PCIX Slot 5) */
+				04000 0 0 1 &mpic 0 1
+				04000 0 0 2 &mpic 1 1
+				04000 0 0 3 &mpic 2 1
+				04000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0xC (Tsi310 bridge) */
+				06000 0 0 1 &mpic 0 1
+				06000 0 0 2 &mpic 1 1
+				06000 0 0 3 &mpic 2 1
+				06000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0x14 (Slot 2) */
+				0a000 0 0 1 &mpic 0 1
+				0a000 0 0 2 &mpic 1 1
+				0a000 0 0 3 &mpic 2 1
+				0a000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0x15 (Slot 3) */
+				0a800 0 0 1 &mpic 1 1
+				0a800 0 0 2 &mpic 2 1
+				0a800 0 0 3 &mpic 3 1
+				0a800 0 0 4 &mpic 0 1
+
+				/* IDSEL 0x16 (Slot 4) */
+				0b000 0 0 1 &mpic 2 1
+				0b000 0 0 2 &mpic 3 1
+				0b000 0 0 3 &mpic 0 1
+				0b000 0 0 4 &mpic 1 1
+
+				/* IDSEL 0x18 (Slot 5) */
+				0c000 0 0 1 &mpic 0 1
+				0c000 0 0 2 &mpic 1 1
+				0c000 0 0 3 &mpic 2 1
+				0c000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
+				0E000 0 0 1 &mpic 0 1
+				0E000 0 0 2 &mpic 1 1
+				0E000 0 0 3 &mpic 2 1
+				0E000 0 0 4 &mpic 3 1
+
+				/* bus 1 , idsel 0x2 Tsi310 bridge secondary */
+				11000 0 0 1 &mpic 2 1
+				11000 0 0 2 &mpic 3 1
+				11000 0 0 3 &mpic 0 1
+				11000 0 0 4 &mpic 1 1
+
+				/* VIA chip */
+				12000 0 0 1 &mpic 0 1
+				12000 0 0 2 &mpic 1 1
+				12000 0 0 3 &mpic 2 1
+				12000 0 0 4 &mpic 3 1>;
 
-				/* IDSEL 0x10 */
-				08000 0 0 1 &mpic 0 1
-				08000 0 0 2 &mpic 1 1
-				08000 0 0 3 &mpic 2 1
-				08000 0 0 4 &mpic 3 1
-
-				/* IDSEL 0x11 */
-				08800 0 0 1 &mpic 0 1
-				08800 0 0 2 &mpic 1 1
-				08800 0 0 3 &mpic 2 1
-				08800 0 0 4 &mpic 3 1
-
-				/* IDSEL 0x12 (Slot 1) */
-				09000 0 0 1 &mpic 0 1
-				09000 0 0 2 &mpic 1 1
-				09000 0 0 3 &mpic 2 1
-				09000 0 0 4 &mpic 3 1
-
-				/* IDSEL 0x13 (Slot 2) */
-				09800 0 0 1 &mpic 1 1
-				09800 0 0 2 &mpic 2 1
-				09800 0 0 3 &mpic 3 1
-				09800 0 0 4 &mpic 0 1
-
-				/* IDSEL 0x14 (Slot 3) */
-				0a000 0 0 1 &mpic 2 1
-				0a000 0 0 2 &mpic 3 1
-				0a000 0 0 3 &mpic 0 1
-				0a000 0 0 4 &mpic 1 1
-
-				/* IDSEL 0x15 (Slot 4) */
-				0a800 0 0 1 &mpic 3 1
-				0a800 0 0 2 &mpic 0 1
-				0a800 0 0 3 &mpic 1 1
-				0a800 0 0 4 &mpic 2 1
-
-				/* Bus 1 (Tundra Bridge) */
-				/* IDSEL 0x12 (ISA bridge) */
-				19000 0 0 1 &mpic 0 1
-				19000 0 0 2 &mpic 1 1
-				19000 0 0 3 &mpic 2 1
-				19000 0 0 4 &mpic 3 1>;
 			interrupt-parent = <&mpic>;
 			interrupts = <18 2>;
 			bus-range = <0 0>;
-			ranges = <02000000 0 80000000 80000000 0 20000000
-				  01000000 0 00000000 e2000000 0 00100000>;
+			ranges = <02000000 0 80000000 80000000 0 10000000
+				  01000000 0 00000000 e2000000 0 00800000>;
 			clock-frequency = <3f940aa>;
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <8000 1000>;
-			compatible = "85xx";
+			compatible = "fsl,mpc85xx-pci","85xx";
 			device_type = "pci";
 
-			i8259@19000 {
+			i8259@4 {
 				clock-frequency = <0>;
 				interrupt-controller;
 				device_type = "interrupt-controller";
-				reg = <19000 0 0 0 1>;
+				reg = <12000 0 0 0 1>;
 				#address-cells = <0>;
 				#interrupt-cells = <2>;
 				built-in;
@@ -266,17 +295,42 @@
 				a800 0 0 2 &mpic b 1
 				a800 0 0 3 &mpic b 1
 				a800 0 0 4 &mpic b 1>;
+
 			interrupt-parent = <&mpic>;
 			interrupts = <19 2>;
 			bus-range = <0 0>;
-			ranges = <02000000 0 a0000000 a0000000 0 20000000
-				  01000000 0 00000000 e3000000 0 00100000>;
+			ranges = <02000000 0 90000000 90000000 0 10000000
+				  01000000 0 00000000 e2800000 0 00800000>;
 			clock-frequency = <3f940aa>;
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <9000 1000>;
-			compatible = "85xx";
+			compatible = "fsl,mpc85xx-pci","85xx";
+			device_type = "pci";
+		};
+		/* PCI Express */
+		pci@a000 {
+			interrupt-map-mask = <f800 0 0 7>;
+			interrupt-map = <
+
+				/* IDSEL 0x0 (PEX) */
+				00000 0 0 1 &mpic 0 1
+				00000 0 0 2 &mpic 1 0
+				00000 0 0 3 &mpic 2 0
+				00000 0 0 4 &mpic 3 0>;
+
+			interrupt-parent = <&mpic>;
+			interrupts = <1a 2>;
+			bus-range = <0 ff>;
+			ranges = <02000000 0 a0000000 a0000000 0 20000000
+				  01000000 0 00000000 e3000000 0 08000000>;
+			clock-frequency = <1fca055>;
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			reg = <a000 1000>;
+			compatible = "fsl,mpc86xx-pciex","86xx";
 			device_type = "pci";
 		};
 
-- 
1.5.1

Re: [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[Segher Boessenkool]

>  		pci1: pci@8000 {
>  			interrupt-map-mask = <1f800 0 0 7>;

Set the mask to <1800 0 0 7>, and you need only 16
entries to encode the swizzle.  Except...

> +				/* bus 1 , idsel 0x2 Tsi310 bridge secondary */

...interrupts on bus 1 should be swizzled on bus 1, not
at the PHB.  Really.  It is a horrible workaround for a
non-existing problem to do it here, and I promise you
it _will_ come back to hurt you later.  Not a threat,
just a promise :-)

> -			compatible = "85xx";
> +			compatible = "fsl,mpc85xx-pci","85xx";

No more "xx" please...

> +		pci@a000 {
> +			interrupt-map-mask = <f800 0 0 7>;
> +			interrupt-map = <
> +
> +				/* IDSEL 0x0 (PEX) */
> +				00000 0 0 1 &mpic 0 1
> +				00000 0 0 2 &mpic 1 0
> +				00000 0 0 3 &mpic 2 0
> +				00000 0 0 4 &mpic 3 0>;

Why sense 0 for all but the first entry in this map?

> +			compatible = "fsl,mpc86xx-pciex","86xx";

And "xx" again.  Aren't the 85- and 86- PCIe controllers
compatible, btw?


Segher

Re: [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[Kumar Gala]

On Jul 10, 2007, at 3:25 PM, Segher Boessenkool wrote:

>>  		pci1: pci@8000 {
>>  			interrupt-map-mask = <1f800 0 0 7>;
>
> Set the mask to <1800 0 0 7>, and you need only 16
> entries to encode the swizzle.  Except...
>
>> +				/* bus 1 , idsel 0x2 Tsi310 bridge secondary */
>
> ...interrupts on bus 1 should be swizzled on bus 1, not
> at the PHB.  Really.  It is a horrible workaround for a
> non-existing problem to do it here, and I promise you
> it _will_ come back to hurt you later.  Not a threat,
> just a promise :-)
>
>> -			compatible = "85xx";
>> +			compatible = "fsl,mpc85xx-pci","85xx";
>
> No more "xx" please...
>
>> +		pci@a000 {
>> +			interrupt-map-mask = <f800 0 0 7>;
>> +			interrupt-map = <
>> +
>> +				/* IDSEL 0x0 (PEX) */
>> +				00000 0 0 1 &mpic 0 1
>> +				00000 0 0 2 &mpic 1 0
>> +				00000 0 0 3 &mpic 2 0
>> +				00000 0 0 4 &mpic 3 0>;
>
> Why sense 0 for all but the first entry in this map?
>
>> +			compatible = "fsl,mpc86xx-pciex","86xx";
>
> And "xx" again.  Aren't the 85- and 86- PCIe controllers
> compatible, btw?

They are, but we need to distinguish between 83xx, 85xx, and 86xx  
pci, pciex, pci-x controllers.

- k

Re: [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[Segher Boessenkool]

>>> +			compatible = "fsl,mpc86xx-pciex","86xx";
>>
>> And "xx" again.  Aren't the 85- and 86- PCIe controllers
>> compatible, btw?
>
> They are, but we need to distinguish between 83xx, 85xx, and 86xx  
> pci, pciex, pci-x controllers.

Sure, but if 85xx-pcie and 86xx-pcie are compatible, the OS
driver can match on the same "compatible" entry for both.
Just choose one -- "fsl,8641-pcie" or something.  It is a
good idea to put the exact name of the controller on the
board in the first "compatible" entry in case it is found
later that some specific model needs a workaround or some
other special treatment, but in general, everything can
just use the generic "grandfather" model to match on.


Segher

Re: [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[Zang Roy-r61911]

On Wed, 2007-07-11 at 04:25, Segher Boessenkool wrote:
> >               pci1: pci@8000 {
> >                       interrupt-map-mask = <1f800 0 0 7>;
> 
> Set the mask to <1800 0 0 7>, and you need only 16
> entries to encode the swizzle.  Except...
> 
> > +                             /* bus 1 , idsel 0x2 Tsi310 bridge
> secondary */
> 
> ...interrupts on bus 1 should be swizzled on bus 1, not
> at the PHB.  Really.  It is a horrible workaround for a
> non-existing problem to do it here, and I promise you
> it _will_ come back to hurt you later.  Not a threat,
> just a promise :-)

I just want to make it as a temporary workaround now.
Extra patches will be provided to fix it.


> > -                     compatible = "85xx";
> > +                     compatible = "fsl,mpc85xx-pci","85xx";
> 
> No more "xx" please...
> 
> > +             pci@a000 {
> > +                     interrupt-map-mask = <f800 0 0 7>;
> > +                     interrupt-map = <
> > +
> > +                             /* IDSEL 0x0 (PEX) */
> > +                             00000 0 0 1 &mpic 0 1
> > +                             00000 0 0 2 &mpic 1 0
> > +                             00000 0 0 3 &mpic 2 0
> > +                             00000 0 0 4 &mpic 3 0>;
> 
> Why sense 0 for all but the first entry in this map?
Now, only the first entry is used.
> 
> > +                     compatible = "fsl,mpc86xx-pciex","86xx";
> 
> And "xx" again.  Aren't the 85- and 86- PCIe controllers
> compatible, btw?

Re: [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[Segher Boessenkool]

>>>               pci1: pci@8000 {
>>>                       interrupt-map-mask = <1f800 0 0 7>;
>>
>> Set the mask to <1800 0 0 7>, and you need only 16
>> entries to encode the swizzle.  Except...
>>
>>> +                             /* bus 1 , idsel 0x2 Tsi310 bridge
>> secondary */
>>
>> ...interrupts on bus 1 should be swizzled on bus 1, not
>> at the PHB.  Really.  It is a horrible workaround for a
>> non-existing problem to do it here, and I promise you
>> it _will_ come back to hurt you later.  Not a threat,
>> just a promise :-)
>
> I just want to make it as a temporary workaround now.

That is fine.

> Extra patches will be provided to fix it.

Looking forward to it!

>>> +             pci@a000 {
>>> +                     interrupt-map-mask = <f800 0 0 7>;
>>> +                     interrupt-map = <
>>> +
>>> +                             /* IDSEL 0x0 (PEX) */
>>> +                             00000 0 0 1 &mpic 0 1
>>> +                             00000 0 0 2 &mpic 1 0
>>> +                             00000 0 0 3 &mpic 2 0
>>> +                             00000 0 0 4 &mpic 3 0>;
>>
>> Why sense 0 for all but the first entry in this map?
> Now, only the first entry is used.

Sure, but the other three entries are incorrect.  Either
provide correct entries, or just leave the unused entries
out of the map; if those three interrupts aren't wired up,
that is the right thing to do, too.


Segher

Re: [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[Kumar Gala]

>
>>>> +             pci@a000 {
>>>> +                     interrupt-map-mask = <f800 0 0 7>;
>>>> +                     interrupt-map = <
>>>> +
>>>> +                             /* IDSEL 0x0 (PEX) */
>>>> +                             00000 0 0 1 &mpic 0 1
>>>> +                             00000 0 0 2 &mpic 1 0
>>>> +                             00000 0 0 3 &mpic 2 0
>>>> +                             00000 0 0 4 &mpic 3 0>;
>>>
>>> Why sense 0 for all but the first entry in this map?
>> Now, only the first entry is used.
>
> Sure, but the other three entries are incorrect.  Either
> provide correct entries, or just leave the unused entries
> out of the map; if those three interrupts aren't wired up,
> that is the right thing to do, too.

Yeah these should be sense 1 for irq b, c, d.  I'll fix that up when  
I apply the patch.

- k

Re: [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[Zang Roy-r61911]

From: Roy Zang <tie-fei.zang@freescale.com>

Add 8548 CDS PCI express controller node and PCI-X device node.
The current  dts file is suitable for 8548 Rev 2.0 board with
Arcadia 3.1.
This kind of board combination is the most popular.

Indentify pci, pcie host by compatible property "fsl,mpc85xx-pci"
and "fsl, mpc85xx-pciex".

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
Fix the PCI Express b,c,d, irq sense.

 arch/powerpc/boot/dts/mpc8548cds.dts |  156 +++++++++++++++++++++++-----------
 1 files changed, 105 insertions(+), 51 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 9d0b84b..d60821b 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -1,5 +1,5 @@
 /*
- * MPC8555 CDS Device Tree Source
+ * MPC8548 CDS Device Tree Source
  *
  * Copyright 2006 Freescale Semiconductor Inc.
  *
@@ -186,67 +186,96 @@
 		pci1: pci@8000 {
 			interrupt-map-mask = <1f800 0 0 7>;
 			interrupt-map = <
+				/* IDSEL 0x4 (PCIX Slot 2) */
+				02000 0 0 1 &mpic 0 1
+				02000 0 0 2 &mpic 1 1
+				02000 0 0 3 &mpic 2 1
+				02000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0x5 (PCIX Slot 3) */
+				02800 0 0 1 &mpic 1 1
+				02800 0 0 2 &mpic 2 1
+				02800 0 0 3 &mpic 3 1
+				02800 0 0 4 &mpic 0 1
+
+				/* IDSEL 0x6 (PCIX Slot 4) */
+				03000 0 0 1 &mpic 2 1
+				03000 0 0 2 &mpic 3 1
+				03000 0 0 3 &mpic 0 1
+				03000 0 0 4 &mpic 1 1
+
+				/* IDSEL 0x8 (PCIX Slot 5) */
+				04000 0 0 1 &mpic 0 1
+				04000 0 0 2 &mpic 1 1
+				04000 0 0 3 &mpic 2 1
+				04000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0xC (Tsi310 bridge) */
+				06000 0 0 1 &mpic 0 1
+				06000 0 0 2 &mpic 1 1
+				06000 0 0 3 &mpic 2 1
+				06000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0x14 (Slot 2) */
+				0a000 0 0 1 &mpic 0 1
+				0a000 0 0 2 &mpic 1 1
+				0a000 0 0 3 &mpic 2 1
+				0a000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0x15 (Slot 3) */
+				0a800 0 0 1 &mpic 1 1
+				0a800 0 0 2 &mpic 2 1
+				0a800 0 0 3 &mpic 3 1
+				0a800 0 0 4 &mpic 0 1
+
+				/* IDSEL 0x16 (Slot 4) */
+				0b000 0 0 1 &mpic 2 1
+				0b000 0 0 2 &mpic 3 1
+				0b000 0 0 3 &mpic 0 1
+				0b000 0 0 4 &mpic 1 1
+
+				/* IDSEL 0x18 (Slot 5) */
+				0c000 0 0 1 &mpic 0 1
+				0c000 0 0 2 &mpic 1 1
+				0c000 0 0 3 &mpic 2 1
+				0c000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
+				0E000 0 0 1 &mpic 0 1
+				0E000 0 0 2 &mpic 1 1
+				0E000 0 0 3 &mpic 2 1
+				0E000 0 0 4 &mpic 3 1
+
+				/* bus 1 , idsel 0x2 Tsi310 bridge secondary */
+				11000 0 0 1 &mpic 2 1
+				11000 0 0 2 &mpic 3 1
+				11000 0 0 3 &mpic 0 1
+				11000 0 0 4 &mpic 1 1
+
+				/* VIA chip */
+				12000 0 0 1 &mpic 0 1
+				12000 0 0 2 &mpic 1 1
+				12000 0 0 3 &mpic 2 1
+				12000 0 0 4 &mpic 3 1>;
 
-				/* IDSEL 0x10 */
-				08000 0 0 1 &mpic 0 1
-				08000 0 0 2 &mpic 1 1
-				08000 0 0 3 &mpic 2 1
-				08000 0 0 4 &mpic 3 1
-
-				/* IDSEL 0x11 */
-				08800 0 0 1 &mpic 0 1
-				08800 0 0 2 &mpic 1 1
-				08800 0 0 3 &mpic 2 1
-				08800 0 0 4 &mpic 3 1
-
-				/* IDSEL 0x12 (Slot 1) */
-				09000 0 0 1 &mpic 0 1
-				09000 0 0 2 &mpic 1 1
-				09000 0 0 3 &mpic 2 1
-				09000 0 0 4 &mpic 3 1
-
-				/* IDSEL 0x13 (Slot 2) */
-				09800 0 0 1 &mpic 1 1
-				09800 0 0 2 &mpic 2 1
-				09800 0 0 3 &mpic 3 1
-				09800 0 0 4 &mpic 0 1
-
-				/* IDSEL 0x14 (Slot 3) */
-				0a000 0 0 1 &mpic 2 1
-				0a000 0 0 2 &mpic 3 1
-				0a000 0 0 3 &mpic 0 1
-				0a000 0 0 4 &mpic 1 1
-
-				/* IDSEL 0x15 (Slot 4) */
-				0a800 0 0 1 &mpic 3 1
-				0a800 0 0 2 &mpic 0 1
-				0a800 0 0 3 &mpic 1 1
-				0a800 0 0 4 &mpic 2 1
-
-				/* Bus 1 (Tundra Bridge) */
-				/* IDSEL 0x12 (ISA bridge) */
-				19000 0 0 1 &mpic 0 1
-				19000 0 0 2 &mpic 1 1
-				19000 0 0 3 &mpic 2 1
-				19000 0 0 4 &mpic 3 1>;
 			interrupt-parent = <&mpic>;
 			interrupts = <18 2>;
 			bus-range = <0 0>;
-			ranges = <02000000 0 80000000 80000000 0 20000000
-				  01000000 0 00000000 e2000000 0 00100000>;
+			ranges = <02000000 0 80000000 80000000 0 10000000
+				  01000000 0 00000000 e2000000 0 00800000>;
 			clock-frequency = <3f940aa>;
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <8000 1000>;
-			compatible = "85xx";
+			compatible = "fsl,mpc85xx-pci","85xx";
 			device_type = "pci";
 
-			i8259@19000 {
+			i8259@4 {
 				clock-frequency = <0>;
 				interrupt-controller;
 				device_type = "interrupt-controller";
-				reg = <19000 0 0 0 1>;
+				reg = <12000 0 0 0 1>;
 				#address-cells = <0>;
 				#interrupt-cells = <2>;
 				built-in;
@@ -266,17 +295,42 @@
 				a800 0 0 2 &mpic b 1
 				a800 0 0 3 &mpic b 1
 				a800 0 0 4 &mpic b 1>;
+
 			interrupt-parent = <&mpic>;
 			interrupts = <19 2>;
 			bus-range = <0 0>;
-			ranges = <02000000 0 a0000000 a0000000 0 20000000
-				  01000000 0 00000000 e3000000 0 00100000>;
+			ranges = <02000000 0 90000000 90000000 0 10000000
+				  01000000 0 00000000 e2800000 0 00800000>;
 			clock-frequency = <3f940aa>;
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <9000 1000>;
-			compatible = "85xx";
+			compatible = "fsl,mpc85xx-pci","85xx";
+			device_type = "pci";
+		};
+		/* PCI Express */
+		pci@a000 {
+			interrupt-map-mask = <f800 0 0 7>;
+			interrupt-map = <
+
+				/* IDSEL 0x0 (PEX) */
+				00000 0 0 1 &mpic 0 1
+				00000 0 0 2 &mpic 1 1
+				00000 0 0 3 &mpic 2 1
+				00000 0 0 4 &mpic 3 1>;
+
+			interrupt-parent = <&mpic>;
+			interrupts = <1a 2>;
+			bus-range = <0 ff>;
+			ranges = <02000000 0 a0000000 a0000000 0 20000000
+				  01000000 0 00000000 e3000000 0 08000000>;
+			clock-frequency = <1fca055>;
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			reg = <a000 1000>;
+			compatible = "fsl,mpc86xx-pciex","86xx";
 			device_type = "pci";
 		};
 
-- 
1.5.1

Re: [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[Kumar Gala]

On Jul 12, 2007, at 3:27 AM, Zang Roy-r61911 wrote:

> From: Roy Zang <tie-fei.zang@freescale.com>
>
> Add 8548 CDS PCI express controller node and PCI-X device node.
> The current  dts file is suitable for 8548 Rev 2.0 board with
> Arcadia 3.1.
> This kind of board combination is the most popular.
>
> Indentify pci, pcie host by compatible property "fsl,mpc85xx-pci"
> and "fsl, mpc85xx-pciex".
>
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> ---
> Fix the PCI Express b,c,d, irq sense.

is this the only fix, I've already applied a version of this to my  
tree (with the irq sense fix) and just want to make sure there isn't  
anything else.

- k

Re: [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[Zang Roy-r61911]

On Thu, 2007-07-12 at 17:00, Kumar Gala wrote:
> On Jul 12, 2007, at 3:27 AM, Zang Roy-r61911 wrote:
> 
> > From: Roy Zang <tie-fei.zang@freescale.com>
> >
> > Add 8548 CDS PCI express controller node and PCI-X device node.
> > The current  dts file is suitable for 8548 Rev 2.0 board with
> > Arcadia 3.1.
> > This kind of board combination is the most popular.
> >
> > Indentify pci, pcie host by compatible property "fsl,mpc85xx-pci"
> > and "fsl, mpc85xx-pciex".
> >
> > Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> > ---
> > Fix the PCI Express b,c,d, irq sense.
> 
> is this the only fix, I've already applied a version of this to my  
> tree (with the irq sense fix) and just want to make sure there isn't  
> anything else.
I do not get more.
I'd like to enroll Segher's suggestion together with VIA chip function
in next step.
We need to make basic pcie work on 8548 CDS board first.
Thanks.

Roy

Re: [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[Segher Boessenkool]

>> is this the only fix, I've already applied a version of this to my
>> tree (with the irq sense fix) and just want to make sure there isn't
>> anything else.
> I do not get more.
> I'd like to enroll Segher's suggestion together with VIA chip function
> in next step.
> We need to make basic pcie work on 8548 CDS board first.

If you can, please make the "compatible" properties correct
("pcie" instead of "pciex") before the patch goes in; it'll
be less work total and less confusing in the end.


Segher

Re: [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[Kumar Gala]

On Jul 16, 2007, at 8:05 AM, Segher Boessenkool wrote:

>>> is this the only fix, I've already applied a version of this to my
>>> tree (with the irq sense fix) and just want to make sure there isn't
>>> anything else.
>> I do not get more.
>> I'd like to enroll Segher's suggestion together with VIA chip  
>> function
>> in next step.
>> We need to make basic pcie work on 8548 CDS board first.
>
> If you can, please make the "compatible" properties correct
> ("pcie" instead of "pciex") before the patch goes in; it'll
> be less work total and less confusing in the end.

I've taken care of that as well.

They are now 'fsl,mpc8548-pcie, and 'fsl,mpc8641-pcie'

- k

Re: [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[Segher Boessenkool]

>>>> is this the only fix, I've already applied a version of this to my
>>>> tree (with the irq sense fix) and just want to make sure there  
>>>> isn't
>>>> anything else.
>>> I do not get more.
>>> I'd like to enroll Segher's suggestion together with VIA chip  
>>> function
>>> in next step.
>>> We need to make basic pcie work on 8548 CDS board first.
>>
>> If you can, please make the "compatible" properties correct
>> ("pcie" instead of "pciex") before the patch goes in; it'll
>> be less work total and less confusing in the end.
>
> I've taken care of that as well.
>
> They are now 'fsl,mpc8548-pcie, and 'fsl,mpc8641-pcie'

Perfect, thanks!


Segher

Re: [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node

[Zang Roy-r61911]

On Mon, 2007-07-16 at 23:00, Segher Boessenkool wrote:
> >>>> is this the only fix, I've already applied a version of this to
> my
> >>>> tree (with the irq sense fix) and just want to make sure there  
> >>>> isn't
> >>>> anything else.
> >>> I do not get more.
> >>> I'd like to enroll Segher's suggestion together with VIA chip  
> >>> function
> >>> in next step.
> >>> We need to make basic pcie work on 8548 CDS board first.
> >>
> >> If you can, please make the "compatible" properties correct
> >> ("pcie" instead of "pciex") before the patch goes in; it'll
> >> be less work total and less confusing in the end.
> >
> > I've taken care of that as well.
> >
> > They are now 'fsl,mpc8548-pcie, and 'fsl,mpc8641-pcie'
> 
> Perfect, thanks!
I noticed Kumar made some modifications according to the feedback, when
he applied the patch.
Thanks!
Roy