* [PATCH 00/25] Freescale PCI/PCIe support/fixup/cleanup
@ 2007-07-23 20:49 Kumar Gala
2007-07-23 20:49 ` [PATCH 01/25] [POWERPC] Create common fsl pci/e files based on 86xx platforms Kumar Gala
0 siblings, 1 reply; 39+ messages in thread
From: Kumar Gala @ 2007-07-23 20:49 UTC (permalink / raw)
To: Benjamin Herrenschmidt, linuxppc-dev
This set of patches is queued up for 2.6.23-rc1 that add support
for PCI, PCI-X, PCIe for Freescale 8{5,6}xxx processors/boards.
There are also some misc other PPC PCI cleanups in here.
- k
^ permalink raw reply [flat|nested] 39+ messages in thread* [PATCH 01/25] [POWERPC] Create common fsl pci/e files based on 86xx platforms 2007-07-23 20:49 [PATCH 00/25] Freescale PCI/PCIe support/fixup/cleanup Kumar Gala @ 2007-07-23 20:49 ` Kumar Gala 2007-07-23 20:49 ` [PATCH 02/25] [POWERPC] Rewrite Freescale PCI/PCIe support for 8{3, 5, 6}xx Kumar Gala 0 siblings, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:49 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev From: Roy Zang <tie-fei.zang@freescale.com> Move arch/powerpc/platforms/86xx/pci.c -> arch/powerpc/sysdev/fsl_pci.c arch/powerpc/sysdev/fsl_pcie.h -> arch/powerpc/sysdev/fsl_pci.h as the base to unify 83xx/85xx/86xx pci and pcie. Add CONFIG_FSL_PCI to build fsl_pci.c for Freescale pci and pcie option. The code still works for 86xx platforms. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/Kconfig | 4 + arch/powerpc/platforms/86xx/Kconfig | 4 +- arch/powerpc/platforms/86xx/Makefile | 1 - arch/powerpc/platforms/86xx/pci.c | 238 ---------------------------------- arch/powerpc/sysdev/Makefile | 1 + arch/powerpc/sysdev/fsl_pci.c | 238 ++++++++++++++++++++++++++++++++++ arch/powerpc/sysdev/fsl_pci.h | 94 +++++++++++++ arch/powerpc/sysdev/fsl_pcie.h | 94 ------------- 8 files changed, 339 insertions(+), 335 deletions(-) delete mode 100644 arch/powerpc/platforms/86xx/pci.c create mode 100644 arch/powerpc/sysdev/fsl_pci.c create mode 100644 arch/powerpc/sysdev/fsl_pci.h delete mode 100644 arch/powerpc/sysdev/fsl_pcie.h diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 853c282..3ff90f0 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -425,6 +425,10 @@ config SBUS config FSL_SOC bool +config FSL_PCI + bool + select PPC_INDIRECT_PCI + # Yes MCA RS/6000s exist but Linux-PPC does not currently support any config MCA bool diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig index 0faebfd..d1c8115 100644 --- a/arch/powerpc/platforms/86xx/Kconfig +++ b/arch/powerpc/platforms/86xx/Kconfig @@ -14,8 +14,8 @@ endchoice config MPC8641 bool - select PPC_INDIRECT_PCI - select PPC_INDIRECT_PCI_BE + select PPC_INDIRECT_PCI_BE if PCI + select FSL_PCI if PCI select PPC_UDBG_16550 select MPIC default y if MPC8641_HPCN diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile index 418fd8f..3376c77 100644 --- a/arch/powerpc/platforms/86xx/Makefile +++ b/arch/powerpc/platforms/86xx/Makefile @@ -4,4 +4,3 @@ obj-$(CONFIG_SMP) += mpc86xx_smp.o obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c deleted file mode 100644 index 73cd5b0..0000000 --- a/arch/powerpc/platforms/86xx/pci.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * MPC86XX pci setup code - * - * Recode: ZHANG WEI <wei.zhang@freescale.com> - * Initial author: Xianghua Xiao <x.xiao@freescale.com> - * - * Copyright 2006 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/types.h> -#include <linux/module.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/serial.h> - -#include <asm/system.h> -#include <asm/atomic.h> -#include <asm/io.h> -#include <asm/prom.h> -#include <asm/pci-bridge.h> -#include <sysdev/fsl_soc.h> -#include <sysdev/fsl_pcie.h> - -#include "mpc86xx.h" - -#undef DEBUG - -#ifdef DEBUG -#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) -#else -#define DBG(fmt, args...) -#endif - -struct pcie_outbound_window_regs { - uint pexotar; /* 0x.0 - PCI Express outbound translation address register */ - uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */ - uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */ - char res1[4]; - uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */ - char res2[12]; -}; - -struct pcie_inbound_window_regs { - uint pexitar; /* 0x.0 - PCI Express inbound translation address register */ - char res1[4]; - uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */ - uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */ - uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */ - char res2[12]; -}; - -static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc) -{ - volatile struct ccsr_pex *pcie; - volatile struct pcie_outbound_window_regs *pcieow; - volatile struct pcie_inbound_window_regs *pcieiw; - int i = 0; - - DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start, - rsrc->end - rsrc->start + 1); - pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); - - /* Disable all windows (except pexowar0 since its ignored) */ - pcie->pexowar1 = 0; - pcie->pexowar2 = 0; - pcie->pexowar3 = 0; - pcie->pexowar4 = 0; - pcie->pexiwar1 = 0; - pcie->pexiwar2 = 0; - pcie->pexiwar3 = 0; - - pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1; - pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1; - - /* Setup outbound MEM window */ - for(i = 0; i < 3; i++) - if (hose->mem_resources[i].flags & IORESOURCE_MEM){ - DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n", - hose->mem_resources[i].start, - hose->mem_resources[i].end - - hose->mem_resources[i].start + 1); - pcieow->pexotar = (hose->mem_resources[i].start) >> 12 - & 0x000fffff; - pcieow->pexotear = 0; - pcieow->pexowbar = (hose->mem_resources[i].start) >> 12 - & 0x000fffff; - /* Enable, Mem R/W */ - pcieow->pexowar = 0x80044000 | - (__ilog2(hose->mem_resources[i].end - - hose->mem_resources[i].start + 1) - - 1); - pcieow++; - } - - /* Setup outbound IO window */ - if (hose->io_resource.flags & IORESOURCE_IO){ - DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", - hose->io_resource.start, - hose->io_resource.end - hose->io_resource.start + 1, - hose->io_base_phys); - pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff; - pcieow->pexotear = 0; - pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff; - /* Enable, IO R/W */ - pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end - - hose->io_resource.start + 1) - 1); - } - - /* Setup 2G inbound Memory Window @ 0 */ - pcieiw->pexitar = 0x00000000; - pcieiw->pexiwbar = 0x00000000; - /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */ - pcieiw->pexiwar = 0xa0f5501e; -} - -static void __init -mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size) -{ - u16 cmd; - - DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n", - pcie_offset, pcie_size); - - early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); - cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY - | PCI_COMMAND_IO; - early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); - - early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); -} - -static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) -{ - struct resource *res; - int i, res_idx = PCI_BRIDGE_RESOURCES; - struct pci_controller *hose; - - /* - * Make the bridge be transparent. - */ - dev->transparent = 1; - - hose = pci_bus_to_host(dev->bus); - if (!hose) { - printk(KERN_ERR "Can't find hose for bus %d\n", - dev->bus->number); - return; - } - - if (hose->io_resource.flags) { - res = &dev->resource[res_idx++]; - res->start = hose->io_resource.start; - res->end = hose->io_resource.end; - res->flags = hose->io_resource.flags; - } - - for (i = 0; i < 3; i++) { - res = &dev->resource[res_idx + i]; - res->start = hose->mem_resources[i].start; - res->end = hose->mem_resources[i].end; - res->flags = hose->mem_resources[i].flags; - } -} - - -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); - -#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */ -#define PCIE_LTSSM_L0 0x16 /* L0 state */ - -int __init mpc86xx_add_bridge(struct device_node *dev) -{ - int len; - struct pci_controller *hose; - struct resource rsrc; - const int *bus_range; - int has_address = 0; - int primary = 0; - u16 val; - - DBG("Adding PCIE host bridge %s\n", dev->full_name); - - /* Fetch host bridge registers address */ - has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); - - /* Get bus range if any */ - bus_range = of_get_property(dev, "bus-range", &len); - if (bus_range == NULL || len < 2 * sizeof(int)) - printk(KERN_WARNING "Can't get bus-range for %s, assume" - " bus 0\n", dev->full_name); - - pci_assign_all_buses = 1; - hose = pcibios_alloc_controller(dev); - if (!hose) - return -ENOMEM; - - hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | - PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; - - hose->first_busno = bus_range ? bus_range[0] : 0x0; - hose->last_busno = bus_range ? bus_range[1] : 0xff; - - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); - - /* Probe the hose link training status */ - early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); - if (val < PCIE_LTSSM_L0) - return -ENXIO; - - /* Setup the PCIE host controller. */ - mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1); - - if ((rsrc.start & 0xfffff) == 0x8000) - primary = 1; - - printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. " - "Firmware bus number: %d->%d\n", - (unsigned long) rsrc.start, - hose->first_busno, hose->last_busno); - - DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", - hose, hose->cfg_addr, hose->cfg_data); - - /* Interpret the "ranges" property */ - /* This also maps the I/O region and sets isa_io/mem_base */ - pci_process_bridge_OF_ranges(hose, dev, primary); - - /* Setup PEX window registers */ - setup_pcie_atmu(hose, &rsrc); - - return 0; -} diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile index 484eb4e..08ce31e 100644 --- a/arch/powerpc/sysdev/Makefile +++ b/arch/powerpc/sysdev/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PPC_PMI) += pmi.o obj-$(CONFIG_U3_DART) += dart_iommu.o obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o obj-$(CONFIG_FSL_SOC) += fsl_soc.o +obj-$(CONFIG_FSL_PCI) += fsl_pci.o obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ mv64x60-$(CONFIG_PCI) += mv64x60_pci.o diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c new file mode 100644 index 0000000..24ba1b6 --- /dev/null +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -0,0 +1,238 @@ +/* + * MPC86XX pci setup code + * + * Recode: ZHANG WEI <wei.zhang@freescale.com> + * Initial author: Xianghua Xiao <x.xiao@freescale.com> + * + * Copyright 2006 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/types.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/pci.h> +#include <linux/serial.h> + +#include <asm/system.h> +#include <asm/atomic.h> +#include <asm/io.h> +#include <asm/prom.h> +#include <asm/pci-bridge.h> +#include <sysdev/fsl_soc.h> +#include <sysdev/fsl_pci.h> + +#include "../platforms/86xx/mpc86xx.h" + +#undef DEBUG + +#ifdef DEBUG +#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) +#else +#define DBG(fmt, args...) +#endif + +struct pcie_outbound_window_regs { + uint pexotar; /* 0x.0 - PCI Express outbound translation address register */ + uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */ + uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */ + char res1[4]; + uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */ + char res2[12]; +}; + +struct pcie_inbound_window_regs { + uint pexitar; /* 0x.0 - PCI Express inbound translation address register */ + char res1[4]; + uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */ + uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */ + uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */ + char res2[12]; +}; + +static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc) +{ + volatile struct ccsr_pex *pcie; + volatile struct pcie_outbound_window_regs *pcieow; + volatile struct pcie_inbound_window_regs *pcieiw; + int i = 0; + + DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start, + rsrc->end - rsrc->start + 1); + pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); + + /* Disable all windows (except pexowar0 since its ignored) */ + pcie->pexowar1 = 0; + pcie->pexowar2 = 0; + pcie->pexowar3 = 0; + pcie->pexowar4 = 0; + pcie->pexiwar1 = 0; + pcie->pexiwar2 = 0; + pcie->pexiwar3 = 0; + + pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1; + pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1; + + /* Setup outbound MEM window */ + for(i = 0; i < 3; i++) + if (hose->mem_resources[i].flags & IORESOURCE_MEM){ + DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n", + hose->mem_resources[i].start, + hose->mem_resources[i].end + - hose->mem_resources[i].start + 1); + pcieow->pexotar = (hose->mem_resources[i].start) >> 12 + & 0x000fffff; + pcieow->pexotear = 0; + pcieow->pexowbar = (hose->mem_resources[i].start) >> 12 + & 0x000fffff; + /* Enable, Mem R/W */ + pcieow->pexowar = 0x80044000 | + (__ilog2(hose->mem_resources[i].end + - hose->mem_resources[i].start + 1) + - 1); + pcieow++; + } + + /* Setup outbound IO window */ + if (hose->io_resource.flags & IORESOURCE_IO){ + DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", + hose->io_resource.start, + hose->io_resource.end - hose->io_resource.start + 1, + hose->io_base_phys); + pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff; + pcieow->pexotear = 0; + pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff; + /* Enable, IO R/W */ + pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end + - hose->io_resource.start + 1) - 1); + } + + /* Setup 2G inbound Memory Window @ 0 */ + pcieiw->pexitar = 0x00000000; + pcieiw->pexiwbar = 0x00000000; + /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */ + pcieiw->pexiwar = 0xa0f5501e; +} + +static void __init +mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size) +{ + u16 cmd; + + DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n", + pcie_offset, pcie_size); + + early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY + | PCI_COMMAND_IO; + early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); + + early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); +} + +static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) +{ + struct resource *res; + int i, res_idx = PCI_BRIDGE_RESOURCES; + struct pci_controller *hose; + + /* + * Make the bridge be transparent. + */ + dev->transparent = 1; + + hose = pci_bus_to_host(dev->bus); + if (!hose) { + printk(KERN_ERR "Can't find hose for bus %d\n", + dev->bus->number); + return; + } + + if (hose->io_resource.flags) { + res = &dev->resource[res_idx++]; + res->start = hose->io_resource.start; + res->end = hose->io_resource.end; + res->flags = hose->io_resource.flags; + } + + for (i = 0; i < 3; i++) { + res = &dev->resource[res_idx + i]; + res->start = hose->mem_resources[i].start; + res->end = hose->mem_resources[i].end; + res->flags = hose->mem_resources[i].flags; + } +} + + +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); + +#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */ +#define PCIE_LTSSM_L0 0x16 /* L0 state */ + +int __init mpc86xx_add_bridge(struct device_node *dev) +{ + int len; + struct pci_controller *hose; + struct resource rsrc; + const int *bus_range; + int has_address = 0; + int primary = 0; + u16 val; + + DBG("Adding PCIE host bridge %s\n", dev->full_name); + + /* Fetch host bridge registers address */ + has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); + + /* Get bus range if any */ + bus_range = of_get_property(dev, "bus-range", &len); + if (bus_range == NULL || len < 2 * sizeof(int)) + printk(KERN_WARNING "Can't get bus-range for %s, assume" + " bus 0\n", dev->full_name); + + pci_assign_all_buses = 1; + hose = pcibios_alloc_controller(dev); + if (!hose) + return -ENOMEM; + + hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | + PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; + + hose->first_busno = bus_range ? bus_range[0] : 0x0; + hose->last_busno = bus_range ? bus_range[1] : 0xff; + + setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); + + /* Probe the hose link training status */ + early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); + if (val < PCIE_LTSSM_L0) + return -ENXIO; + + /* Setup the PCIE host controller. */ + mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1); + + if ((rsrc.start & 0xfffff) == 0x8000) + primary = 1; + + printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. " + "Firmware bus number: %d->%d\n", + (unsigned long) rsrc.start, + hose->first_busno, hose->last_busno); + + DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", + hose, hose->cfg_addr, hose->cfg_data); + + /* Interpret the "ranges" property */ + /* This also maps the I/O region and sets isa_io/mem_base */ + pci_process_bridge_OF_ranges(hose, dev, primary); + + /* Setup PEX window registers */ + setup_pcie_atmu(hose, &rsrc); + + return 0; +} diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h new file mode 100644 index 0000000..8d9779c --- /dev/null +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -0,0 +1,94 @@ +/* + * MPC85xx/86xx PCI Express structure define + * + * Copyright 2007 Freescale Semiconductor, Inc + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifdef __KERNEL__ +#ifndef __POWERPC_FSL_PCIE_H +#define __POWERPC_FSL_PCIE_H + +/* PCIE Express IO block registers in 85xx/86xx */ + +struct ccsr_pex { + __be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */ + __be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */ + u8 __iomem res1[4]; + __be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */ + __be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */ + u8 __iomem res2[12]; + __be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */ + __be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */ + __be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */ + __be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */ + u8 __iomem res3[3024]; + __be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */ + __be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/ + u8 __iomem res4[8]; + __be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/ + u8 __iomem res5[12]; + __be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */ + __be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/ + __be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/ + u8 __iomem res6[4]; + __be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/ + u8 __iomem res7[12]; + __be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */ + __be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/ + __be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/ + u8 __iomem res8[4]; + __be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/ + u8 __iomem res9[12]; + __be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */ + __be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/ + __be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/ + u8 __iomem res10[4]; + __be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/ + u8 __iomem res11[12]; + __be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */ + __be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/ + __be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/ + u8 __iomem res12[4]; + __be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/ + u8 __iomem res13[12]; + u8 __iomem res14[256]; + __be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */ + u8 __iomem res15[4]; + __be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */ + __be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */ + __be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */ + u8 __iomem res16[12]; + __be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */ + u8 __iomem res17[4]; + __be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */ + __be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */ + __be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */ + u8 __iomem res18[12]; + __be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */ + u8 __iomem res19[4]; + __be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */ + __be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */ + __be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */ + u8 __iomem res20[12]; + __be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */ + u8 __iomem res21[4]; + __be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */ + u8 __iomem res22[4]; + __be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */ + u8 __iomem res23[12]; + __be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */ + u8 __iomem res24[4]; + __be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */ + __be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */ + __be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */ + __be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */ +}; + +#endif /* __POWERPC_FSL_PCIE_H */ +#endif /* __KERNEL__ */ diff --git a/arch/powerpc/sysdev/fsl_pcie.h b/arch/powerpc/sysdev/fsl_pcie.h deleted file mode 100644 index 8d9779c..0000000 --- a/arch/powerpc/sysdev/fsl_pcie.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * MPC85xx/86xx PCI Express structure define - * - * Copyright 2007 Freescale Semiconductor, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifdef __KERNEL__ -#ifndef __POWERPC_FSL_PCIE_H -#define __POWERPC_FSL_PCIE_H - -/* PCIE Express IO block registers in 85xx/86xx */ - -struct ccsr_pex { - __be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */ - __be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */ - u8 __iomem res1[4]; - __be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */ - __be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */ - u8 __iomem res2[12]; - __be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */ - __be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */ - __be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */ - __be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */ - u8 __iomem res3[3024]; - __be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */ - __be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/ - u8 __iomem res4[8]; - __be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/ - u8 __iomem res5[12]; - __be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */ - __be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/ - __be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/ - u8 __iomem res6[4]; - __be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/ - u8 __iomem res7[12]; - __be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */ - __be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/ - __be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/ - u8 __iomem res8[4]; - __be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/ - u8 __iomem res9[12]; - __be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */ - __be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/ - __be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/ - u8 __iomem res10[4]; - __be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/ - u8 __iomem res11[12]; - __be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */ - __be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/ - __be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/ - u8 __iomem res12[4]; - __be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/ - u8 __iomem res13[12]; - u8 __iomem res14[256]; - __be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */ - u8 __iomem res15[4]; - __be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */ - __be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */ - __be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */ - u8 __iomem res16[12]; - __be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */ - u8 __iomem res17[4]; - __be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */ - __be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */ - __be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */ - u8 __iomem res18[12]; - __be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */ - u8 __iomem res19[4]; - __be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */ - __be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */ - __be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */ - u8 __iomem res20[12]; - __be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */ - u8 __iomem res21[4]; - __be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */ - u8 __iomem res22[4]; - __be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */ - u8 __iomem res23[12]; - __be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */ - u8 __iomem res24[4]; - __be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */ - __be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */ - __be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */ - __be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */ -}; - -#endif /* __POWERPC_FSL_PCIE_H */ -#endif /* __KERNEL__ */ -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 02/25] [POWERPC] Rewrite Freescale PCI/PCIe support for 8{3, 5, 6}xx 2007-07-23 20:49 ` [PATCH 01/25] [POWERPC] Create common fsl pci/e files based on 86xx platforms Kumar Gala @ 2007-07-23 20:49 ` Kumar Gala 2007-07-23 20:49 ` [PATCH 03/25] [POWERPC] Add the ability to find PCI capabilities early on Kumar Gala 0 siblings, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:49 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev From: Zang Roy-r61911 <tie-fei.zang@freescale.com> Rewrite the Freescale PCI code to support PCI on 83xx/85xx/86xx and PCIe on 85xx/86xx. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/boot/dts/mpc8641_hpcn.dts | 8 +- arch/powerpc/platforms/86xx/mpc86xx.h | 5 - arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 11 +- arch/powerpc/sysdev/fsl_pci.c | 244 ++++++++++++---------------- arch/powerpc/sysdev/fsl_pci.h | 145 ++++++++--------- 5 files changed, 187 insertions(+), 226 deletions(-) diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts index 6a78a2b..5d82709 100644 --- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts +++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts @@ -211,8 +211,8 @@ interrupt-parent = <&mpic>; }; - pci@8000 { - compatible = "86xx"; + pcie@8000 { + compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; @@ -399,8 +399,8 @@ }; - pci@9000 { - compatible = "86xx"; + pcie@9000 { + compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; diff --git a/arch/powerpc/platforms/86xx/mpc86xx.h b/arch/powerpc/platforms/86xx/mpc86xx.h index 23f7ed2..525ffa1 100644 --- a/arch/powerpc/platforms/86xx/mpc86xx.h +++ b/arch/powerpc/platforms/86xx/mpc86xx.h @@ -15,11 +15,6 @@ * mpc86xx_* files. Mostly for use by mpc86xx_setup(). */ -extern int mpc86xx_add_bridge(struct device_node *dev); - -extern int mpc86xx_exclude_device(struct pci_controller *hose, - u_char bus, u_char devfn); - extern void __init mpc86xx_smp_init(void); #endif /* __MPC86XX_H__ */ diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c index 5b01ec7..e67e10d 100644 --- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c +++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c @@ -31,6 +31,7 @@ #include <asm/mpic.h> +#include <sysdev/fsl_pci.h> #include <sysdev/fsl_soc.h> #include "mpc86xx.h" @@ -344,8 +345,14 @@ mpc86xx_hpcn_setup_arch(void) } #ifdef CONFIG_PCI - for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) - mpc86xx_add_bridge(np); + for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) { + struct resource rsrc; + of_address_to_resource(np, 0, &rsrc); + if ((rsrc.start & 0xfffff) == 0x8000) + fsl_add_bridge(np, 1); + else + fsl_add_bridge(np, 0); + } #endif printk("MPC86xx HPCN board from Freescale Semiconductor\n"); diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 24ba1b6..10c47b5 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -1,136 +1,98 @@ /* - * MPC86XX pci setup code + * MPC85xx/86xx PCI/PCIE support routing. * - * Recode: ZHANG WEI <wei.zhang@freescale.com> - * Initial author: Xianghua Xiao <x.xiao@freescale.com> + * Copyright 2007 Freescale Semiconductor, Inc * - * Copyright 2006 Freescale Semiconductor Inc. + * Initial author: Xianghua Xiao <x.xiao@freescale.com> + * Recode: ZHANG WEI <wei.zhang@freescale.com> + * Rewrite the routing for Frescale PCI and PCI Express + * Roy Zang <tie-fei.zang@freescale.com> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ - -#include <linux/types.h> -#include <linux/module.h> -#include <linux/init.h> +#include <linux/kernel.h> #include <linux/pci.h> -#include <linux/serial.h> +#include <linux/delay.h> +#include <linux/string.h> +#include <linux/init.h> +#include <linux/bootmem.h> -#include <asm/system.h> -#include <asm/atomic.h> #include <asm/io.h> #include <asm/prom.h> #include <asm/pci-bridge.h> +#include <asm/machdep.h> #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> -#include "../platforms/86xx/mpc86xx.h" - -#undef DEBUG - -#ifdef DEBUG -#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) -#else -#define DBG(fmt, args...) -#endif - -struct pcie_outbound_window_regs { - uint pexotar; /* 0x.0 - PCI Express outbound translation address register */ - uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */ - uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */ - char res1[4]; - uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */ - char res2[12]; -}; - -struct pcie_inbound_window_regs { - uint pexitar; /* 0x.0 - PCI Express inbound translation address register */ - char res1[4]; - uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */ - uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */ - uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */ - char res2[12]; -}; - -static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc) +/* atmu setup for fsl pci/pcie controller */ +void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc) { - volatile struct ccsr_pex *pcie; - volatile struct pcie_outbound_window_regs *pcieow; - volatile struct pcie_inbound_window_regs *pcieiw; - int i = 0; + struct ccsr_pci __iomem *pci; + int i; - DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start, + pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start, rsrc->end - rsrc->start + 1); - pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); - - /* Disable all windows (except pexowar0 since its ignored) */ - pcie->pexowar1 = 0; - pcie->pexowar2 = 0; - pcie->pexowar3 = 0; - pcie->pexowar4 = 0; - pcie->pexiwar1 = 0; - pcie->pexiwar2 = 0; - pcie->pexiwar3 = 0; - - pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1; - pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1; - - /* Setup outbound MEM window */ - for(i = 0; i < 3; i++) - if (hose->mem_resources[i].flags & IORESOURCE_MEM){ - DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n", - hose->mem_resources[i].start, - hose->mem_resources[i].end - - hose->mem_resources[i].start + 1); - pcieow->pexotar = (hose->mem_resources[i].start) >> 12 - & 0x000fffff; - pcieow->pexotear = 0; - pcieow->pexowbar = (hose->mem_resources[i].start) >> 12 - & 0x000fffff; - /* Enable, Mem R/W */ - pcieow->pexowar = 0x80044000 | - (__ilog2(hose->mem_resources[i].end - - hose->mem_resources[i].start + 1) - - 1); - pcieow++; - } - - /* Setup outbound IO window */ - if (hose->io_resource.flags & IORESOURCE_IO){ - DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", - hose->io_resource.start, - hose->io_resource.end - hose->io_resource.start + 1, - hose->io_base_phys); - pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff; - pcieow->pexotear = 0; - pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff; - /* Enable, IO R/W */ - pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end - - hose->io_resource.start + 1) - 1); - } - - /* Setup 2G inbound Memory Window @ 0 */ - pcieiw->pexitar = 0x00000000; - pcieiw->pexiwbar = 0x00000000; - /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */ - pcieiw->pexiwar = 0xa0f5501e; + pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); + + /* Disable all windows (except powar0 since its ignored) */ + for(i = 1; i < 5; i++) + out_be32(&pci->pow[i].powar, 0); + for(i = 0; i < 3; i++) + out_be32(&pci->piw[i].piwar, 0); + + /* Setup outbound MEM window */ + for(i = 0; i < 3; i++) + if (hose->mem_resources[i].flags & IORESOURCE_MEM){ + pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n", + hose->mem_resources[i].start, + hose->mem_resources[i].end + - hose->mem_resources[i].start + 1); + out_be32(&pci->pow[i+1].potar, + (hose->mem_resources[i].start >> 12) + & 0x000fffff); + out_be32(&pci->pow[i+1].potear, 0); + out_be32(&pci->pow[i+1].powbar, + (hose->mem_resources[i].start >> 12) + & 0x000fffff); + /* Enable, Mem R/W */ + out_be32(&pci->pow[i+1].powar, 0x80044000 + | (__ilog2(hose->mem_resources[i].end + - hose->mem_resources[i].start + 1) - 1)); + } + + /* Setup outbound IO window */ + if (hose->io_resource.flags & IORESOURCE_IO){ + pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", + hose->io_resource.start, + hose->io_resource.end - hose->io_resource.start + 1, + hose->io_base_phys); + out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12) + & 0x000fffff); + out_be32(&pci->pow[i+1].potear, 0); + out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12) + & 0x000fffff); + /* Enable, IO R/W */ + out_be32(&pci->pow[i+1].powar, 0x80088000 + | (__ilog2(hose->io_resource.end + - hose->io_resource.start + 1) - 1)); + } + + /* Setup 2G inbound Memory Window @ 1 */ + out_be32(&pci->piw[2].pitar, 0x00000000); + out_be32(&pci->piw[2].piwbar,0x00000000); + out_be32(&pci->piw[2].piwar, PIWAR_2G); } -static void __init -mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size) +void __init setup_pci_cmd(struct pci_controller *hose) { u16 cmd; - - DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n", - pcie_offset, pcie_size); - early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY - | PCI_COMMAND_IO; + | PCI_COMMAND_IO; early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); - early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); } @@ -167,72 +129,76 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) } } +int __init fsl_pcie_check_link(struct pci_controller *hose) +{ + u16 val; + early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); + if (val < PCIE_LTSSM_L0) + return 1; + return 0; +} -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); - -#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */ -#define PCIE_LTSSM_L0 0x16 /* L0 state */ - -int __init mpc86xx_add_bridge(struct device_node *dev) +int __init fsl_add_bridge(struct device_node *dev, int is_primary) { int len; struct pci_controller *hose; struct resource rsrc; const int *bus_range; - int has_address = 0; - int primary = 0; - u16 val; - DBG("Adding PCIE host bridge %s\n", dev->full_name); + pr_debug("Adding PCI host bridge %s\n", dev->full_name); /* Fetch host bridge registers address */ - has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); + if (of_address_to_resource(dev, 0, &rsrc)) { + printk(KERN_WARNING "Can't get pci register base!"); + return -ENOMEM; + } /* Get bus range if any */ bus_range = of_get_property(dev, "bus-range", &len); if (bus_range == NULL || len < 2 * sizeof(int)) printk(KERN_WARNING "Can't get bus-range for %s, assume" - " bus 0\n", dev->full_name); + " bus 0\n", dev->full_name); pci_assign_all_buses = 1; hose = pcibios_alloc_controller(dev); if (!hose) return -ENOMEM; - hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | - PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; - hose->first_busno = bus_range ? bus_range[0] : 0x0; hose->last_busno = bus_range ? bus_range[1] : 0xff; - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); - - /* Probe the hose link training status */ - early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); - if (val < PCIE_LTSSM_L0) - return -ENXIO; + /* check PCI express bridge */ + if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") || + of_device_is_compatible(dev, "fsl,mpc8641-pcie")) + hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | + PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; - /* Setup the PCIE host controller. */ - mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1); + setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); + setup_pci_cmd(hose); - if ((rsrc.start & 0xfffff) == 0x8000) - primary = 1; + /* check PCI express link status */ + if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") || + of_device_is_compatible(dev, "fsl,mpc8641-pcie")) + if (fsl_pcie_check_link(hose)) + return -ENXIO; - printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. " - "Firmware bus number: %d->%d\n", - (unsigned long) rsrc.start, - hose->first_busno, hose->last_busno); + printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx." + "Firmware bus number: %d->%d\n", + (unsigned long long)rsrc.start, hose->first_busno, + hose->last_busno); - DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", + pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", hose, hose->cfg_addr, hose->cfg_data); /* Interpret the "ranges" property */ /* This also maps the I/O region and sets isa_io/mem_base */ - pci_process_bridge_OF_ranges(hose, dev, primary); + pci_process_bridge_OF_ranges(hose, dev, is_primary); /* Setup PEX window registers */ - setup_pcie_atmu(hose, &rsrc); + setup_pci_atmu(hose, &rsrc); return 0; } + +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index 8d9779c..700d478 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -11,84 +11,77 @@ */ #ifdef __KERNEL__ -#ifndef __POWERPC_FSL_PCIE_H -#define __POWERPC_FSL_PCIE_H +#ifndef __POWERPC_FSL_PCI_H +#define __POWERPC_FSL_PCI_H -/* PCIE Express IO block registers in 85xx/86xx */ +#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ +#define PCIE_LTSSM_L0 0x16 /* L0 state */ +#define PIWAR_2G 0xa0f5501e /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */ -struct ccsr_pex { - __be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */ - __be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */ - u8 __iomem res1[4]; - __be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */ - __be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */ - u8 __iomem res2[12]; - __be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */ - __be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */ - __be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */ - __be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */ - u8 __iomem res3[3024]; - __be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */ - __be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/ - u8 __iomem res4[8]; - __be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/ - u8 __iomem res5[12]; - __be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */ - __be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/ - __be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/ - u8 __iomem res6[4]; - __be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/ - u8 __iomem res7[12]; - __be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */ - __be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/ - __be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/ - u8 __iomem res8[4]; - __be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/ - u8 __iomem res9[12]; - __be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */ - __be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/ - __be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/ - u8 __iomem res10[4]; - __be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/ - u8 __iomem res11[12]; - __be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */ - __be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/ - __be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/ - u8 __iomem res12[4]; - __be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/ - u8 __iomem res13[12]; - u8 __iomem res14[256]; - __be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */ - u8 __iomem res15[4]; - __be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */ - __be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */ - __be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */ - u8 __iomem res16[12]; - __be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */ - u8 __iomem res17[4]; - __be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */ - __be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */ - __be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */ - u8 __iomem res18[12]; - __be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */ - u8 __iomem res19[4]; - __be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */ - __be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */ - __be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */ - u8 __iomem res20[12]; - __be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */ - u8 __iomem res21[4]; - __be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */ - u8 __iomem res22[4]; - __be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */ - u8 __iomem res23[12]; - __be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */ - u8 __iomem res24[4]; - __be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */ - __be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */ - __be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */ - __be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */ +/* PCI/PCI Express outbound window reg */ +struct pci_outbound_window_regs { + __be32 potar; /* 0x.0 - Outbound translation address register */ + __be32 potear; /* 0x.4 - Outbound translation extended address register */ + __be32 powbar; /* 0x.8 - Outbound window base address register */ + u8 res1[4]; + __be32 powar; /* 0x.10 - Outbound window attributes register */ + u8 res2[12]; }; -#endif /* __POWERPC_FSL_PCIE_H */ +/* PCI/PCI Express inbound window reg */ +struct pci_inbound_window_regs { + __be32 pitar; /* 0x.0 - Inbound translation address register */ + u8 res1[4]; + __be32 piwbar; /* 0x.8 - Inbound window base address register */ + __be32 piwbear; /* 0x.c - Inbound window base extended address register */ + __be32 piwar; /* 0x.10 - Inbound window attributes register */ + u8 res2[12]; +}; + +/* PCI/PCI Express IO block registers for 85xx/86xx */ +struct ccsr_pci { + __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */ + __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */ + __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ + __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */ + __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */ + u8 res2[12]; + __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */ + __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */ + __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */ + __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */ + u8 res3[3024]; + +/* PCI/PCI Express outbound window 0-4 + * Window 0 is the default window and is the only window enabled upon reset. + * The default outbound register set is used when a transaction misses + * in all of the other outbound windows. + */ + struct pci_outbound_window_regs pow[5]; + + u8 res14[256]; + +/* PCI/PCI Express inbound window 3-1 + * inbound window 1 supports only a 32-bit base address and does not + * define an inbound window base extended address register. + */ + struct pci_inbound_window_regs piw[3]; + + __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ + u8 res21[4]; + __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */ + u8 res22[4]; + __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */ + u8 res23[12]; + __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */ + u8 res24[4]; + __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */ + __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */ + __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */ + __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */ +}; + +extern int fsl_add_bridge(struct device_node *dev, int is_primary); + +#endif /* __POWERPC_FSL_PCI_H */ #endif /* __KERNEL__ */ -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 03/25] [POWERPC] Add the ability to find PCI capabilities early on 2007-07-23 20:49 ` [PATCH 02/25] [POWERPC] Rewrite Freescale PCI/PCIe support for 8{3, 5, 6}xx Kumar Gala @ 2007-07-23 20:49 ` Kumar Gala 2007-07-23 20:49 ` [PATCH 04/25] [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link Kumar Gala 2007-07-24 1:37 ` [PATCH 03/25] [POWERPC] Add the ability to find PCI capabilities early on Benjamin Herrenschmidt 0 siblings, 2 replies; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:49 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev Added early_find_capability that wraps pci_bus_find_capability and uses fake_pci_bus() to allow us to call it before we've fully setup the pci_controller. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/kernel/pci_32.c | 7 +++++++ include/asm-powerpc/pci-bridge.h | 3 +++ 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c index 0adf077..bfcfa14 100644 --- a/arch/powerpc/kernel/pci_32.c +++ b/arch/powerpc/kernel/pci_32.c @@ -1468,3 +1468,10 @@ EARLY_PCI_OP(read, dword, u32 *) EARLY_PCI_OP(write, byte, u8) EARLY_PCI_OP(write, word, u16) EARLY_PCI_OP(write, dword, u32) + +extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); +int early_find_capability(struct pci_controller *hose, int bus, int devfn, + int cap) +{ + return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); +} diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h index e72c2a6..7a00b8e 100644 --- a/include/asm-powerpc/pci-bridge.h +++ b/include/asm-powerpc/pci-bridge.h @@ -79,6 +79,9 @@ int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, int where, u32 val); +extern int early_find_capability(struct pci_controller *hose, int bus, + int dev_fn, int cap); + extern void setup_indirect_pci_nomap(struct pci_controller* hose, void __iomem *cfg_addr, void __iomem *cfg_data); extern void setup_indirect_pci(struct pci_controller* hose, -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 04/25] [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link 2007-07-23 20:49 ` [PATCH 03/25] [POWERPC] Add the ability to find PCI capabilities early on Kumar Gala @ 2007-07-23 20:49 ` Kumar Gala 2007-07-23 20:49 ` [PATCH 05/25] [POWERPC] FSL: Cleanup how we detect if we are a PCIe controller Kumar Gala 2007-07-24 1:39 ` [PATCH 04/25] [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link Benjamin Herrenschmidt 2007-07-24 1:37 ` [PATCH 03/25] [POWERPC] Add the ability to find PCI capabilities early on Benjamin Herrenschmidt 1 sibling, 2 replies; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:49 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev Added PPC_INDIRECT_TYPE_NO_PCIE_LINK flag to the indirect pci handling code to ensure that we don't talk to any device other than the PHB if we don't have PCIe link. Some controllers will lockup if they try to do a config cycle to any device on the bus except the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/sysdev/indirect_pci.c | 16 +++++++++++++++- include/asm-powerpc/pci-bridge.h | 5 +++++ 2 files changed, 20 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c index c7e6e85..bc5b4e2 100644 --- a/arch/powerpc/sysdev/indirect_pci.c +++ b/arch/powerpc/sysdev/indirect_pci.c @@ -35,10 +35,17 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, u8 cfg_type = 0; u32 bus_no, reg; + if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) { + if (bus->number != hose->first_busno) + return PCIBIOS_DEVICE_NOT_FOUND; + if (devfn != 0) + return PCIBIOS_DEVICE_NOT_FOUND; + } + if (ppc_md.pci_exclude_device) if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) return PCIBIOS_DEVICE_NOT_FOUND; - + if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE) if (bus->number != hose->first_busno) cfg_type = 1; @@ -83,6 +90,13 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, u8 cfg_type = 0; u32 bus_no, reg; + if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) { + if (bus->number != hose->first_busno) + return PCIBIOS_DEVICE_NOT_FOUND; + if (devfn != 0) + return PCIBIOS_DEVICE_NOT_FOUND; + } + if (ppc_md.pci_exclude_device) if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) return PCIBIOS_DEVICE_NOT_FOUND; diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h index 7a00b8e..9754357 100644 --- a/include/asm-powerpc/pci-bridge.h +++ b/include/asm-powerpc/pci-bridge.h @@ -45,10 +45,15 @@ struct pci_controller { * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS * to determine which bus number to match on when generating type0 * config cycles + * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with + * hanging if we don't have link and try to do config cycles to + * anything but the PHB. Only allow talking to the PHB if this is + * set. */ #define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001) #define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004) +#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008) u32 indirect_type; /* Currently, we limit ourselves to 1 IO range and 3 mem -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 05/25] [POWERPC] FSL: Cleanup how we detect if we are a PCIe controller 2007-07-23 20:49 ` [PATCH 04/25] [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link Kumar Gala @ 2007-07-23 20:49 ` Kumar Gala 2007-07-23 20:49 ` [PATCH 06/25] [POWERPC] Add 8548 CDS PCI express controller node and PCI-X device node Kumar Gala 2007-07-24 1:39 ` [PATCH 04/25] [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link Benjamin Herrenschmidt 1 sibling, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:49 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev Use the PCI capabilities to determine if we are PCIe PHB. Also use PPC_INDIRECT_TYPE_NO_PCIE_LINK since the Freescale PCIe controllers will lock the system if they don't have link and you try to do a config access to anything but the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/sysdev/fsl_pci.c | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 10c47b5..69d3c6e 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -102,6 +102,10 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) int i, res_idx = PCI_BRIDGE_RESOURCES; struct pci_controller *hose; + /* if we aren't a PCIe don't bother */ + if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) + return ; + /* * Make the bridge be transparent. */ @@ -167,20 +171,16 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) hose->first_busno = bus_range ? bus_range[0] : 0x0; hose->last_busno = bus_range ? bus_range[1] : 0xff; - /* check PCI express bridge */ - if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") || - of_device_is_compatible(dev, "fsl,mpc8641-pcie")) - hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | - PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); setup_pci_cmd(hose); /* check PCI express link status */ - if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") || - of_device_is_compatible(dev, "fsl,mpc8641-pcie")) + if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { + hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | + PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; if (fsl_pcie_check_link(hose)) - return -ENXIO; + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; + } printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx." "Firmware bus number: %d->%d\n", -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 06/25] [POWERPC] Add 8548 CDS PCI express controller node and PCI-X device node 2007-07-23 20:49 ` [PATCH 05/25] [POWERPC] FSL: Cleanup how we detect if we are a PCIe controller Kumar Gala @ 2007-07-23 20:49 ` Kumar Gala 2007-07-23 20:49 ` [PATCH 07/25] [POWERPC] Update PCI nodes in the 83xx/85xx boards device tree Kumar Gala 0 siblings, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:49 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev From: Roy Zang <tie-fei.zang@freescale.com> Add 8548 CDS PCI express controller node and PCI-X device node. The current dts file is suitable for 8548 Rev 2.0 board with Arcadia 3.1. This kind of board combination is the most popular. Used the following compatible properties: PCI "fsl,mpc8540-pci" PCI-X: "fsl,mpc8540-pcix" PCIe: "fsl,mpc8548-pcie" Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/boot/dts/mpc8548cds.dts | 156 +++++++++++++++++++++++----------- 1 files changed, 105 insertions(+), 51 deletions(-) diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index 9d0b84b..4770a5b 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -1,5 +1,5 @@ /* - * MPC8555 CDS Device Tree Source + * MPC8548 CDS Device Tree Source * * Copyright 2006 Freescale Semiconductor Inc. * @@ -186,67 +186,96 @@ pci1: pci@8000 { interrupt-map-mask = <1f800 0 0 7>; interrupt-map = < + /* IDSEL 0x4 (PCIX Slot 2) */ + 02000 0 0 1 &mpic 0 1 + 02000 0 0 2 &mpic 1 1 + 02000 0 0 3 &mpic 2 1 + 02000 0 0 4 &mpic 3 1 + + /* IDSEL 0x5 (PCIX Slot 3) */ + 02800 0 0 1 &mpic 1 1 + 02800 0 0 2 &mpic 2 1 + 02800 0 0 3 &mpic 3 1 + 02800 0 0 4 &mpic 0 1 + + /* IDSEL 0x6 (PCIX Slot 4) */ + 03000 0 0 1 &mpic 2 1 + 03000 0 0 2 &mpic 3 1 + 03000 0 0 3 &mpic 0 1 + 03000 0 0 4 &mpic 1 1 + + /* IDSEL 0x8 (PCIX Slot 5) */ + 04000 0 0 1 &mpic 0 1 + 04000 0 0 2 &mpic 1 1 + 04000 0 0 3 &mpic 2 1 + 04000 0 0 4 &mpic 3 1 + + /* IDSEL 0xC (Tsi310 bridge) */ + 06000 0 0 1 &mpic 0 1 + 06000 0 0 2 &mpic 1 1 + 06000 0 0 3 &mpic 2 1 + 06000 0 0 4 &mpic 3 1 + + /* IDSEL 0x14 (Slot 2) */ + 0a000 0 0 1 &mpic 0 1 + 0a000 0 0 2 &mpic 1 1 + 0a000 0 0 3 &mpic 2 1 + 0a000 0 0 4 &mpic 3 1 + + /* IDSEL 0x15 (Slot 3) */ + 0a800 0 0 1 &mpic 1 1 + 0a800 0 0 2 &mpic 2 1 + 0a800 0 0 3 &mpic 3 1 + 0a800 0 0 4 &mpic 0 1 + + /* IDSEL 0x16 (Slot 4) */ + 0b000 0 0 1 &mpic 2 1 + 0b000 0 0 2 &mpic 3 1 + 0b000 0 0 3 &mpic 0 1 + 0b000 0 0 4 &mpic 1 1 + + /* IDSEL 0x18 (Slot 5) */ + 0c000 0 0 1 &mpic 0 1 + 0c000 0 0 2 &mpic 1 1 + 0c000 0 0 3 &mpic 2 1 + 0c000 0 0 4 &mpic 3 1 + + /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ + 0E000 0 0 1 &mpic 0 1 + 0E000 0 0 2 &mpic 1 1 + 0E000 0 0 3 &mpic 2 1 + 0E000 0 0 4 &mpic 3 1 + + /* bus 1 , idsel 0x2 Tsi310 bridge secondary */ + 11000 0 0 1 &mpic 2 1 + 11000 0 0 2 &mpic 3 1 + 11000 0 0 3 &mpic 0 1 + 11000 0 0 4 &mpic 1 1 + + /* VIA chip */ + 12000 0 0 1 &mpic 0 1 + 12000 0 0 2 &mpic 1 1 + 12000 0 0 3 &mpic 2 1 + 12000 0 0 4 &mpic 3 1>; - /* IDSEL 0x10 */ - 08000 0 0 1 &mpic 0 1 - 08000 0 0 2 &mpic 1 1 - 08000 0 0 3 &mpic 2 1 - 08000 0 0 4 &mpic 3 1 - - /* IDSEL 0x11 */ - 08800 0 0 1 &mpic 0 1 - 08800 0 0 2 &mpic 1 1 - 08800 0 0 3 &mpic 2 1 - 08800 0 0 4 &mpic 3 1 - - /* IDSEL 0x12 (Slot 1) */ - 09000 0 0 1 &mpic 0 1 - 09000 0 0 2 &mpic 1 1 - 09000 0 0 3 &mpic 2 1 - 09000 0 0 4 &mpic 3 1 - - /* IDSEL 0x13 (Slot 2) */ - 09800 0 0 1 &mpic 1 1 - 09800 0 0 2 &mpic 2 1 - 09800 0 0 3 &mpic 3 1 - 09800 0 0 4 &mpic 0 1 - - /* IDSEL 0x14 (Slot 3) */ - 0a000 0 0 1 &mpic 2 1 - 0a000 0 0 2 &mpic 3 1 - 0a000 0 0 3 &mpic 0 1 - 0a000 0 0 4 &mpic 1 1 - - /* IDSEL 0x15 (Slot 4) */ - 0a800 0 0 1 &mpic 3 1 - 0a800 0 0 2 &mpic 0 1 - 0a800 0 0 3 &mpic 1 1 - 0a800 0 0 4 &mpic 2 1 - - /* Bus 1 (Tundra Bridge) */ - /* IDSEL 0x12 (ISA bridge) */ - 19000 0 0 1 &mpic 0 1 - 19000 0 0 2 &mpic 1 1 - 19000 0 0 3 &mpic 2 1 - 19000 0 0 4 &mpic 3 1>; interrupt-parent = <&mpic>; interrupts = <18 2>; bus-range = <0 0>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 00100000>; + ranges = <02000000 0 80000000 80000000 0 10000000 + 01000000 0 00000000 e2000000 0 00800000>; clock-frequency = <3f940aa>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <8000 1000>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; device_type = "pci"; - i8259@19000 { + i8259@4 { clock-frequency = <0>; interrupt-controller; device_type = "interrupt-controller"; - reg = <19000 0 0 0 1>; + reg = <12000 0 0 0 1>; #address-cells = <0>; #interrupt-cells = <2>; built-in; @@ -266,17 +295,42 @@ a800 0 0 2 &mpic b 1 a800 0 0 3 &mpic b 1 a800 0 0 4 &mpic b 1>; + interrupt-parent = <&mpic>; interrupts = <19 2>; bus-range = <0 0>; - ranges = <02000000 0 a0000000 a0000000 0 20000000 - 01000000 0 00000000 e3000000 0 00100000>; + ranges = <02000000 0 90000000 90000000 0 10000000 + 01000000 0 00000000 e2800000 0 00800000>; clock-frequency = <3f940aa>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <9000 1000>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + }; + /* PCI Express */ + pcie@a000 { + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + + /* IDSEL 0x0 (PEX) */ + 00000 0 0 1 &mpic 0 1 + 00000 0 0 2 &mpic 1 1 + 00000 0 0 3 &mpic 2 1 + 00000 0 0 4 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <1a 2>; + bus-range = <0 ff>; + ranges = <02000000 0 a0000000 a0000000 0 20000000 + 01000000 0 00000000 e3000000 0 08000000>; + clock-frequency = <1fca055>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <a000 1000>; + compatible = "fsl,mpc8548-pcie"; device_type = "pci"; }; -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 07/25] [POWERPC] Update PCI nodes in the 83xx/85xx boards device tree 2007-07-23 20:49 ` [PATCH 06/25] [POWERPC] Add 8548 CDS PCI express controller node and PCI-X device node Kumar Gala @ 2007-07-23 20:49 ` Kumar Gala 2007-07-23 20:49 ` [PATCH 08/25] [POWERPC] Use Freescale pci/pcie common code for 85xx boards Kumar Gala 0 siblings, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:49 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev From: Roy Zang <tie-fei.zang@freescale.com> Updated the 83xx & 85xx device tree PCI related compartible property. Used the following compatible properties: PCI "fsl,mpc8349-pci" PCI "fsl,mpc8540-pci" PCI-X: "fsl,mpc8540-pcix" PCIe: "fsl,mpc8548-pcie" Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/boot/dts/mpc8313erdb.dts | 2 +- arch/powerpc/boot/dts/mpc832x_mds.dts | 2 +- arch/powerpc/boot/dts/mpc832x_rdb.dts | 2 +- arch/powerpc/boot/dts/mpc8349emitx.dts | 4 ++-- arch/powerpc/boot/dts/mpc8349emitxgp.dts | 2 +- arch/powerpc/boot/dts/mpc834x_mds.dts | 4 ++-- arch/powerpc/boot/dts/mpc836x_mds.dts | 2 +- arch/powerpc/boot/dts/mpc8540ads.dts | 2 +- arch/powerpc/boot/dts/mpc8541cds.dts | 4 ++-- arch/powerpc/boot/dts/mpc8555cds.dts | 4 ++-- arch/powerpc/boot/dts/mpc8560ads.dts | 2 +- 11 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts index a1533cc..c5adbe4 100644 --- a/arch/powerpc/boot/dts/mpc8313erdb.dts +++ b/arch/powerpc/boot/dts/mpc8313erdb.dts @@ -178,7 +178,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8500 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts index 4fc0c4d..f158ed7 100644 --- a/arch/powerpc/boot/dts/mpc832x_mds.dts +++ b/arch/powerpc/boot/dts/mpc832x_mds.dts @@ -154,7 +154,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8500 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts index 447c03f..7c4beff 100644 --- a/arch/powerpc/boot/dts/mpc832x_rdb.dts +++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts @@ -123,7 +123,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8500 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts index ae9bca5..502f47c 100644 --- a/arch/powerpc/boot/dts/mpc8349emitx.dts +++ b/arch/powerpc/boot/dts/mpc8349emitx.dts @@ -197,7 +197,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8500 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; @@ -222,7 +222,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8600 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts index f636528..0b83871 100644 --- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts +++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts @@ -154,7 +154,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8600 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts index 310e877..4810997 100644 --- a/arch/powerpc/boot/dts/mpc834x_mds.dts +++ b/arch/powerpc/boot/dts/mpc834x_mds.dts @@ -241,7 +241,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8500 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; @@ -301,7 +301,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8600 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts index 1e914f3..e3f7c12 100644 --- a/arch/powerpc/boot/dts/mpc836x_mds.dts +++ b/arch/powerpc/boot/dts/mpc836x_mds.dts @@ -169,7 +169,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8500 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts index 364a969..fc8dff9 100644 --- a/arch/powerpc/boot/dts/mpc8540ads.dts +++ b/arch/powerpc/boot/dts/mpc8540ads.dts @@ -258,7 +258,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8000 1000>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index 070206f..fb0b647 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts @@ -193,7 +193,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8000 1000>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pci"; device_type = "pci"; i8259@19000 { @@ -230,7 +230,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <9000 1000>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts index 17e45d9..c3c8882 100644 --- a/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/arch/powerpc/boot/dts/mpc8555cds.dts @@ -193,7 +193,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8000 1000>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pci"; device_type = "pci"; i8259@19000 { @@ -230,7 +230,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <9000 1000>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts index 21ccaaa..16dbe84 100644 --- a/arch/powerpc/boot/dts/mpc8560ads.dts +++ b/arch/powerpc/boot/dts/mpc8560ads.dts @@ -136,7 +136,7 @@ #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; device_type = "pci"; reg = <8000 1000>; clock-frequency = <3f940aa>; -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 08/25] [POWERPC] Use Freescale pci/pcie common code for 85xx boards 2007-07-23 20:49 ` [PATCH 07/25] [POWERPC] Update PCI nodes in the 83xx/85xx boards device tree Kumar Gala @ 2007-07-23 20:49 ` Kumar Gala 2007-07-23 20:49 ` [PATCH 09/25] [POWERPC] Add basic PCI node for mpc8568mds board Kumar Gala 0 siblings, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:49 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev From: Roy Zang <tie-fei.zang@freescale.com> Switch the 85xx platform over to using the FSL generic PCI code. This gets ups PCIe support in addition to base PCI support. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/platforms/85xx/Kconfig | 5 +- arch/powerpc/platforms/85xx/Makefile | 2 +- arch/powerpc/platforms/85xx/mpc85xx.h | 1 - arch/powerpc/platforms/85xx/mpc85xx_ads.c | 3 +- arch/powerpc/platforms/85xx/mpc85xx_cds.c | 14 +++-- arch/powerpc/platforms/85xx/mpc85xx_mds.c | 6 +- arch/powerpc/platforms/85xx/pci.c | 91 ----------------------------- arch/powerpc/sysdev/fsl_pci.c | 7 ++ 8 files changed, 25 insertions(+), 104 deletions(-) delete mode 100644 arch/powerpc/platforms/85xx/pci.c diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 629926e..526ddde 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -50,9 +50,10 @@ config MPC8560 config MPC85xx bool select PPC_UDBG_16550 - select PPC_INDIRECT_PCI - select PPC_INDIRECT_PCI_BE + select PPC_INDIRECT_PCI if PCI + select PPC_INDIRECT_PCI_BE if PCI select MPIC + select FSL_PCI if PCI select SERIAL_8250_SHARE_IRQ if SERIAL_8250 default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS \ || MPC85xx_MDS || MPC8544_DS diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index 4e02cbb..d70f2d0 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile @@ -1,7 +1,7 @@ # # Makefile for the PowerPC 85xx linux kernel. # -obj-$(CONFIG_PPC_85xx) += misc.o pci.o +obj-$(CONFIG_PPC_85xx) += misc.o obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h index 7286ffa..5b34dee 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx.h +++ b/arch/powerpc/platforms/85xx/mpc85xx.h @@ -15,4 +15,3 @@ */ extern void mpc85xx_restart(char *); -extern int mpc85xx_add_bridge(struct device_node *dev); diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c index 7235f70..40a8286 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c @@ -29,6 +29,7 @@ #include <asm/udbg.h> #include <sysdev/fsl_soc.h> +#include <sysdev/fsl_pci.h> #include "mpc85xx.h" #ifdef CONFIG_CPM2 @@ -217,7 +218,7 @@ static void __init mpc85xx_ads_setup_arch(void) #ifdef CONFIG_PCI for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) - mpc85xx_add_bridge(np); + fsl_add_bridge(np, 1); ppc_md.pci_exclude_device = mpc85xx_exclude_device; #endif } diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c index 50c8d64..2539bb5 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c @@ -45,6 +45,7 @@ #include <asm/i8259.h> #include <sysdev/fsl_soc.h> +#include <sysdev/fsl_pci.h> #include "mpc85xx.h" static int cds_pci_slot = 2; @@ -58,8 +59,6 @@ static volatile u8 *cadmus; static int mpc85xx_exclude_device(struct pci_controller *hose, u_char bus, u_char devfn) { - if ((bus == hose->first_busno) && PCI_SLOT(devfn) == 0) - return PCIBIOS_DEVICE_NOT_FOUND; /* We explicitly do not go past the Tundra 320 Bridge */ if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL)) return PCIBIOS_DEVICE_NOT_FOUND; @@ -218,9 +217,14 @@ static void __init mpc85xx_cds_setup_arch(void) } #ifdef CONFIG_PCI - for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) - mpc85xx_add_bridge(np); - + for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) { + struct resource rsrc; + of_address_to_resource(np, 0, &rsrc); + if ((rsrc.start & 0xfffff) == 0x9000) + fsl_add_bridge(np, 0); + else + fsl_add_bridge(np, 1); + } ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup; ppc_md.pci_exclude_device = mpc85xx_exclude_device; #endif diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 004b80b..9aa96f0 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -46,6 +46,7 @@ #include <asm/prom.h> #include <asm/udbg.h> #include <sysdev/fsl_soc.h> +#include <sysdev/fsl_pci.h> #include <asm/qe.h> #include <asm/qe_ic.h> #include <asm/mpic.h> @@ -94,9 +95,8 @@ static void __init mpc85xx_mds_setup_arch(void) } #ifdef CONFIG_PCI - for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) { - mpc85xx_add_bridge(np); - } + for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) + fsl_add_bridge(np, 1); of_node_put(np); #endif diff --git a/arch/powerpc/platforms/85xx/pci.c b/arch/powerpc/platforms/85xx/pci.c deleted file mode 100644 index 8118417..0000000 --- a/arch/powerpc/platforms/85xx/pci.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * FSL SoC setup code - * - * Maintained by Kumar Gala (see MAINTAINERS for contact information) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/stddef.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/pci.h> -#include <linux/delay.h> -#include <linux/irq.h> -#include <linux/module.h> - -#include <asm/system.h> -#include <asm/atomic.h> -#include <asm/io.h> -#include <asm/pci-bridge.h> -#include <asm/prom.h> -#include <sysdev/fsl_soc.h> - -#undef DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -#ifdef CONFIG_PCI -int __init mpc85xx_add_bridge(struct device_node *dev) -{ - int len; - struct pci_controller *hose; - struct resource rsrc; - const int *bus_range; - int primary = 1, has_address = 0; - phys_addr_t immr = get_immrbase(); - - DBG("Adding PCI host bridge %s\n", dev->full_name); - - /* Fetch host bridge registers address */ - has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); - - /* Get bus range if any */ - bus_range = of_get_property(dev, "bus-range", &len); - if (bus_range == NULL || len < 2 * sizeof(int)) { - printk(KERN_WARNING "Can't get bus-range for %s, assume" - " bus 0\n", dev->full_name); - } - - pci_assign_all_buses = 1; - hose = pcibios_alloc_controller(dev); - if (!hose) - return -ENOMEM; - - hose->first_busno = bus_range ? bus_range[0] : 0; - hose->last_busno = bus_range ? bus_range[1] : 0xff; - - /* PCI 1 */ - if ((rsrc.start & 0xfffff) == 0x8000) { - setup_indirect_pci(hose, immr + 0x8000, immr + 0x8004); - } - /* PCI 2 */ - if ((rsrc.start & 0xfffff) == 0x9000) { - setup_indirect_pci(hose, immr + 0x9000, immr + 0x9004); - primary = 0; - } - - printk(KERN_INFO "Found MPC85xx PCI host bridge at 0x%016llx. " - "Firmware bus number: %d->%d\n", - (unsigned long long)rsrc.start, hose->first_busno, - hose->last_busno); - - DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", - hose, hose->cfg_addr, hose->cfg_data); - - /* Interpret the "ranges" property */ - /* This also maps the I/O region and sets isa_io/mem_base */ - pci_process_bridge_OF_ranges(hose, dev, primary); - - return 0; -} - -#endif diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 69d3c6e..2eefcde 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -200,5 +200,12 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) return 0; } +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0012, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0013, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0014, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0015, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0018, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0019, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x001a, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 09/25] [POWERPC] Add basic PCI node for mpc8568mds board 2007-07-23 20:49 ` [PATCH 08/25] [POWERPC] Use Freescale pci/pcie common code for 85xx boards Kumar Gala @ 2007-07-23 20:49 ` Kumar Gala 2007-07-23 20:49 ` [PATCH 10/25] [POWERPC] Fixup resources on pci_bus for PCIe PHB when no device is connected Kumar Gala 0 siblings, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:49 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev; +Cc: Haiying Wang From: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/boot/dts/mpc8568mds.dts | 29 +++++++++++++++++++++++++++++ 1 files changed, 29 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index 6bb18f2..54cde68 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -170,6 +170,35 @@ interrupt-parent = <&mpic>; }; + pci@8000 { + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + /* IDSEL 0x12 AD18 */ + 9000 0 0 1 &mpic 5 1 + 9000 0 0 2 &mpic 6 1 + 9000 0 0 3 &mpic 7 1 + 9000 0 0 4 &mpic 4 1 + + /* IDSEL 0x13 AD19 */ + 9800 0 0 1 &mpic 6 1 + 9800 0 0 2 &mpic 7 1 + 9800 0 0 3 &mpic 4 1 + 9800 0 0 4 &mpic 5 1>; + + interrupt-parent = <&mpic>; + interrupts = <18 2>; + bus-range = <0 ff>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 00800000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <8000 1000>; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + }; + serial@4600 { device_type = "serial"; compatible = "ns16550"; -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 10/25] [POWERPC] Fixup resources on pci_bus for PCIe PHB when no device is connected 2007-07-23 20:49 ` [PATCH 09/25] [POWERPC] Add basic PCI node for mpc8568mds board Kumar Gala @ 2007-07-23 20:49 ` Kumar Gala 2007-07-23 20:49 ` [PATCH 11/25] [POWERPC] 85xx: Added 8568 PCIe support Kumar Gala 0 siblings, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:49 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev On the 85xx/86xx PCIe controllers if there is no device connected to the PHB we will still allocate a pci_bus for downstream bus of the virtual P2P bridge. However the resources allocated to the downstream bus are not correct and so we just mimic the resources from the upstream pci_bus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/platforms/85xx/mpc85xx_cds.c | 1 + arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 2 +- arch/powerpc/sysdev/fsl_pci.c | 14 ++++++++++++++ arch/powerpc/sysdev/fsl_pci.h | 1 + 4 files changed, 17 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c index 2539bb5..9b559eb 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c @@ -272,4 +272,5 @@ define_machine(mpc85xx_cds) { .restart = mpc85xx_restart, .calibrate_decr = generic_calibrate_decr, .progress = udbg_progress, + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, }; diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c index e67e10d..e9eaa07 100644 --- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c +++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c @@ -431,7 +431,6 @@ mpc86xx_time_init(void) return 0; } - define_machine(mpc86xx_hpcn) { .name = "MPC86xx HPCN", .probe = mpc86xx_hpcn_probe, @@ -443,4 +442,5 @@ define_machine(mpc86xx_hpcn) { .time_init = mpc86xx_time_init, .calibrate_decr = generic_calibrate_decr, .progress = udbg_progress, + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, }; diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 2eefcde..faafae6 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -142,6 +142,20 @@ int __init fsl_pcie_check_link(struct pci_controller *hose) return 0; } +void fsl_pcibios_fixup_bus(struct pci_bus *bus) +{ + struct pci_controller *hose = (struct pci_controller *) bus->sysdata; + int i; + + /* deal with bogus pci_bus when we don't have anything connected on PCIe */ + if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) { + if (bus->parent) { + for (i = 0; i < 4; ++i) + bus->resource[i] = bus->parent->resource[i]; + } + } +} + int __init fsl_add_bridge(struct device_node *dev, int is_primary) { int len; diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index 700d478..37b04ad 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -82,6 +82,7 @@ struct ccsr_pci { }; extern int fsl_add_bridge(struct device_node *dev, int is_primary); +extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); #endif /* __POWERPC_FSL_PCI_H */ #endif /* __KERNEL__ */ -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 11/25] [POWERPC] 85xx: Added 8568 PCIe support 2007-07-23 20:49 ` [PATCH 10/25] [POWERPC] Fixup resources on pci_bus for PCIe PHB when no device is connected Kumar Gala @ 2007-07-23 20:49 ` Kumar Gala 2007-07-23 20:49 ` [PATCH 12/25] [POWERPC] 85xx: Add quirk to ignore bogus FPGA on CDS Kumar Gala 0 siblings, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:49 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev Added the PCIe device node to the 8568 dts and the needed quirk entries. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/boot/dts/mpc8568mds.dts | 25 +++ arch/powerpc/configs/mpc8568mds_defconfig | 292 ++++++++++++++++++----------- arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 + arch/powerpc/sysdev/fsl_pci.c | 4 + 4 files changed, 208 insertions(+), 114 deletions(-) diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index 54cde68..99fa5a0 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -199,6 +199,31 @@ device_type = "pci"; }; + /* PCI Express */ + pcie@a000 { + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + + /* IDSEL 0x0 (PEX) */ + 00000 0 0 1 &mpic 0 1 + 00000 0 0 2 &mpic 1 1 + 00000 0 0 3 &mpic 2 1 + 00000 0 0 4 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <1a 2>; + bus-range = <0 ff>; + ranges = <02000000 0 a0000000 a0000000 0 20000000 + 01000000 0 00000000 e3000000 0 08000000>; + clock-frequency = <1fca055>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <a000 1000>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + }; + serial@4600 { device_type = "serial"; compatible = "ns16550"; diff --git a/arch/powerpc/configs/mpc8568mds_defconfig b/arch/powerpc/configs/mpc8568mds_defconfig index 6451d4d..417d3e6 100644 --- a/arch/powerpc/configs/mpc8568mds_defconfig +++ b/arch/powerpc/configs/mpc8568mds_defconfig @@ -1,9 +1,26 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.22-rc7 -# Sun Jul 1 23:56:59 2007 +# Linux kernel version: 2.6.22 +# Fri Jul 20 13:55:04 2007 # # CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_6xx is not set +CONFIG_PPC_85xx=y +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_85xx=y +CONFIG_E500=y +CONFIG_BOOKE=y +CONFIG_FSL_BOOKE=y +# CONFIG_PHYS_64BIT is not set +CONFIG_SPE=y +# CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_PPC_MERGE=y CONFIG_MMU=y @@ -14,6 +31,7 @@ CONFIG_ARCH_HAS_ILOG2_U32=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set CONFIG_PPC=y CONFIG_EARLY_PRINTK=y CONFIG_GENERIC_NVRAM=y @@ -25,28 +43,8 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y - -# -# Processor support -# -# CONFIG_CLASSIC32 is not set -# CONFIG_PPC_82xx is not set -# CONFIG_PPC_83xx is not set -CONFIG_PPC_85xx=y -# CONFIG_PPC_86xx is not set -# CONFIG_PPC_8xx is not set -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_E200 is not set -CONFIG_85xx=y -CONFIG_E500=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set -CONFIG_BOOKE=y -CONFIG_FSL_BOOKE=y -# CONFIG_PHYS_64BIT is not set -CONFIG_SPE=y -# CONFIG_PPC_MM_SLICES is not set CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # @@ -63,12 +61,11 @@ CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set +# CONFIG_USER_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 @@ -100,24 +97,17 @@ CONFIG_SLAB=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 - -# -# Loadable module support -# CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_KMOD is not set - -# -# Block layer -# CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set # # IO Schedulers @@ -186,6 +176,8 @@ CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set # CONFIG_PM is not set @@ -201,14 +193,20 @@ CONFIG_ZONE_DMA=y CONFIG_PPC_INDIRECT_PCI=y CONFIG_PPC_INDIRECT_PCI_BE=y CONFIG_FSL_SOC=y -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_FSL_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +# CONFIG_PCIEPORTBUS is not set +CONFIG_ARCH_SUPPORTS_MSI=y +# CONFIG_PCI_MSI is not set +# CONFIG_PCI_DEBUG is not set # # PCCARD (PCMCIA/CardBus) support # # CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set # # Advanced setup @@ -309,6 +307,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -323,42 +322,31 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# # CONFIG_CONNECTOR is not set # CONFIG_MTD is not set - -# -# Parallel port support -# # CONFIG_PARPORT is not set - -# -# Plug and Play support -# -# CONFIG_PNPACPI is not set - -# -# Block devices -# +CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=32768 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set - -# -# Misc devices -# -# CONFIG_BLINK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set # CONFIG_IDE is not set # @@ -366,6 +354,7 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y +CONFIG_SCSI_DMA=y # CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y @@ -402,23 +391,65 @@ CONFIG_SCSI_WAIT_SCAN=m # SCSI low-level drivers # # CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set # CONFIG_ATA is not set +# CONFIG_MD is not set # -# Multi-device support (RAID and LVM) +# Fusion MPT device support # -# CONFIG_MD is not set -# CONFIG_MACINTOSH_DRIVERS is not set +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set # -# Network device support +# IEEE 1394 (FireWire) support # +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_ARCNET is not set CONFIG_PHYLIB=y # @@ -432,17 +463,44 @@ CONFIG_MARVELL_PHY=y # CONFIG_VITESSE_PHY is not set # CONFIG_SMSC_PHY is not set # CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set # CONFIG_FIXED_PHY is not set - -# -# Ethernet (10 or 100Mbit) -# CONFIG_NET_ETHERNET=y CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set CONFIG_GIANFAR=y CONFIG_GFAR_NAPI=y +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TR is not set # # Wireless LAN @@ -450,21 +508,16 @@ CONFIG_NETDEV_10000=y # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set # CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_NET_FC is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set - -# -# Telephony Support -# # CONFIG_PHONE is not set # @@ -510,6 +563,7 @@ CONFIG_INPUT=y # CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_8250_EXTENDED is not set @@ -521,14 +575,11 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set @@ -538,17 +589,23 @@ CONFIG_WATCHDOG=y # # CONFIG_SOFT_WATCHDOG is not set # CONFIG_BOOKE_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set CONFIG_GEN_RTC=y # CONFIG_GEN_RTC_X is not set # CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# # CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y @@ -563,23 +620,43 @@ CONFIG_I2C_CHARDEV=y # # I2C Hardware Bus support # +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set CONFIG_I2C_MPC=y +# CONFIG_I2C_NFORCE2 is not set # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set # CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_STUB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set # # Miscellaneous I2C Chip support # # CONFIG_SENSORS_DS1337 is not set # CONFIG_SENSORS_DS1374 is not set +# CONFIG_DS1682 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_M41T00 is not set # CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -590,11 +667,8 @@ CONFIG_I2C_MPC=y # # CONFIG_SPI is not set # CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# # CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set # CONFIG_SENSORS_ABITUGURU is not set @@ -628,10 +702,13 @@ CONFIG_HWMON=y # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SIS5595 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set @@ -670,19 +747,14 @@ CONFIG_DAB=y # Sound # # CONFIG_SOUND is not set - -# -# HID Devices -# +CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -706,14 +778,7 @@ CONFIG_HID=y # # LED Triggers # - -# -# InfiniBand support -# - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# +# CONFIG_INFINIBAND is not set # # Real Time Clock @@ -734,6 +799,11 @@ CONFIG_HID=y # # +# Userspace I/O +# +# CONFIG_UIO is not set + +# # File systems # CONFIG_EXT2_FS=y @@ -829,7 +899,6 @@ CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types @@ -868,6 +937,7 @@ CONFIG_BITREVERSE=y # CONFIG_CRC16 is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_PLIST=y CONFIG_HAS_IOMEM=y @@ -892,6 +962,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set # CONFIG_DEBUG_SLAB is not set @@ -915,7 +986,7 @@ CONFIG_FORCED_INLINING=y CONFIG_DEBUGGER=y # CONFIG_XMON is not set # CONFIG_BDI_SWITCH is not set -CONFIG_BOOTX_TEXT=y +# CONFIG_BOOTX_TEXT is not set CONFIG_PPC_EARLY_DEBUG=y # CONFIG_PPC_EARLY_DEBUG_LPAR is not set # CONFIG_PPC_EARLY_DEBUG_G5 is not set @@ -932,10 +1003,6 @@ CONFIG_PPC_EARLY_DEBUG=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set - -# -# Cryptographic options -# CONFIG_CRYPTO=y CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_BLKCIPHER=y @@ -973,7 +1040,4 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# +CONFIG_CRYPTO_HW=y diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 9aa96f0..e8003bf 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -208,4 +208,5 @@ define_machine(mpc85xx_mds) { .restart = mpc85xx_restart, .calibrate_decr = generic_calibrate_decr, .progress = udbg_progress, + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, }; diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index faafae6..c6a30f9 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -221,5 +221,9 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0015, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0018, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0019, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x001a, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0020, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0021, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0024, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0025, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 12/25] [POWERPC] 85xx: Add quirk to ignore bogus FPGA on CDS 2007-07-23 20:49 ` [PATCH 11/25] [POWERPC] 85xx: Added 8568 PCIe support Kumar Gala @ 2007-07-23 20:49 ` Kumar Gala 2007-07-23 20:50 ` [PATCH 13/25] [POWERPC] Removed setup_indirect_pci_nomap Kumar Gala 0 siblings, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:49 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev The newer Arcadia boards for CDS have an FPGA that shows up on PCI however isn't a real PCI device. Add a quirk to just ignore the FPGA. This is based on the following patch from Andy & York: http://ozlabs.org/pipermail/linuxppc-dev/2007-February/032042.html Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/platforms/85xx/mpc85xx_cds.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c index 9b559eb..71200bd 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c @@ -108,6 +108,16 @@ static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev) } } +static void __devinit skip_fake_bridge(struct pci_dev *dev) +{ + /* Make it an error to skip the fake bridge + * in pci_setup_device() in probe.c */ + dev->hdr_type = 0x7f; +} +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge); +DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge); +DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge); + #ifdef CONFIG_PPC_I8259 #warning The i8259 PIC support is currently broken static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 13/25] [POWERPC] Removed setup_indirect_pci_nomap 2007-07-23 20:49 ` [PATCH 12/25] [POWERPC] 85xx: Add quirk to ignore bogus FPGA on CDS Kumar Gala @ 2007-07-23 20:50 ` Kumar Gala 2007-07-23 20:50 ` [PATCH 14/25] [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime Kumar Gala 2007-07-24 1:40 ` [PATCH 13/25] [POWERPC] Removed setup_indirect_pci_nomap Benjamin Herrenschmidt 0 siblings, 2 replies; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:50 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev We don't use setup_indirect_pci_nomap in arch/powerpc and it appears the users that needed it from arch/ppc are now using setup_indirect_pci. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/sysdev/indirect_pci.c | 17 ++++------------- include/asm-powerpc/pci-bridge.h | 2 -- 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c index bc5b4e2..ad341f5 100644 --- a/arch/powerpc/sysdev/indirect_pci.c +++ b/arch/powerpc/sysdev/indirect_pci.c @@ -149,24 +149,15 @@ static struct pci_ops indirect_pci_ops = }; void __init -setup_indirect_pci_nomap(struct pci_controller* hose, void __iomem * cfg_addr, - void __iomem * cfg_data) -{ - hose->cfg_addr = cfg_addr; - hose->cfg_data = cfg_data; - hose->ops = &indirect_pci_ops; -} - -void __init setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) { unsigned long base = cfg_addr & PAGE_MASK; - void __iomem *mbase, *addr, *data; + void __iomem *mbase; mbase = ioremap(base, PAGE_SIZE); - addr = mbase + (cfg_addr & ~PAGE_MASK); + hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK); if ((cfg_data & PAGE_MASK) != base) mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE); - data = mbase + (cfg_data & ~PAGE_MASK); - setup_indirect_pci_nomap(hose, addr, data); + hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK); + hose->ops = &indirect_pci_ops; } diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h index 9754357..13cb0a9 100644 --- a/include/asm-powerpc/pci-bridge.h +++ b/include/asm-powerpc/pci-bridge.h @@ -87,8 +87,6 @@ int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, extern int early_find_capability(struct pci_controller *hose, int bus, int dev_fn, int cap); -extern void setup_indirect_pci_nomap(struct pci_controller* hose, - void __iomem *cfg_addr, void __iomem *cfg_data); extern void setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); extern void setup_grackle(struct pci_controller *hose); -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 14/25] [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime 2007-07-23 20:50 ` [PATCH 13/25] [POWERPC] Removed setup_indirect_pci_nomap Kumar Gala @ 2007-07-23 20:50 ` Kumar Gala 2007-07-23 20:50 ` [PATCH 15/25] [POWERPC] Add basic PCI/PCI Express support for 8544DS board Kumar Gala 2007-07-24 1:43 ` [PATCH 14/25] [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime Benjamin Herrenschmidt 2007-07-24 1:40 ` [PATCH 13/25] [POWERPC] Removed setup_indirect_pci_nomap Benjamin Herrenschmidt 1 sibling, 2 replies; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:50 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev Make it so we do a runtime check to know if we need to write cfg_addr as big or little endian. This is needed if we want to allow 86xx support to co-exist in the same kernel as other 6xx PPCs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/Kconfig | 5 ----- arch/powerpc/platforms/82xx/mpc82xx_ads.c | 3 ++- arch/powerpc/platforms/83xx/pci.c | 4 ++-- arch/powerpc/platforms/85xx/Kconfig | 1 - arch/powerpc/platforms/86xx/Kconfig | 1 - arch/powerpc/platforms/chrp/pci.c | 7 ++++--- arch/powerpc/platforms/embedded6xx/linkstation.c | 2 +- arch/powerpc/sysdev/fsl_pci.c | 3 ++- arch/powerpc/sysdev/grackle.c | 2 +- arch/powerpc/sysdev/indirect_pci.c | 20 +++++++++++++++++--- arch/powerpc/sysdev/mv64x60_pci.c | 2 +- include/asm-powerpc/pci-bridge.h | 6 +++++- 12 files changed, 35 insertions(+), 21 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 3ff90f0..00099ef 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -411,11 +411,6 @@ config PPC_INDIRECT_PCI default y if 40x || 44x default n -config PPC_INDIRECT_PCI_BE - bool - depends PPC_INDIRECT_PCI - default n - config EISA bool diff --git a/arch/powerpc/platforms/82xx/mpc82xx_ads.c b/arch/powerpc/platforms/82xx/mpc82xx_ads.c index da20832..2d1b05b 100644 --- a/arch/powerpc/platforms/82xx/mpc82xx_ads.c +++ b/arch/powerpc/platforms/82xx/mpc82xx_ads.c @@ -553,7 +553,8 @@ static void __init mpc82xx_add_bridge(struct device_node *np) setup_indirect_pci(hose, r.start + offsetof(pci_cpm2_t, pci_cfg_addr), - r.start + offsetof(pci_cpm2_t, pci_cfg_data)); + r.start + offsetof(pci_cpm2_t, pci_cfg_data), + 0); pci_process_bridge_OF_ranges(hose, np, 1); } diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/platforms/83xx/pci.c index c0e2b89..9206946 100644 --- a/arch/powerpc/platforms/83xx/pci.c +++ b/arch/powerpc/platforms/83xx/pci.c @@ -74,11 +74,11 @@ int __init mpc83xx_add_bridge(struct device_node *dev) */ /* PCI 1 */ if ((rsrc.start & 0xfffff) == 0x8500) { - setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304); + setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304, 0); } /* PCI 2 */ if ((rsrc.start & 0xfffff) == 0x8600) { - setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384); + setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384, 0); primary = 0; } diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 526ddde..4661fcc 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -51,7 +51,6 @@ config MPC85xx bool select PPC_UDBG_16550 select PPC_INDIRECT_PCI if PCI - select PPC_INDIRECT_PCI_BE if PCI select MPIC select FSL_PCI if PCI select SERIAL_8250_SHARE_IRQ if SERIAL_8250 diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig index d1c8115..343b76d 100644 --- a/arch/powerpc/platforms/86xx/Kconfig +++ b/arch/powerpc/platforms/86xx/Kconfig @@ -14,7 +14,6 @@ endchoice config MPC8641 bool - select PPC_INDIRECT_PCI_BE if PCI select FSL_PCI if PCI select PPC_UDBG_16550 select MPIC diff --git a/arch/powerpc/platforms/chrp/pci.c b/arch/powerpc/platforms/chrp/pci.c index 3690624..28d1647 100644 --- a/arch/powerpc/platforms/chrp/pci.c +++ b/arch/powerpc/platforms/chrp/pci.c @@ -181,7 +181,7 @@ setup_python(struct pci_controller *hose, struct device_node *dev) } iounmap(reg); - setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010); + setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010, 0); } /* Marvell Discovery II based Pegasos 2 */ @@ -277,13 +277,14 @@ chrp_find_bridges(void) hose->cfg_data = p; gg2_pci_config_base = p; } else if (is_pegasos == 1) { - setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc); + setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc, 0); } else if (is_pegasos == 2) { setup_peg2(hose, dev); } else if (!strncmp(model, "IBM,CPC710", 10)) { setup_indirect_pci(hose, r.start + 0x000f8000, - r.start + 0x000f8010); + r.start + 0x000f8010, + 0); if (index == 0) { dma = of_get_property(dev, "system-dma-base", &len); diff --git a/arch/powerpc/platforms/embedded6xx/linkstation.c b/arch/powerpc/platforms/embedded6xx/linkstation.c index f4d0a7a..bd5ca58 100644 --- a/arch/powerpc/platforms/embedded6xx/linkstation.c +++ b/arch/powerpc/platforms/embedded6xx/linkstation.c @@ -73,7 +73,7 @@ static int __init linkstation_add_bridge(struct device_node *dev) return -ENOMEM; hose->first_busno = bus_range ? bus_range[0] : 0; hose->last_busno = bus_range ? bus_range[1] : 0xff; - setup_indirect_pci(hose, 0xfec00000, 0xfee00000); + setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); /* Interpret the "ranges" property */ /* This also maps the I/O region and sets isa_io/mem_base */ diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index c6a30f9..1426642 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -185,7 +185,8 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) hose->first_busno = bus_range ? bus_range[0] : 0x0; hose->last_busno = bus_range ? bus_range[1] : 0xff; - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); + setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, + INDIRECT_PCI_BIG_ENDIAN); setup_pci_cmd(hose); /* check PCI express link status */ diff --git a/arch/powerpc/sysdev/grackle.c b/arch/powerpc/sysdev/grackle.c index 4205362..11ad562 100644 --- a/arch/powerpc/sysdev/grackle.c +++ b/arch/powerpc/sysdev/grackle.c @@ -55,7 +55,7 @@ static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable) void __init setup_grackle(struct pci_controller *hose) { - setup_indirect_pci(hose, 0xfec00000, 0xfee00000); + setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); if (machine_is_compatible("PowerMac1,1")) pci_assign_all_buses = 1; if (machine_is_compatible("AAPL,PowerBook1998")) diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c index ad341f5..33b9b69 100644 --- a/arch/powerpc/sysdev/indirect_pci.c +++ b/arch/powerpc/sysdev/indirect_pci.c @@ -26,6 +26,16 @@ #define PCI_CFG_OUT out_le32 #endif +static void pci_cfg_out_le(volatile u32 __iomem *addr, u32 val) +{ + out_le32(addr, val); +} + +static void pci_cfg_out_be(volatile u32 __iomem *addr, u32 val) +{ + out_be32(addr, val); +} + static int indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) @@ -58,7 +68,7 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, else reg = offset & 0xfc; - PCI_CFG_OUT(hose->cfg_addr, + hose->pci_cfg_out(hose->cfg_addr, (0x80000000 | (bus_no << 16) | (devfn << 8) | reg | cfg_type)); @@ -113,7 +123,7 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, else reg = offset & 0xfc; - PCI_CFG_OUT(hose->cfg_addr, + hose->pci_cfg_out(hose->cfg_addr, (0x80000000 | (bus_no << 16) | (devfn << 8) | reg | cfg_type)); @@ -149,7 +159,7 @@ static struct pci_ops indirect_pci_ops = }; void __init -setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) +setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data, u32 flags) { unsigned long base = cfg_addr & PAGE_MASK; void __iomem *mbase; @@ -160,4 +170,8 @@ setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE); hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK); hose->ops = &indirect_pci_ops; + if (flags & INDIRECT_PCI_BIG_ENDIAN) + hose->pci_cfg_out = pci_cfg_out_be; + else + hose->pci_cfg_out = pci_cfg_out_le; } diff --git a/arch/powerpc/sysdev/mv64x60_pci.c b/arch/powerpc/sysdev/mv64x60_pci.c index 45db86c..9b3baa7 100644 --- a/arch/powerpc/sysdev/mv64x60_pci.c +++ b/arch/powerpc/sysdev/mv64x60_pci.c @@ -144,7 +144,7 @@ static int __init mv64x60_add_bridge(struct device_node *dev) hose->first_busno = bus_range ? bus_range[0] : 0; hose->last_busno = bus_range ? bus_range[1] : 0xff; - setup_indirect_pci(hose, rsrc.start, rsrc.start + 4); + setup_indirect_pci(hose, rsrc.start, rsrc.start + 4, 0); hose->self_busno = hose->first_busno; printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. " diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h index 13cb0a9..435bfe8 100644 --- a/include/asm-powerpc/pci-bridge.h +++ b/include/asm-powerpc/pci-bridge.h @@ -36,6 +36,7 @@ struct pci_controller { struct pci_ops *ops; volatile unsigned int __iomem *cfg_addr; volatile void __iomem *cfg_data; + void (*pci_cfg_out)(volatile u32 __iomem *cfg_addr, u32 val); /* * Used for variants of PCI indirect handling and possible quirks: @@ -87,8 +88,10 @@ int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, extern int early_find_capability(struct pci_controller *hose, int bus, int dev_fn, int cap); +/* Set this for a big-endian cfg_addr */ +#define INDIRECT_PCI_BIG_ENDIAN 0x00000001 extern void setup_indirect_pci(struct pci_controller* hose, - u32 cfg_addr, u32 cfg_data); + u32 cfg_addr, u32 cfg_data, u32 flags); extern void setup_grackle(struct pci_controller *hose); #else @@ -128,6 +131,7 @@ struct pci_controller { struct pci_ops *ops; volatile unsigned int __iomem *cfg_addr; volatile void __iomem *cfg_data; + void (*pci_cfg_out)(volatile u32 __iomem *cfg_addr, u32 val); /* Currently, we limit ourselves to 1 IO range and 3 mem * ranges since the common pci_bus structure can't handle more -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 15/25] [POWERPC] Add basic PCI/PCI Express support for 8544DS board 2007-07-23 20:50 ` [PATCH 14/25] [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime Kumar Gala @ 2007-07-23 20:50 ` Kumar Gala 2007-07-23 20:50 ` [PATCH 16/25] [POWERPC] Provide ability to setup P2P bridge registers from struct resource Kumar Gala 2007-07-24 1:43 ` [PATCH 14/25] [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime Benjamin Herrenschmidt 1 sibling, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:50 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev; +Cc: York Sun From: Roy Zang <tie-fei.zang@freescale.com> Add basic support for the PCIe PHB and enable the ULI bridge. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/boot/dts/mpc8544ds.dts | 211 ++++++++++++++++++ arch/powerpc/configs/mpc8544_ds_defconfig | 333 ++++++++++++++++++----------- arch/powerpc/platforms/85xx/Kconfig | 1 + arch/powerpc/platforms/85xx/mpc8544_ds.c | 241 +++++++++++++++++++++- arch/powerpc/sysdev/fsl_pci.c | 2 + 5 files changed, 662 insertions(+), 126 deletions(-) diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 8285925..4a900c6 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts @@ -137,6 +137,217 @@ interrupt-parent = <&mpic>; }; + pci@8000 { + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + + /* IDSEL 0x11 J17 Slot 1 */ + 8800 0 0 1 &mpic 2 1 + 8800 0 0 2 &mpic 3 1 + 8800 0 0 3 &mpic 4 1 + 8800 0 0 4 &mpic 1 1 + + /* IDSEL 0x12 J16 Slot 2 */ + + 9000 0 0 1 &mpic 3 1 + 9000 0 0 2 &mpic 4 1 + 9000 0 0 3 &mpic 2 1 + 9000 0 0 4 &mpic 1 1>; + + interrupt-parent = <&mpic>; + interrupts = <18 2>; + bus-range = <0 ff>; + ranges = <02000000 0 80000000 80000000 0 10000000 + 01000000 0 00000000 e2000000 0 00800000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <8000 1000>; + }; + + pcie@9000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <9000 1000>; + bus-range = <0 ff>; + ranges = <02000000 0 90000000 90000000 0 10000000 + 01000000 0 00000000 e3000000 0 00800000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <1a 2>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 4 1 + 0000 0 0 2 &mpic 5 1 + 0000 0 0 3 &mpic 6 1 + 0000 0 0 4 &mpic 7 1 + >; + }; + + pcie@a000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <a000 1000>; + bus-range = <0 ff>; + ranges = <02000000 0 a0000000 a0000000 0 10000000 + 01000000 0 00000000 e2800000 0 00800000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <19 2>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 0 1 + 0000 0 0 2 &mpic 1 1 + 0000 0 0 3 &mpic 2 1 + 0000 0 0 4 &mpic 3 1 + >; + }; + + pcie@b000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <b000 1000>; + bus-range = <0 ff>; + ranges = <02000000 0 b0000000 b0000000 0 10000000 + 01000000 0 00000000 e3800000 0 00800000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <1b 2>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + + // IDSEL 0x1a + d000 0 0 1 &i8259 6 2 + d000 0 0 2 &i8259 3 2 + d000 0 0 3 &i8259 4 2 + d000 0 0 4 &i8259 5 2 + + // IDSEL 0x1b + d800 0 0 1 &i8259 5 2 + d800 0 0 2 &i8259 0 0 + d800 0 0 3 &i8259 0 0 + d800 0 0 4 &i8259 0 0 + + // IDSEL 0x1c USB + e000 0 0 1 &i8259 9 2 + e000 0 0 2 &i8259 a 2 + e000 0 0 3 &i8259 c 2 + e000 0 0 4 &i8259 7 2 + + // IDSEL 0x1d Audio + e800 0 0 1 &i8259 9 2 + e800 0 0 2 &i8259 a 2 + e800 0 0 3 &i8259 b 2 + e800 0 0 4 &i8259 0 0 + + // IDSEL 0x1e Legacy + f000 0 0 1 &i8259 c 2 + f000 0 0 2 &i8259 0 0 + f000 0 0 3 &i8259 0 0 + f000 0 0 4 &i8259 0 0 + + // IDSEL 0x1f IDE/SATA + f800 0 0 1 &i8259 6 2 + f800 0 0 2 &i8259 0 0 + f800 0 0 3 &i8259 0 0 + f800 0 0 4 &i8259 0 0 + >; + uli1575@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + ranges = <02000000 0 b0000000 + 02000000 0 b0000000 + 0 10000000 + 01000000 0 00000000 + 01000000 0 00000000 + 0 00080000>; + + pci_bridge@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + ranges = <02000000 0 b0000000 + 02000000 0 b0000000 + 0 20000000 + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; + + isa@1e { + device_type = "isa"; + #interrupt-cells = <2>; + #size-cells = <1>; + #address-cells = <2>; + reg = <f000 0 0 0 0>; + ranges = <1 0 01000000 0 0 + 00001000>; + interrupt-parent = <&i8259>; + + i8259: interrupt-controller@20 { + reg = <1 20 2 + 1 a0 2 + 1 4d0 2>; + clock-frequency = <0>; + interrupt-controller; + device_type = "interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <2>; + built-in; + compatible = "chrp,iic"; + interrupts = <9 2>; + interrupt-parent = + <&mpic>; + }; + + i8042@60 { + #size-cells = <0>; + #address-cells = <1>; + reg = <1 60 1 1 64 1>; + interrupts = <1 3 c 3>; + interrupt-parent = + <&i8259>; + + keyboard@0 { + reg = <0>; + compatible = "pnpPNP,303"; + }; + + mouse@1 { + reg = <1>; + compatible = "pnpPNP,f03"; + }; + }; + + rtc@70 { + compatible = + "pnpPNP,b00"; + reg = <1 70 2>; + }; + + gpio@400 { + reg = <1 400 80>; + }; + }; + }; + }; + + }; + mpic: pic@40000 { clock-frequency = <0>; interrupt-controller; diff --git a/arch/powerpc/configs/mpc8544_ds_defconfig b/arch/powerpc/configs/mpc8544_ds_defconfig index c40a25a..7995231 100644 --- a/arch/powerpc/configs/mpc8544_ds_defconfig +++ b/arch/powerpc/configs/mpc8544_ds_defconfig @@ -1,9 +1,26 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.22-rc7 -# Sun Jul 1 23:56:58 2007 +# Linux kernel version: 2.6.22 +# Fri Jul 20 14:09:13 2007 # # CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_6xx is not set +CONFIG_PPC_85xx=y +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_85xx=y +CONFIG_E500=y +CONFIG_BOOKE=y +CONFIG_FSL_BOOKE=y +# CONFIG_PHYS_64BIT is not set +# CONFIG_SPE is not set +# CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_PPC_MERGE=y CONFIG_MMU=y @@ -14,6 +31,7 @@ CONFIG_ARCH_HAS_ILOG2_U32=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set CONFIG_PPC=y CONFIG_EARLY_PRINTK=y CONFIG_GENERIC_NVRAM=y @@ -25,28 +43,8 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y - -# -# Processor support -# -# CONFIG_CLASSIC32 is not set -# CONFIG_PPC_82xx is not set -# CONFIG_PPC_83xx is not set -CONFIG_PPC_85xx=y -# CONFIG_PPC_86xx is not set -# CONFIG_PPC_8xx is not set -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_E200 is not set -CONFIG_85xx=y -CONFIG_E500=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set -CONFIG_BOOKE=y -CONFIG_FSL_BOOKE=y -# CONFIG_PHYS_64BIT is not set -# CONFIG_SPE is not set -# CONFIG_PPC_MM_SLICES is not set CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # @@ -63,13 +61,12 @@ CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y -CONFIG_IPC_NS=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set # CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set +# CONFIG_USER_NS is not set CONFIG_AUDIT=y # CONFIG_AUDITSYSCALL is not set CONFIG_IKCONFIG=y @@ -86,7 +83,7 @@ CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y @@ -105,24 +102,17 @@ CONFIG_SLAB=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 - -# -# Loadable module support -# CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_KMOD=y - -# -# Block layer -# CONFIG_BLOCK=y CONFIG_LBD=y # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set # # IO Schedulers @@ -153,7 +143,7 @@ CONFIG_MPC8544_DS=y CONFIG_MPC85xx=y CONFIG_MPIC=y # CONFIG_MPIC_WEIRD is not set -# CONFIG_PPC_I8259 is not set +CONFIG_PPC_I8259=y # CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set # CONFIG_PPC_MPC106 is not set @@ -191,6 +181,8 @@ CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y CONFIG_PROC_DEVICETREE=y CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="root=/dev/sda3 rw console=ttyS0,115200" @@ -205,15 +197,21 @@ CONFIG_ISA_DMA_API=y # CONFIG_ZONE_DMA=y CONFIG_PPC_INDIRECT_PCI=y -CONFIG_PPC_INDIRECT_PCI_BE=y CONFIG_FSL_SOC=y -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_FSL_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +# CONFIG_PCIEPORTBUS is not set +CONFIG_ARCH_SUPPORTS_MSI=y +# CONFIG_PCI_MSI is not set +# CONFIG_PCI_DEBUG is not set # # PCCARD (PCMCIA/CardBus) support # +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set # # Advanced setup @@ -254,7 +252,6 @@ CONFIG_ASK_IP_FIB_HASH=y CONFIG_IP_FIB_HASH=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y -# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y @@ -330,6 +327,7 @@ CONFIG_FIB_RULES=y # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -340,45 +338,35 @@ CONFIG_FIB_RULES=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# # CONFIG_CONNECTOR is not set # CONFIG_MTD is not set - -# -# Parallel port support -# # CONFIG_PARPORT is not set - -# -# Plug and Play support -# -# CONFIG_PNPACPI is not set - -# -# Block devices -# +CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set CONFIG_BLK_DEV_NBD=y +# CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=2 CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set - -# -# Misc devices -# -# CONFIG_BLINK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set # CONFIG_IDE is not set # @@ -386,6 +374,7 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y +CONFIG_SCSI_DMA=y # CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y @@ -422,25 +411,120 @@ CONFIG_SCSI_WAIT_SCAN=m # SCSI low-level drivers # # CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_SVW is not set +# CONFIG_ATA_PIIX is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set # CONFIG_PATA_PLATFORM is not set +# CONFIG_MD is not set # -# Multi-device support (RAID and LVM) +# Fusion MPT device support # -# CONFIG_MD is not set -# CONFIG_MACINTOSH_DRIVERS is not set +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set # -# Network device support +# IEEE 1394 (FireWire) support # +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_ARCNET is not set CONFIG_PHYLIB=y # @@ -454,17 +538,44 @@ CONFIG_PHYLIB=y CONFIG_VITESSE_PHY=y # CONFIG_SMSC_PHY is not set # CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set # CONFIG_FIXED_PHY is not set - -# -# Ethernet (10 or 100Mbit) -# CONFIG_NET_ETHERNET=y CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set CONFIG_GIANFAR=y CONFIG_GFAR_NAPI=y +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TR is not set # # Wireless LAN @@ -472,21 +583,16 @@ CONFIG_NETDEV_10000=y # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set # CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_NET_FC is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set - -# -# Telephony Support -# # CONFIG_PHONE is not set # @@ -521,6 +627,7 @@ CONFIG_INPUT=y CONFIG_SERIO=y CONFIG_SERIO_I8042=y CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set # CONFIG_GAMEPORT is not set @@ -539,6 +646,7 @@ CONFIG_HW_CONSOLE=y # CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_8250_EXTENDED is not set @@ -550,14 +658,11 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set # CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set @@ -565,12 +670,12 @@ CONFIG_NVRAM=y CONFIG_GEN_RTC=y CONFIG_GEN_RTC_X=y # CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# # CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y # CONFIG_I2C is not set # @@ -578,11 +683,8 @@ CONFIG_GEN_RTC_X=y # # CONFIG_SPI is not set # CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# # CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # @@ -655,19 +757,14 @@ CONFIG_DUMMY_CONSOLE=y # Sound # # CONFIG_SOUND is not set - -# -# HID Devices -# +CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -691,14 +788,7 @@ CONFIG_HID=y # # LED Triggers # - -# -# InfiniBand support -# - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# +# CONFIG_INFINIBAND is not set # # Real Time Clock @@ -719,19 +809,13 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_TEST is not set # -# I2C RTC drivers -# - -# -# SPI RTC drivers -# - -# # Platform RTC drivers # +# CONFIG_RTC_DRV_CMOS is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -752,6 +836,11 @@ CONFIG_RTC_INTF_DEV=y # # +# Userspace I/O +# +# CONFIG_UIO is not set + +# # File systems # CONFIG_EXT2_FS=y @@ -859,7 +948,6 @@ CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types @@ -941,6 +1029,7 @@ CONFIG_BITREVERSE=y # CONFIG_CRC16 is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y +# CONFIG_CRC7 is not set CONFIG_LIBCRC32C=m CONFIG_ZLIB_INFLATE=y CONFIG_PLIST=y @@ -965,6 +1054,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set # CONFIG_DEBUG_SLAB is not set @@ -996,10 +1086,6 @@ CONFIG_FORCED_INLINING=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set - -# -# Cryptographic options -# CONFIG_CRYPTO=y CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_BLKCIPHER=y @@ -1038,7 +1124,4 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# +CONFIG_CRYPTO_HW=y diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 4661fcc..99bb74d 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -30,6 +30,7 @@ config MPC85xx_MDS config MPC8544_DS bool "Freescale MPC8544 DS" + select PPC_I8259 select DEFAULT_UIMAGE help This option enables support for the MPC8544 DS board diff --git a/arch/powerpc/platforms/85xx/mpc8544_ds.c b/arch/powerpc/platforms/85xx/mpc8544_ds.c index 6fb90aa..4905f6f 100644 --- a/arch/powerpc/platforms/85xx/mpc8544_ds.c +++ b/arch/powerpc/platforms/85xx/mpc8544_ds.c @@ -2,6 +2,8 @@ * MPC8544 DS Board Setup * * Author Xianghua Xiao (x.xiao@freescale.com) + * Roy Zang <tie-fei.zang@freescale.com> + * - Add PCI/PCI Exprees support * Copyright 2007 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it @@ -12,13 +14,16 @@ #include <linux/stddef.h> #include <linux/kernel.h> +#include <linux/pci.h> #include <linux/kdev_t.h> #include <linux/delay.h> #include <linux/seq_file.h> +#include <linux/interrupt.h> #include <asm/system.h> #include <asm/time.h> #include <asm/machdep.h> +#include <asm/pci-bridge.h> #include <asm/mpc85xx.h> #include <mm/mmu_decl.h> #include <asm/prom.h> @@ -27,6 +32,7 @@ #include <asm/i8259.h> #include <sysdev/fsl_soc.h> +#include <sysdev/fsl_pci.h> #include "mpc85xx.h" #undef DEBUG @@ -37,6 +43,17 @@ #define DBG(fmt, args...) #endif +#ifdef CONFIG_PPC_I8259 +static void mpc8544_8259_cascade(unsigned int irq, struct irq_desc *desc) +{ + unsigned int cascade_irq = i8259_irq(); + + if (cascade_irq != NO_IRQ) { + generic_handle_irq(cascade_irq); + } + desc->chip->eoi(irq); +} +#endif /* CONFIG_PPC_I8259 */ void __init mpc8544_ds_pic_init(void) { @@ -96,19 +113,240 @@ void __init mpc8544_ds_pic_init(void) #endif /* CONFIG_PPC_I8259 */ } +#ifdef CONFIG_PCI +enum pirq { PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH }; + +/* + * Value in table -- IRQ number + */ +const unsigned char uli1575_irq_route_table[16] = { + 0, /* 0: Reserved */ + 0x8, + 0, /* 2: Reserved */ + 0x2, + 0x4, + 0x5, + 0x7, + 0x6, + 0, /* 8: Reserved */ + 0x1, + 0x3, + 0x9, + 0xb, + 0, /* 13: Reserved */ + 0xd, + 0xf, +}; + +static int __devinit +get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin) +{ + struct of_irq oirq; + u32 laddr[3]; + struct device_node *hosenode = hose ? hose->arch_data : NULL; + + if (!hosenode) + return -EINVAL; + + laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8); + laddr[1] = laddr[2] = 0; + of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq); + DBG("mpc8544_ds: pci irq addr %x, slot %d, pin %d, irq %d\n", + laddr[0], slot, pin, oirq.specifier[0]); + return oirq.specifier[0]; +} + +/*8259*/ +static void __devinit quirk_uli1575(struct pci_dev *dev) +{ + unsigned short temp; + struct pci_controller *hose = pci_bus_to_host(dev->bus); + unsigned char irq2pin[16]; + unsigned long pirq_map_word = 0; + u32 irq; + int i; + + /* + * ULI1575 interrupts route setup + */ + memset(irq2pin, 0, 16); /* Initialize default value 0 */ + + irq2pin[6]=PIRQA+3; /* enabled mapping for IRQ6 to PIRQD, used by SATA */ + + /* + * PIRQE -> PIRQF mapping set manually + * + * IRQ pin IRQ# + * PIRQE ---- 9 + * PIRQF ---- 10 + * PIRQG ---- 11 + * PIRQH ---- 12 + */ + for (i = 0; i < 4; i++) + irq2pin[i + 9] = PIRQE + i; + + /* Set IRQ-PIRQ Mapping to ULI1575 */ + for (i = 0; i < 16; i++) + if (irq2pin[i]) + pirq_map_word |= (uli1575_irq_route_table[i] & 0xf) + << ((irq2pin[i] - PIRQA) * 4); + + pirq_map_word |= 1<<26; /* disable INTx in EP mode*/ + + /* ULI1575 IRQ mapping conf register default value is 0xb9317542 */ + DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n", + (int)pirq_map_word); + pci_write_config_dword(dev, 0x48, pirq_map_word); + +#define ULI1575_SET_DEV_IRQ(slot, pin, reg) \ + do { \ + int irq; \ + irq = get_pci_irq_from_of(hose, slot, pin); \ + if (irq > 0 && irq < 16) \ + pci_write_config_byte(dev, reg, irq2pin[irq]); \ + else \ + printk(KERN_WARNING "ULI1575 device" \ + "(slot %d, pin %d) irq %d is invalid.\n", \ + slot, pin, irq); \ + } while(0) + + /* USB 1.1 OHCI controller 1, slot 28, pin 1 */ + ULI1575_SET_DEV_IRQ(28, 1, 0x86); + + /* USB 1.1 OHCI controller 2, slot 28, pin 2 */ + ULI1575_SET_DEV_IRQ(28, 2, 0x87); + + /* USB 1.1 OHCI controller 3, slot 28, pin 3 */ + ULI1575_SET_DEV_IRQ(28, 3, 0x88); + + /* USB 2.0 controller, slot 28, pin 4 */ + irq = get_pci_irq_from_of(hose, 28, 4); + if (irq >= 0 && irq <= 15) + pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]); + + /* Audio controller, slot 29, pin 1 */ + ULI1575_SET_DEV_IRQ(29, 1, 0x8a); + + /* Modem controller, slot 29, pin 2 */ + ULI1575_SET_DEV_IRQ(29, 2, 0x8b); + + /* HD audio controller, slot 29, pin 3 */ + ULI1575_SET_DEV_IRQ(29, 3, 0x8c); + + /* SMB interrupt: slot 30, pin 1 */ + ULI1575_SET_DEV_IRQ(30, 1, 0x8e); + + /* PMU ACPI SCI interrupt: slot 30, pin 2 */ + ULI1575_SET_DEV_IRQ(30, 2, 0x8f); + + /* Serial ATA interrupt: slot 31, pin 1 */ + ULI1575_SET_DEV_IRQ(31, 1, 0x8d); + + /* Primary PATA IDE IRQ: 14 + * Secondary PATA IDE IRQ: 15 + */ + pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]); + pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]); + + /* Set IRQ14 and IRQ15 to legacy IRQs */ + pci_read_config_word(dev, 0x46, &temp); + temp |= 0xc000; + pci_write_config_word(dev, 0x46, temp); + + /* Set i8259 interrupt trigger + * IRQ 3: Level + * IRQ 4: Level + * IRQ 5: Level + * IRQ 6: Level + * IRQ 7: Level + * IRQ 9: Level + * IRQ 10: Level + * IRQ 11: Level + * IRQ 12: Level + * IRQ 14: Edge + * IRQ 15: Edge + */ + outb(0xfa, 0x4d0); + outb(0x1e, 0x4d1); + +#undef ULI1575_SET_DEV_IRQ +} + +/* SATA */ +static void __devinit quirk_uli5288(struct pci_dev *dev) +{ + unsigned char c; + + pci_read_config_byte(dev, 0x83, &c); + c |= 0x80; /* read/write lock */ + pci_write_config_byte(dev, 0x83, c); + + pci_write_config_byte(dev, 0x09, 0x01); /* Base class code: storage */ + pci_write_config_byte(dev, 0x0a, 0x06); /* IDE disk */ + + pci_read_config_byte(dev, 0x83, &c); + c &= 0x7f; + pci_write_config_byte(dev, 0x83, c); + + pci_read_config_byte(dev, 0x84, &c); + c |= 0x01; /* emulated PATA mode enabled */ + pci_write_config_byte(dev, 0x84, c); +} + +/* PATA */ +static void __devinit quirk_uli5229(struct pci_dev *dev) +{ + unsigned short temp; + pci_write_config_word(dev, 0x04, 0x0405); /* MEM IO MSI */ + pci_read_config_word(dev, 0x4a, &temp); + temp |= 0x1000; /* Enable Native IRQ 14/15 */ + pci_write_config_word(dev, 0x4a, temp); +} + +/*Bridge*/ +static void __devinit early_uli5249(struct pci_dev *dev) +{ + unsigned char temp; + pci_write_config_word(dev, 0x04, 0x0007); /* mem access */ + pci_read_config_byte(dev, 0x7c, &temp); + pci_write_config_byte(dev, 0x7c, 0x80); /* R/W lock control */ + pci_write_config_byte(dev, 0x09, 0x01); /* set as pci-pci bridge */ + pci_write_config_byte(dev, 0x7c, temp); /* restore pci bus debug control */ + dev->class |= 0x1; +} + +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249); +#endif /* CONFIG_PCI */ /* * Setup the architecture */ static void __init mpc8544_ds_setup_arch(void) { +#ifdef CONFIG_PCI + struct device_node *np; +#endif + if (ppc_md.progress) ppc_md.progress("mpc8544_ds_setup_arch()", 0); +#ifdef CONFIG_PCI + for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) { + struct resource rsrc; + of_address_to_resource(np, 0, &rsrc); + if ((rsrc.start & 0xfffff) == 0xb000) + fsl_add_bridge(np, 1); + else + fsl_add_bridge(np, 0); + } +#endif + printk("MPC8544 DS board from Freescale Semiconductor\n"); } - /* * Called very early, device-tree isn't unflattened */ @@ -124,6 +362,7 @@ define_machine(mpc8544_ds) { .probe = mpc8544_ds_probe, .setup_arch = mpc8544_ds_setup_arch, .init_IRQ = mpc8544_ds_pic_init, + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, .get_irq = mpic_get_irq, .restart = mpc85xx_restart, .calibrate_decr = generic_calibrate_decr, diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 1426642..f51fedf 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -226,5 +226,7 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0020, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0021, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0024, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0025, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0030, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0031, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 16/25] [POWERPC] Provide ability to setup P2P bridge registers from struct resource 2007-07-23 20:50 ` [PATCH 15/25] [POWERPC] Add basic PCI/PCI Express support for 8544DS board Kumar Gala @ 2007-07-23 20:50 ` Kumar Gala 2007-07-23 20:50 ` [PATCH 17/25] [POWERPC] Make sure virtual P2P bridge registers are setup on PCIe PHB Kumar Gala 2007-07-24 1:45 ` [PATCH 16/25] [POWERPC] Provide ability to setup P2P bridge registers from struct resource Benjamin Herrenschmidt 0 siblings, 2 replies; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:50 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev We need the ability to set P2P bridge registers to properly setup the virtual P2P bridges that exist in PCIe controllers for some of the embedded setups. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/kernel/pci_32.c | 18 ++++++++++++------ include/asm-powerpc/pci-bridge.h | 2 ++ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c index bfcfa14..721a694 100644 --- a/arch/powerpc/kernel/pci_32.c +++ b/arch/powerpc/kernel/pci_32.c @@ -415,15 +415,13 @@ probe_resource(struct pci_bus *parent, struct resource *pr, return 0; } -static void __init -update_bridge_base(struct pci_bus *bus, int i) +void __init +update_bridge_resource(struct pci_dev *dev, struct resource *res) { - struct resource *res = bus->resource[i]; u8 io_base_lo, io_limit_lo; u16 mem_base, mem_limit; u16 cmd; unsigned long start, end, off; - struct pci_dev *dev = bus->self; struct pci_controller *hose = dev->sysdata; if (!hose) { @@ -467,12 +465,20 @@ update_bridge_base(struct pci_bus *bus, int i) pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit); } else { - DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n", - pci_name(dev), i, res->flags); + DBG(KERN_ERR "PCI: ugh, bridge %s res has flags=%lx\n", + pci_name(dev), res->flags); } pci_write_config_word(dev, PCI_COMMAND, cmd); } +static void __init +update_bridge_base(struct pci_bus *bus, int i) +{ + struct resource *res = bus->resource[i]; + struct pci_dev *dev = bus->self; + update_bridge_resource(dev, res); +} + static inline void alloc_resource(struct pci_dev *dev, int idx) { struct resource *pr, *r = &dev->resource[idx]; diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h index 435bfe8..b7d2ea4 100644 --- a/include/asm-powerpc/pci-bridge.h +++ b/include/asm-powerpc/pci-bridge.h @@ -93,6 +93,8 @@ extern int early_find_capability(struct pci_controller *hose, int bus, extern void setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data, u32 flags); extern void setup_grackle(struct pci_controller *hose); +extern void __init update_bridge_resource(struct pci_dev *dev, + struct resource *res); #else -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 17/25] [POWERPC] Make sure virtual P2P bridge registers are setup on PCIe PHB 2007-07-23 20:50 ` [PATCH 16/25] [POWERPC] Provide ability to setup P2P bridge registers from struct resource Kumar Gala @ 2007-07-23 20:50 ` Kumar Gala 2007-07-23 20:50 ` [PATCH 18/25] [POWERPC] FSL: Add support for PCI-X controllers Kumar Gala 2007-07-24 1:45 ` [PATCH 16/25] [POWERPC] Provide ability to setup P2P bridge registers from struct resource Benjamin Herrenschmidt 1 sibling, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:50 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev For the Freescale PCIe PHBs Not all firmwares setup the virtual P2P bridge registers properly. Make sure they get setup based on what the struct pci_controller got from the device tree. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/sysdev/fsl_pci.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index f51fedf..fc3e13e 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -118,11 +118,24 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) return; } + /* Clear out any of the virtual P2P bridge registers */ + pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0); + pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, 0); + pci_write_config_byte(dev, PCI_IO_BASE, 0x10); + pci_write_config_byte(dev, PCI_IO_LIMIT, 0); + pci_write_config_word(dev, PCI_MEMORY_BASE, 0x10); + pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0); + pci_write_config_word(dev, PCI_PREF_BASE_UPPER32, 0x0); + pci_write_config_word(dev, PCI_PREF_LIMIT_UPPER32, 0x0); + pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10); + pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0); + if (hose->io_resource.flags) { res = &dev->resource[res_idx++]; res->start = hose->io_resource.start; res->end = hose->io_resource.end; res->flags = hose->io_resource.flags; + update_bridge_resource(dev, res); } for (i = 0; i < 3; i++) { @@ -130,6 +143,7 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) res->start = hose->mem_resources[i].start; res->end = hose->mem_resources[i].end; res->flags = hose->mem_resources[i].flags; + update_bridge_resource(dev, res); } } -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 18/25] [POWERPC] FSL: Add support for PCI-X controllers 2007-07-23 20:50 ` [PATCH 17/25] [POWERPC] Make sure virtual P2P bridge registers are setup on PCIe PHB Kumar Gala @ 2007-07-23 20:50 ` Kumar Gala 2007-07-23 20:50 ` [PATCH 19/25] [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line Kumar Gala 0 siblings, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:50 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev Some set of 85xx platforms have PCI-X controllers. The old arch/ppc code setup these controllers and we haven't moved it over to arch/powerpc. We use the PCI-X Capabilties to know if we are in PCI-X mode instead of the Global Utilities PORDEVSR. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/sysdev/fsl_pci.c | 13 ++++++++++++- 1 files changed, 12 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index fc3e13e..06a2a9b 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -89,11 +89,22 @@ void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc) void __init setup_pci_cmd(struct pci_controller *hose) { u16 cmd; + int cap_x; + early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); - early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); + + cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); + if (cap_x) { + int pci_x_cmd = cap_x + PCI_X_CMD; + cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); + } else { + early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); + } } static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 19/25] [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line. 2007-07-23 20:50 ` [PATCH 18/25] [POWERPC] FSL: Add support for PCI-X controllers Kumar Gala @ 2007-07-23 20:50 ` Kumar Gala 2007-07-23 20:50 ` [PATCH 20/25] [POWERPC] 85xxCDS: Make sure restart resets the PCI bus Kumar Gala 2007-07-24 1:48 ` [PATCH 19/25] [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line Benjamin Herrenschmidt 0 siblings, 2 replies; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:50 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev From: Randy Vinson <rvinson@mvista.com> The Freescale MPC8555CDS and MPC8548CDS reference hardware has a legacy 8259 interrupt controller pair contained within a VIA VT82C686B Southbridge on the main carrier board. The processor complex plugs into the carrier card using a PCI slot which limits the available interrupts to the INTA-INTD PCI interrupts. The output of the 8259 cascade pair is routed through a gate array and connected to the PCI INTA interrupt line. The normal interrupt chaining hook (set_irq_chained_handler) does not allow sharing of the chained interrupt which prevents the use of PCI INTA by PCI devices. This patch allows the 8259 cascade pair to share their interrupt line with PCI devices. NOTE: The addition of the .end routine for the MPIC is not strictly necessary for this patch. It's there so this code will run from within the threaded interrupt context used by the Real Time patch. Signed-off-by: Randy Vinson <rvinson@mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/platforms/85xx/Kconfig | 1 + arch/powerpc/platforms/85xx/mpc85xx_cds.c | 37 ++++++++++++++++++++++++---- arch/powerpc/sysdev/mpic.c | 1 + 3 files changed, 33 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 99bb74d..f581840 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -18,6 +18,7 @@ config MPC8560_ADS config MPC85xx_CDS bool "Freescale MPC85xx CDS" select DEFAULT_UIMAGE + select PPC_I8259 help This option enables support for the MPC85xx CDS board diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c index 71200bd..81b7062 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c @@ -24,6 +24,7 @@ #include <linux/seq_file.h> #include <linux/initrd.h> #include <linux/module.h> +#include <linux/interrupt.h> #include <linux/fsl_devices.h> #include <asm/system.h> @@ -119,16 +120,30 @@ DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge); DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge); #ifdef CONFIG_PPC_I8259 -#warning The i8259 PIC support is currently broken -static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) +static void mpc85xx_8259_cascade_handler(unsigned int irq, + struct irq_desc *desc) { unsigned int cascade_irq = i8259_irq(); if (cascade_irq != NO_IRQ) + /* handle an interrupt from the 8259 */ generic_handle_irq(cascade_irq); - desc->chip->eoi(irq); + /* check for any interrupts from the shared IRQ line */ + handle_fasteoi_irq(irq, desc); } + +static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + +static struct irqaction mpc85xxcds_8259_irqaction = { + .handler = mpc85xx_8259_cascade_action, + .flags = IRQF_SHARED, + .mask = CPU_MASK_NONE, + .name = "8259 cascade", +}; #endif /* PPC_I8259 */ #endif /* CONFIG_PCI */ @@ -137,7 +152,7 @@ static void __init mpc85xx_cds_pic_init(void) struct mpic *mpic; struct resource r; struct device_node *np = NULL; -#ifdef CONFIG_PPC_I8259 +#if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI) struct device_node *cascade_node = NULL; int cascade_irq; #endif @@ -165,7 +180,7 @@ static void __init mpc85xx_cds_pic_init(void) mpic_init(mpic); -#ifdef CONFIG_PPC_I8259 +#if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI) /* Initialize the i8259 controller */ for_each_node_by_type(np, "interrupt-controller") if (of_device_is_compatible(np, "chrp,iic")) { @@ -187,7 +202,17 @@ static void __init mpc85xx_cds_pic_init(void) i8259_init(cascade_node, 0); of_node_put(cascade_node); - set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade); + /* + * Hook the interrupt to make sure desc->action is never NULL. + * This is required to ensure that the interrupt does not get + * disabled when the last user of the shared IRQ line frees their + * interrupt. + */ + if (setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction)) + printk(KERN_ERR "Failed to setup cascade interrupt\n"); + else + /* Success. Connect our low-level cascade handler. */ + set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler); #endif /* CONFIG_PPC_I8259 */ } diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 74c64c0..17ece50 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -836,6 +836,7 @@ static struct irq_chip mpic_irq_chip = { .mask = mpic_mask_irq, .unmask = mpic_unmask_irq, .eoi = mpic_end_irq, + .end = mpic_unmask_irq, .set_type = mpic_set_irq_type, }; -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 20/25] [POWERPC] 85xxCDS: Make sure restart resets the PCI bus. 2007-07-23 20:50 ` [PATCH 19/25] [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line Kumar Gala @ 2007-07-23 20:50 ` Kumar Gala 2007-07-23 20:50 ` [PATCH 21/25] [POWERPC] 85xxCDS: Delay 8259 cascade hookup Kumar Gala 2007-07-24 1:48 ` [PATCH 19/25] [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line Benjamin Herrenschmidt 1 sibling, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:50 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev From: Randy Vinson <rvinson@linuxbox.(none)> The current 85xxCDS restart code fails to reset the PCI bus which can lead to odd behavior after the restart. This patch uses the VIA Super Southbridge to perform a PCI reset which will reset the entire system. NOTE: Since the VIA chip is behind a PCI-to-PCI bridge which can be disabled with a switch setting, it may not be possible to perform the PCI bus reset. In this case, the code defaults to the previous restart mechanism. Signed-off-by: Randy Vinson <rvinson@mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/platforms/85xx/mpc85xx_cds.c | 35 +++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c index 81b7062..e77c869 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c @@ -69,6 +69,37 @@ static int mpc85xx_exclude_device(struct pci_controller *hose, return PCIBIOS_SUCCESSFUL; } +static void mpc85xx_cds_restart(char *cmd) +{ + struct pci_dev *dev; + u_char tmp; + + if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, + NULL))) { + + /* Use the VIA Super Southbridge to force a PCI reset */ + pci_read_config_byte(dev, 0x47, &tmp); + pci_write_config_byte(dev, 0x47, tmp | 1); + + /* Flush the outbound PCI write queues */ + pci_read_config_byte(dev, 0x47, &tmp); + + /* + * At this point, the harware reset should have triggered. + * However, if it doesn't work for some mysterious reason, + * just fall through to the default reset below. + */ + + pci_dev_put(dev); + } + + /* + * If we can't find the VIA chip (maybe the P2P bridge is disabled) + * or the VIA chip reset didn't work, just use the default reset. + */ + mpc85xx_restart(NULL); +} + static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev) { u_char c; @@ -304,7 +335,11 @@ define_machine(mpc85xx_cds) { .init_IRQ = mpc85xx_cds_pic_init, .show_cpuinfo = mpc85xx_cds_show_cpuinfo, .get_irq = mpic_get_irq, +#ifdef CONFIG_PCI + .restart = mpc85xx_cds_restart, +#else .restart = mpc85xx_restart, +#endif .calibrate_decr = generic_calibrate_decr, .progress = udbg_progress, .pcibios_fixup_bus = fsl_pcibios_fixup_bus, -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 21/25] [POWERPC] 85xxCDS: Delay 8259 cascade hookup. 2007-07-23 20:50 ` [PATCH 20/25] [POWERPC] 85xxCDS: Make sure restart resets the PCI bus Kumar Gala @ 2007-07-23 20:50 ` Kumar Gala 2007-07-23 20:50 ` [PATCH 22/25] [POWERPC] 85xxCDS: Misc 8548 PCI Corrections Kumar Gala 2007-07-24 11:52 ` [PATCH 21/25] [POWERPC] 85xxCDS: Delay 8259 cascade hookup Paul Mackerras 0 siblings, 2 replies; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:50 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev From: Randy Vinson <rvinson@mvista.com> The interrupts of an E100 card inserted in PCI slot 4 may be on at bootup. The resulting interrupt flood interacts with the 8259 cascade handler and prevents proper boot up. There is a quirk for the E100 that will disable the E100's interrupts but to use it, the 8259 cascade hookup must be delayed until after the quirk has run. This patch delays the 8259 cascade hookup by registering a device_initcall() which runs after the PCI quirk for the E100. Signed-off-by: Randy Vinson <rvinson@mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/platforms/85xx/mpc85xx_cds.c | 33 +++++++++++++++++++--------- 1 files changed, 22 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c index e77c869..902a61a 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c @@ -183,10 +183,6 @@ static void __init mpc85xx_cds_pic_init(void) struct mpic *mpic; struct resource r; struct device_node *np = NULL; -#if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI) - struct device_node *cascade_node = NULL; - int cascade_irq; -#endif np = of_find_node_by_type(np, "open-pic"); @@ -210,8 +206,16 @@ static void __init mpc85xx_cds_pic_init(void) of_node_put(np); mpic_init(mpic); +} #if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI) +static int mpc85xx_cds_8259_attach(void) +{ + int ret; + struct device_node *np = NULL; + struct device_node *cascade_node = NULL; + int cascade_irq; + /* Initialize the i8259 controller */ for_each_node_by_type(np, "interrupt-controller") if (of_device_is_compatible(np, "chrp,iic")) { @@ -221,13 +225,13 @@ static void __init mpc85xx_cds_pic_init(void) if (cascade_node == NULL) { printk(KERN_DEBUG "Could not find i8259 PIC\n"); - return; + return -ENODEV; } cascade_irq = irq_of_parse_and_map(cascade_node, 0); if (cascade_irq == NO_IRQ) { printk(KERN_ERR "Failed to map cascade interrupt\n"); - return; + return -ENXIO; } i8259_init(cascade_node, 0); @@ -239,14 +243,21 @@ static void __init mpc85xx_cds_pic_init(void) * disabled when the last user of the shared IRQ line frees their * interrupt. */ - if (setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction)) + if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) { printk(KERN_ERR "Failed to setup cascade interrupt\n"); - else - /* Success. Connect our low-level cascade handler. */ - set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler); -#endif /* CONFIG_PPC_I8259 */ + return ret; + } + + /* Success. Connect our low-level cascade handler. */ + set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler); + + return 0; } +device_initcall(mpc85xx_cds_8259_attach); + +#endif /* CONFIG_PPC_I8259 */ + /* * Setup the architecture */ -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 22/25] [POWERPC] 85xxCDS: Misc 8548 PCI Corrections. 2007-07-23 20:50 ` [PATCH 21/25] [POWERPC] 85xxCDS: Delay 8259 cascade hookup Kumar Gala @ 2007-07-23 20:50 ` Kumar Gala 2007-07-23 20:50 ` [PATCH 23/25] [POWERPC] 85xxCDS: MPC8548 DTS cleanup Kumar Gala 2007-07-24 11:52 ` [PATCH 21/25] [POWERPC] 85xxCDS: Delay 8259 cascade hookup Paul Mackerras 1 sibling, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:50 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev From: Randy Vinson <rvinson@mvista.com> Setting the host bridge @8000 as primary. Also fixing a bug in setting the USB interrupt numbers. Signed-off-by: Randy Vinson <rvinson@mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/platforms/85xx/mpc85xx_cds.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c index 902a61a..3421d60 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c @@ -129,7 +129,7 @@ static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev) /* There are two USB controllers. * Identify them by functon number */ - if (PCI_FUNC(dev->devfn)) + if (PCI_FUNC(dev->devfn) == 3) dev->irq = 11; else dev->irq = 10; @@ -297,10 +297,10 @@ static void __init mpc85xx_cds_setup_arch(void) for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) { struct resource rsrc; of_address_to_resource(np, 0, &rsrc); - if ((rsrc.start & 0xfffff) == 0x9000) - fsl_add_bridge(np, 0); - else + if ((rsrc.start & 0xfffff) == 0x8000) fsl_add_bridge(np, 1); + else + fsl_add_bridge(np, 0); } ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup; ppc_md.pci_exclude_device = mpc85xx_exclude_device; -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 23/25] [POWERPC] 85xxCDS: MPC8548 DTS cleanup. 2007-07-23 20:50 ` [PATCH 22/25] [POWERPC] 85xxCDS: Misc 8548 PCI Corrections Kumar Gala @ 2007-07-23 20:50 ` Kumar Gala 2007-07-23 20:50 ` [PATCH 24/25] [POWERPC] Add Freescale PCI VENDOR ID and 8641 device IDs Kumar Gala 2007-07-23 21:30 ` [PATCH 23/25] [POWERPC] 85xxCDS: MPC8548 DTS cleanup Scott Wood 0 siblings, 2 replies; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:50 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev From: Randy Vinson <rvinson@mvista.com> Added the P2P bridge present on the Arcadia base board and moved the VIA Southbridge behind the bridge to reflect its actual position in the bus organization. Added the RTC that's in the VIA Southbridge and expanded the ranges array for the SOC node to allow proper address translation of the RTC registers. Signed-off-by: Randy Vinson <rvinson@mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/boot/dts/mpc8548cds.dts | 124 ++++++++++++++++++++++++---------- 1 files changed, 89 insertions(+), 35 deletions(-) diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index 4770a5b..d215d21 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -44,8 +44,14 @@ #size-cells = <1>; #interrupt-cells = <2>; device_type = "soc"; - ranges = <0 e0000000 00100000>; - reg = <e0000000 00100000>; // CCSRBAR 1M + ranges = <00001000 e0001000 000ff000 + 80000000 80000000 10000000 + e2000000 e2000000 00800000 + 90000000 90000000 10000000 + e2800000 e2800000 00800000 + a0000000 a0000000 20000000 + e3000000 e3000000 01000000>; + reg = <e0000000 00001000>; // CCSRBAR bus-frequency = <0>; memory-controller@2000 { @@ -162,8 +168,8 @@ serial@4500 { device_type = "serial"; compatible = "ns16550"; - reg = <4500 100>; // reg base, size - clock-frequency = <0>; // should we fill in in uboot? + reg = <4500 100>; // reg base, size + clock-frequency = <0>; // should we fill in in uboot? interrupts = <2a 2>; interrupt-parent = <&mpic>; }; @@ -172,7 +178,7 @@ device_type = "serial"; compatible = "ns16550"; reg = <4600 100>; // reg base, size - clock-frequency = <0>; // should we fill in in uboot? + clock-frequency = <0>; // should we fill in in uboot? interrupts = <2a 2>; interrupt-parent = <&mpic>; }; @@ -183,8 +189,8 @@ fsl,has-rstcr; }; - pci1: pci@8000 { - interrupt-map-mask = <1f800 0 0 7>; + pci@8000 { + interrupt-map-mask = <f800 0 0 7>; interrupt-map = < /* IDSEL 0x4 (PCIX Slot 2) */ 02000 0 0 1 &mpic 0 1 @@ -244,19 +250,7 @@ 0E000 0 0 1 &mpic 0 1 0E000 0 0 2 &mpic 1 1 0E000 0 0 3 &mpic 2 1 - 0E000 0 0 4 &mpic 3 1 - - /* bus 1 , idsel 0x2 Tsi310 bridge secondary */ - 11000 0 0 1 &mpic 2 1 - 11000 0 0 2 &mpic 3 1 - 11000 0 0 3 &mpic 0 1 - 11000 0 0 4 &mpic 1 1 - - /* VIA chip */ - 12000 0 0 1 &mpic 0 1 - 12000 0 0 2 &mpic 1 1 - 12000 0 0 3 &mpic 2 1 - 12000 0 0 4 &mpic 3 1>; + 0E000 0 0 4 &mpic 3 1>; interrupt-parent = <&mpic>; interrupts = <18 2>; @@ -271,18 +265,78 @@ compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; device_type = "pci"; - i8259@4 { - clock-frequency = <0>; - interrupt-controller; - device_type = "interrupt-controller"; - reg = <12000 0 0 0 1>; - #address-cells = <0>; - #interrupt-cells = <2>; - built-in; - compatible = "chrp,iic"; - big-endian; - interrupts = <1>; - interrupt-parent = <&pci1>; + pci_bridge@1c { + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + + /* IDSEL 0x00 (PrPMC Site) */ + 0000 0 0 1 &mpic 0 1 + 0000 0 0 2 &mpic 1 1 + 0000 0 0 3 &mpic 2 1 + 0000 0 0 4 &mpic 3 1 + + /* IDSEL 0x04 (VIA chip) */ + 2000 0 0 1 &mpic 0 1 + 2000 0 0 2 &mpic 1 1 + 2000 0 0 3 &mpic 2 1 + 2000 0 0 4 &mpic 3 1 + + /* IDSEL 0x05 (8139) */ + 2800 0 0 1 &mpic 1 1 + + /* IDSEL 0x06 (Slot 6) */ + 3000 0 0 1 &mpic 2 1 + 3000 0 0 2 &mpic 3 1 + 3000 0 0 3 &mpic 0 1 + 3000 0 0 4 &mpic 1 1 + + /* IDESL 0x07 (Slot 7) */ + 3800 0 0 1 &mpic 3 1 + 3800 0 0 2 &mpic 0 1 + 3800 0 0 3 &mpic 1 1 + 3800 0 0 4 &mpic 2 1>; + + reg = <e000 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + ranges = <02000000 0 80000000 + 02000000 0 80000000 + 0 20000000 + 01000000 0 00000000 + 01000000 0 00000000 + 0 00080000>; + clock-frequency = <1fca055>; + + isa@4 { + device_type = "isa"; + #interrupt-cells = <2>; + #size-cells = <1>; + #address-cells = <2>; + reg = <2000 0 0 0 0>; + ranges = <1 0 01000000 0 0 00001000>; + interrupt-parent = <&i8259>; + + i8259: interrupt-controller@20 { + clock-frequency = <0>; + interrupt-controller; + device_type = "interrupt-controller"; + reg = <1 20 2 + 1 a0 2 + 1 4d0 2>; + #address-cells = <0>; + #interrupt-cells = <2>; + built-in; + compatible = "chrp,iic"; + interrupts = <0 1>; + interrupt-parent = <&mpic>; + }; + + rtc@70 { + compatible = "pnpPNP,b00"; + reg = <1 70 2>; + }; + }; }; }; @@ -292,9 +346,9 @@ /* IDSEL 0x15 */ a800 0 0 1 &mpic b 1 - a800 0 0 2 &mpic b 1 - a800 0 0 3 &mpic b 1 - a800 0 0 4 &mpic b 1>; + a800 0 0 2 &mpic 1 1 + a800 0 0 3 &mpic 2 1 + a800 0 0 4 &mpic 3 1>; interrupt-parent = <&mpic>; interrupts = <19 2>; -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 24/25] [POWERPC] Add Freescale PCI VENDOR ID and 8641 device IDs 2007-07-23 20:50 ` [PATCH 23/25] [POWERPC] 85xxCDS: MPC8548 DTS cleanup Kumar Gala @ 2007-07-23 20:50 ` Kumar Gala 2007-07-23 20:50 ` [PATCH 25/25] [POWERPC] 85xx: Added needed MPC85xx PCI " Kumar Gala 2007-07-23 21:30 ` [PATCH 23/25] [POWERPC] 85xxCDS: MPC8548 DTS cleanup Scott Wood 1 sibling, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:50 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev From: Jon Loeliger <jdl@freescale.com> Also add 8641/8641D device IDs as well. All of which already exist or have been submitted to The Linux PCI ID Repository at: http://pci-ids.ucw.cz/ CC-to: pci-ids@ucw.cz Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/sysdev/fsl_pci.c | 4 ++-- include/linux/pci_ids.h | 4 ++++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 06a2a9b..267edbd 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -253,5 +253,5 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0024, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0025, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0030, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0031, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent); diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index cbabb9c..3c870f1 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2075,6 +2075,10 @@ #define PCI_VENDOR_ID_TDI 0x192E #define PCI_DEVICE_ID_TDI_EHCI 0x0101 +#define PCI_VENDOR_ID_FREESCALE 0x1957 +#define PCI_DEVICE_ID_MPC8641 0x7010 +#define PCI_DEVICE_ID_MPC8641D 0x7011 + #define PCI_VENDOR_ID_PASEMI 0x1959 #define PCI_VENDOR_ID_ATTANSIC 0x1969 -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 25/25] [POWERPC] 85xx: Added needed MPC85xx PCI device IDs 2007-07-23 20:50 ` [PATCH 24/25] [POWERPC] Add Freescale PCI VENDOR ID and 8641 device IDs Kumar Gala @ 2007-07-23 20:50 ` Kumar Gala 0 siblings, 0 replies; 39+ messages in thread From: Kumar Gala @ 2007-07-23 20:50 UTC (permalink / raw) To: Benjamin Herrenschmidt, linuxppc-dev Added the MPC85xx PCI device IDs that we need for the quirks we have. Also, fixed the MPC8567E, MPC8567 device IDs which had the wrong value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/sysdev/fsl_pci.c | 26 +++++++++++++------------- include/linux/pci_ids.h | 13 +++++++++++++ 2 files changed, 26 insertions(+), 13 deletions(-) diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 267edbd..9298da8 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -240,18 +240,18 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) return 0; } -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0012, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0013, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0014, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0015, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0018, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0019, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x001a, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0020, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0021, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0024, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0025, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0030, quirk_fsl_pcie_transparent); -DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0031, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent); diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 3c870f1..c086a70 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2076,6 +2076,19 @@ #define PCI_DEVICE_ID_TDI_EHCI 0x0101 #define PCI_VENDOR_ID_FREESCALE 0x1957 +#define PCI_DEVICE_ID_MPC8548E 0x0012 +#define PCI_DEVICE_ID_MPC8548 0x0013 +#define PCI_DEVICE_ID_MPC8543E 0x0014 +#define PCI_DEVICE_ID_MPC8543 0x0015 +#define PCI_DEVICE_ID_MPC8547E 0x0018 +#define PCI_DEVICE_ID_MPC8545E 0x0019 +#define PCI_DEVICE_ID_MPC8545 0x001a +#define PCI_DEVICE_ID_MPC8568E 0x0020 +#define PCI_DEVICE_ID_MPC8568 0x0021 +#define PCI_DEVICE_ID_MPC8567E 0x0022 +#define PCI_DEVICE_ID_MPC8567 0x0023 +#define PCI_DEVICE_ID_MPC8544E 0x0030 +#define PCI_DEVICE_ID_MPC8544 0x0031 #define PCI_DEVICE_ID_MPC8641 0x7010 #define PCI_DEVICE_ID_MPC8641D 0x7011 -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 23/25] [POWERPC] 85xxCDS: MPC8548 DTS cleanup. 2007-07-23 20:50 ` [PATCH 23/25] [POWERPC] 85xxCDS: MPC8548 DTS cleanup Kumar Gala 2007-07-23 20:50 ` [PATCH 24/25] [POWERPC] Add Freescale PCI VENDOR ID and 8641 device IDs Kumar Gala @ 2007-07-23 21:30 ` Scott Wood 1 sibling, 0 replies; 39+ messages in thread From: Scott Wood @ 2007-07-23 21:30 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev Kumar Gala wrote: > + pci_bridge@1c { The OF PCI specification recommends "pci" here rather than "pci_bridge". In any case, we should prefer dashes to underscores in device trees. -Scott ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 21/25] [POWERPC] 85xxCDS: Delay 8259 cascade hookup. 2007-07-23 20:50 ` [PATCH 21/25] [POWERPC] 85xxCDS: Delay 8259 cascade hookup Kumar Gala 2007-07-23 20:50 ` [PATCH 22/25] [POWERPC] 85xxCDS: Misc 8548 PCI Corrections Kumar Gala @ 2007-07-24 11:52 ` Paul Mackerras 2007-07-24 15:34 ` Kumar Gala 1 sibling, 1 reply; 39+ messages in thread From: Paul Mackerras @ 2007-07-24 11:52 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev Kumar Gala writes: > From: Randy Vinson <rvinson@mvista.com> > +device_initcall(mpc85xx_cds_8259_attach); I don't see any platform test in mpc85xx_cds_8259_attach to make sure it only does its stuff on suitable platforms. Looks like it needs one. Paul. ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 21/25] [POWERPC] 85xxCDS: Delay 8259 cascade hookup. 2007-07-24 11:52 ` [PATCH 21/25] [POWERPC] 85xxCDS: Delay 8259 cascade hookup Paul Mackerras @ 2007-07-24 15:34 ` Kumar Gala 0 siblings, 0 replies; 39+ messages in thread From: Kumar Gala @ 2007-07-24 15:34 UTC (permalink / raw) To: Paul Mackerras; +Cc: linuxppc-dev On Jul 24, 2007, at 6:52 AM, Paul Mackerras wrote: > Kumar Gala writes: > >> From: Randy Vinson <rvinson@mvista.com> > >> +device_initcall(mpc85xx_cds_8259_attach); > > I don't see any platform test in mpc85xx_cds_8259_attach to make sure > it only does its stuff on suitable platforms. Looks like it needs > one. I've added a is_machine(mpc85xx_cds) into the patch in my tree to handle this. - k ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 19/25] [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line. 2007-07-23 20:50 ` [PATCH 19/25] [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line Kumar Gala 2007-07-23 20:50 ` [PATCH 20/25] [POWERPC] 85xxCDS: Make sure restart resets the PCI bus Kumar Gala @ 2007-07-24 1:48 ` Benjamin Herrenschmidt 2007-07-24 2:47 ` Kumar Gala 1 sibling, 1 reply; 39+ messages in thread From: Benjamin Herrenschmidt @ 2007-07-24 1:48 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev On Mon, 2007-07-23 at 15:50 -0500, Kumar Gala wrote: > --- a/arch/powerpc/sysdev/mpic.c > +++ b/arch/powerpc/sysdev/mpic.c > @@ -836,6 +836,7 @@ static struct irq_chip mpic_irq_chip = { > .mask = mpic_mask_irq, > .unmask = mpic_unmask_irq, > .eoi = mpic_end_irq, > + .end = mpic_unmask_irq, > .set_type = mpic_set_irq_type, > }; Nope, that doesn't look correct and shouldn't be in this patch in the first place. end() is flow control business, not chip business, so it's really something that needs to be fixed in the fasteoi handler for -rt I suppose. Ben. ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 19/25] [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line. 2007-07-24 1:48 ` [PATCH 19/25] [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line Benjamin Herrenschmidt @ 2007-07-24 2:47 ` Kumar Gala 2007-07-24 3:41 ` Kumar Gala 0 siblings, 1 reply; 39+ messages in thread From: Kumar Gala @ 2007-07-24 2:47 UTC (permalink / raw) To: Benjamin Herrenschmidt; +Cc: linuxppc-dev On Jul 23, 2007, at 8:48 PM, Benjamin Herrenschmidt wrote: > On Mon, 2007-07-23 at 15:50 -0500, Kumar Gala wrote: >> --- a/arch/powerpc/sysdev/mpic.c >> +++ b/arch/powerpc/sysdev/mpic.c >> @@ -836,6 +836,7 @@ static struct irq_chip mpic_irq_chip = { >> .mask = mpic_mask_irq, >> .unmask = mpic_unmask_irq, >> .eoi = mpic_end_irq, >> + .end = mpic_unmask_irq, >> .set_type = mpic_set_irq_type, >> }; > > Nope, that doesn't look correct and shouldn't be in this patch in the > first place. > > end() is flow control business, not chip business, so it's really > something that needs to be fixed in the fasteoi handler for -rt I > suppose. Ok, I dropped this one for now. - k ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 19/25] [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line. 2007-07-24 2:47 ` Kumar Gala @ 2007-07-24 3:41 ` Kumar Gala 0 siblings, 0 replies; 39+ messages in thread From: Kumar Gala @ 2007-07-24 3:41 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev On Jul 23, 2007, at 9:47 PM, Kumar Gala wrote: > > On Jul 23, 2007, at 8:48 PM, Benjamin Herrenschmidt wrote: > >> On Mon, 2007-07-23 at 15:50 -0500, Kumar Gala wrote: >>> --- a/arch/powerpc/sysdev/mpic.c >>> +++ b/arch/powerpc/sysdev/mpic.c >>> @@ -836,6 +836,7 @@ static struct irq_chip mpic_irq_chip = { >>> .mask = mpic_mask_irq, >>> .unmask = mpic_unmask_irq, >>> .eoi = mpic_end_irq, >>> + .end = mpic_unmask_irq, >>> .set_type = mpic_set_irq_type, >>> }; >> >> Nope, that doesn't look correct and shouldn't be in this patch in the >> first place. >> >> end() is flow control business, not chip business, so it's really >> something that needs to be fixed in the fasteoi handler for -rt I >> suppose. > > Ok, I dropped this one for now. Just dropped the mpic.c change. - k ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 16/25] [POWERPC] Provide ability to setup P2P bridge registers from struct resource 2007-07-23 20:50 ` [PATCH 16/25] [POWERPC] Provide ability to setup P2P bridge registers from struct resource Kumar Gala 2007-07-23 20:50 ` [PATCH 17/25] [POWERPC] Make sure virtual P2P bridge registers are setup on PCIe PHB Kumar Gala @ 2007-07-24 1:45 ` Benjamin Herrenschmidt 1 sibling, 0 replies; 39+ messages in thread From: Benjamin Herrenschmidt @ 2007-07-24 1:45 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev On Mon, 2007-07-23 at 15:50 -0500, Kumar Gala wrote: > We need the ability to set P2P bridge registers to properly setup the virtual > P2P bridges that exist in PCIe controllers for some of the embedded setups. > > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> > --- > arch/powerpc/kernel/pci_32.c | 18 ++++++++++++------ > include/asm-powerpc/pci-bridge.h | 2 ++ > 2 files changed, 14 insertions(+), 6 deletions(-) > > diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c > index bfcfa14..721a694 100644 > --- a/arch/powerpc/kernel/pci_32.c > +++ b/arch/powerpc/kernel/pci_32.c > @@ -415,15 +415,13 @@ probe_resource(struct pci_bus *parent, struct resource *pr, > return 0; > } > > -static void __init > -update_bridge_base(struct pci_bus *bus, int i) > +void __init > +update_bridge_resource(struct pci_dev *dev, struct resource *res) > { > - struct resource *res = bus->resource[i]; > u8 io_base_lo, io_limit_lo; > u16 mem_base, mem_limit; > u16 cmd; > unsigned long start, end, off; > - struct pci_dev *dev = bus->self; > struct pci_controller *hose = dev->sysdata; > > if (!hose) { > @@ -467,12 +465,20 @@ update_bridge_base(struct pci_bus *bus, int i) > pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit); > > } else { > - DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n", > - pci_name(dev), i, res->flags); > + DBG(KERN_ERR "PCI: ugh, bridge %s res has flags=%lx\n", > + pci_name(dev), res->flags); > } > pci_write_config_word(dev, PCI_COMMAND, cmd); > } > > +static void __init > +update_bridge_base(struct pci_bus *bus, int i) > +{ > + struct resource *res = bus->resource[i]; > + struct pci_dev *dev = bus->self; > + update_bridge_resource(dev, res); > +} > + > static inline void alloc_resource(struct pci_dev *dev, int idx) > { > struct resource *pr, *r = &dev->resource[idx]; > diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h > index 435bfe8..b7d2ea4 100644 > --- a/include/asm-powerpc/pci-bridge.h > +++ b/include/asm-powerpc/pci-bridge.h > @@ -93,6 +93,8 @@ extern int early_find_capability(struct pci_controller *hose, int bus, > extern void setup_indirect_pci(struct pci_controller* hose, > u32 cfg_addr, u32 cfg_data, u32 flags); > extern void setup_grackle(struct pci_controller *hose); > +extern void __init update_bridge_resource(struct pci_dev *dev, > + struct resource *res); > > #else > ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 14/25] [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime 2007-07-23 20:50 ` [PATCH 14/25] [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime Kumar Gala 2007-07-23 20:50 ` [PATCH 15/25] [POWERPC] Add basic PCI/PCI Express support for 8544DS board Kumar Gala @ 2007-07-24 1:43 ` Benjamin Herrenschmidt 2007-07-24 2:30 ` Kumar Gala 1 sibling, 1 reply; 39+ messages in thread From: Benjamin Herrenschmidt @ 2007-07-24 1:43 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev On Mon, 2007-07-23 at 15:50 -0500, Kumar Gala wrote: > Make it so we do a runtime check to know if we need to write cfg_addr > as big or little endian. This is needed if we want to allow 86xx support > to co-exist in the same kernel as other 6xx PPCs. > > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Nack on that one. Don't add this function pointer. Just have the indirect read/write routines test the flag and do the right endian, possibly with an inline or a macro if you want to be clean. A function ointer is probably slower anyway and I don't want to add more cruft to struct pci_controller. Cheers, Ben > --- > arch/powerpc/Kconfig | 5 ----- > arch/powerpc/platforms/82xx/mpc82xx_ads.c | 3 ++- > arch/powerpc/platforms/83xx/pci.c | 4 ++-- > arch/powerpc/platforms/85xx/Kconfig | 1 - > arch/powerpc/platforms/86xx/Kconfig | 1 - > arch/powerpc/platforms/chrp/pci.c | 7 ++++--- > arch/powerpc/platforms/embedded6xx/linkstation.c | 2 +- > arch/powerpc/sysdev/fsl_pci.c | 3 ++- > arch/powerpc/sysdev/grackle.c | 2 +- > arch/powerpc/sysdev/indirect_pci.c | 20 +++++++++++++++++--- > arch/powerpc/sysdev/mv64x60_pci.c | 2 +- > include/asm-powerpc/pci-bridge.h | 6 +++++- > 12 files changed, 35 insertions(+), 21 deletions(-) > > diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig > index 3ff90f0..00099ef 100644 > --- a/arch/powerpc/Kconfig > +++ b/arch/powerpc/Kconfig > @@ -411,11 +411,6 @@ config PPC_INDIRECT_PCI > default y if 40x || 44x > default n > > -config PPC_INDIRECT_PCI_BE > - bool > - depends PPC_INDIRECT_PCI > - default n > - > config EISA > bool > > diff --git a/arch/powerpc/platforms/82xx/mpc82xx_ads.c b/arch/powerpc/platforms/82xx/mpc82xx_ads.c > index da20832..2d1b05b 100644 > --- a/arch/powerpc/platforms/82xx/mpc82xx_ads.c > +++ b/arch/powerpc/platforms/82xx/mpc82xx_ads.c > @@ -553,7 +553,8 @@ static void __init mpc82xx_add_bridge(struct device_node *np) > > setup_indirect_pci(hose, > r.start + offsetof(pci_cpm2_t, pci_cfg_addr), > - r.start + offsetof(pci_cpm2_t, pci_cfg_data)); > + r.start + offsetof(pci_cpm2_t, pci_cfg_data), > + 0); > > pci_process_bridge_OF_ranges(hose, np, 1); > } > diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/platforms/83xx/pci.c > index c0e2b89..9206946 100644 > --- a/arch/powerpc/platforms/83xx/pci.c > +++ b/arch/powerpc/platforms/83xx/pci.c > @@ -74,11 +74,11 @@ int __init mpc83xx_add_bridge(struct device_node *dev) > */ > /* PCI 1 */ > if ((rsrc.start & 0xfffff) == 0x8500) { > - setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304); > + setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304, 0); > } > /* PCI 2 */ > if ((rsrc.start & 0xfffff) == 0x8600) { > - setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384); > + setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384, 0); > primary = 0; > } > > diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig > index 526ddde..4661fcc 100644 > --- a/arch/powerpc/platforms/85xx/Kconfig > +++ b/arch/powerpc/platforms/85xx/Kconfig > @@ -51,7 +51,6 @@ config MPC85xx > bool > select PPC_UDBG_16550 > select PPC_INDIRECT_PCI if PCI > - select PPC_INDIRECT_PCI_BE if PCI > select MPIC > select FSL_PCI if PCI > select SERIAL_8250_SHARE_IRQ if SERIAL_8250 > diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig > index d1c8115..343b76d 100644 > --- a/arch/powerpc/platforms/86xx/Kconfig > +++ b/arch/powerpc/platforms/86xx/Kconfig > @@ -14,7 +14,6 @@ endchoice > > config MPC8641 > bool > - select PPC_INDIRECT_PCI_BE if PCI > select FSL_PCI if PCI > select PPC_UDBG_16550 > select MPIC > diff --git a/arch/powerpc/platforms/chrp/pci.c b/arch/powerpc/platforms/chrp/pci.c > index 3690624..28d1647 100644 > --- a/arch/powerpc/platforms/chrp/pci.c > +++ b/arch/powerpc/platforms/chrp/pci.c > @@ -181,7 +181,7 @@ setup_python(struct pci_controller *hose, struct device_node *dev) > } > iounmap(reg); > > - setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010); > + setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010, 0); > } > > /* Marvell Discovery II based Pegasos 2 */ > @@ -277,13 +277,14 @@ chrp_find_bridges(void) > hose->cfg_data = p; > gg2_pci_config_base = p; > } else if (is_pegasos == 1) { > - setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc); > + setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc, 0); > } else if (is_pegasos == 2) { > setup_peg2(hose, dev); > } else if (!strncmp(model, "IBM,CPC710", 10)) { > setup_indirect_pci(hose, > r.start + 0x000f8000, > - r.start + 0x000f8010); > + r.start + 0x000f8010, > + 0); > if (index == 0) { > dma = of_get_property(dev, "system-dma-base", > &len); > diff --git a/arch/powerpc/platforms/embedded6xx/linkstation.c b/arch/powerpc/platforms/embedded6xx/linkstation.c > index f4d0a7a..bd5ca58 100644 > --- a/arch/powerpc/platforms/embedded6xx/linkstation.c > +++ b/arch/powerpc/platforms/embedded6xx/linkstation.c > @@ -73,7 +73,7 @@ static int __init linkstation_add_bridge(struct device_node *dev) > return -ENOMEM; > hose->first_busno = bus_range ? bus_range[0] : 0; > hose->last_busno = bus_range ? bus_range[1] : 0xff; > - setup_indirect_pci(hose, 0xfec00000, 0xfee00000); > + setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); > > /* Interpret the "ranges" property */ > /* This also maps the I/O region and sets isa_io/mem_base */ > diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c > index c6a30f9..1426642 100644 > --- a/arch/powerpc/sysdev/fsl_pci.c > +++ b/arch/powerpc/sysdev/fsl_pci.c > @@ -185,7 +185,8 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) > hose->first_busno = bus_range ? bus_range[0] : 0x0; > hose->last_busno = bus_range ? bus_range[1] : 0xff; > > - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); > + setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, > + INDIRECT_PCI_BIG_ENDIAN); > setup_pci_cmd(hose); > > /* check PCI express link status */ > diff --git a/arch/powerpc/sysdev/grackle.c b/arch/powerpc/sysdev/grackle.c > index 4205362..11ad562 100644 > --- a/arch/powerpc/sysdev/grackle.c > +++ b/arch/powerpc/sysdev/grackle.c > @@ -55,7 +55,7 @@ static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable) > > void __init setup_grackle(struct pci_controller *hose) > { > - setup_indirect_pci(hose, 0xfec00000, 0xfee00000); > + setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); > if (machine_is_compatible("PowerMac1,1")) > pci_assign_all_buses = 1; > if (machine_is_compatible("AAPL,PowerBook1998")) > diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c > index ad341f5..33b9b69 100644 > --- a/arch/powerpc/sysdev/indirect_pci.c > +++ b/arch/powerpc/sysdev/indirect_pci.c > @@ -26,6 +26,16 @@ > #define PCI_CFG_OUT out_le32 > #endif > > +static void pci_cfg_out_le(volatile u32 __iomem *addr, u32 val) > +{ > + out_le32(addr, val); > +} > + > +static void pci_cfg_out_be(volatile u32 __iomem *addr, u32 val) > +{ > + out_be32(addr, val); > +} > + > static int > indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, > int len, u32 *val) > @@ -58,7 +68,7 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, > else > reg = offset & 0xfc; > > - PCI_CFG_OUT(hose->cfg_addr, > + hose->pci_cfg_out(hose->cfg_addr, > (0x80000000 | (bus_no << 16) > | (devfn << 8) | reg | cfg_type)); > > @@ -113,7 +123,7 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, > else > reg = offset & 0xfc; > > - PCI_CFG_OUT(hose->cfg_addr, > + hose->pci_cfg_out(hose->cfg_addr, > (0x80000000 | (bus_no << 16) > | (devfn << 8) | reg | cfg_type)); > > @@ -149,7 +159,7 @@ static struct pci_ops indirect_pci_ops = > }; > > void __init > -setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) > +setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data, u32 flags) > { > unsigned long base = cfg_addr & PAGE_MASK; > void __iomem *mbase; > @@ -160,4 +170,8 @@ setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) > mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE); > hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK); > hose->ops = &indirect_pci_ops; > + if (flags & INDIRECT_PCI_BIG_ENDIAN) > + hose->pci_cfg_out = pci_cfg_out_be; > + else > + hose->pci_cfg_out = pci_cfg_out_le; > } > diff --git a/arch/powerpc/sysdev/mv64x60_pci.c b/arch/powerpc/sysdev/mv64x60_pci.c > index 45db86c..9b3baa7 100644 > --- a/arch/powerpc/sysdev/mv64x60_pci.c > +++ b/arch/powerpc/sysdev/mv64x60_pci.c > @@ -144,7 +144,7 @@ static int __init mv64x60_add_bridge(struct device_node *dev) > hose->first_busno = bus_range ? bus_range[0] : 0; > hose->last_busno = bus_range ? bus_range[1] : 0xff; > > - setup_indirect_pci(hose, rsrc.start, rsrc.start + 4); > + setup_indirect_pci(hose, rsrc.start, rsrc.start + 4, 0); > hose->self_busno = hose->first_busno; > > printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. " > diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h > index 13cb0a9..435bfe8 100644 > --- a/include/asm-powerpc/pci-bridge.h > +++ b/include/asm-powerpc/pci-bridge.h > @@ -36,6 +36,7 @@ struct pci_controller { > struct pci_ops *ops; > volatile unsigned int __iomem *cfg_addr; > volatile void __iomem *cfg_data; > + void (*pci_cfg_out)(volatile u32 __iomem *cfg_addr, u32 val); > > /* > * Used for variants of PCI indirect handling and possible quirks: > @@ -87,8 +88,10 @@ int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, > extern int early_find_capability(struct pci_controller *hose, int bus, > int dev_fn, int cap); > > +/* Set this for a big-endian cfg_addr */ > +#define INDIRECT_PCI_BIG_ENDIAN 0x00000001 > extern void setup_indirect_pci(struct pci_controller* hose, > - u32 cfg_addr, u32 cfg_data); > + u32 cfg_addr, u32 cfg_data, u32 flags); > extern void setup_grackle(struct pci_controller *hose); > > #else > @@ -128,6 +131,7 @@ struct pci_controller { > struct pci_ops *ops; > volatile unsigned int __iomem *cfg_addr; > volatile void __iomem *cfg_data; > + void (*pci_cfg_out)(volatile u32 __iomem *cfg_addr, u32 val); > > /* Currently, we limit ourselves to 1 IO range and 3 mem > * ranges since the common pci_bus structure can't handle more ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 14/25] [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime 2007-07-24 1:43 ` [PATCH 14/25] [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime Benjamin Herrenschmidt @ 2007-07-24 2:30 ` Kumar Gala 0 siblings, 0 replies; 39+ messages in thread From: Kumar Gala @ 2007-07-24 2:30 UTC (permalink / raw) To: Benjamin Herrenschmidt; +Cc: linuxppc-dev On Tue, 24 Jul 2007, Benjamin Herrenschmidt wrote: > On Mon, 2007-07-23 at 15:50 -0500, Kumar Gala wrote: > > Make it so we do a runtime check to know if we need to write cfg_addr > > as big or little endian. This is needed if we want to allow 86xx support > > to co-exist in the same kernel as other 6xx PPCs. > > > > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > > Nack on that one. Don't add this function pointer. Just have the > indirect read/write routines test the flag and do the right endian, > possibly with an inline or a macro if you want to be clean. A function > ointer is probably slower anyway and I don't want to add more cruft to > struct pci_controller. > How about this version? --- arch/powerpc/Kconfig | 5 ---- arch/powerpc/platforms/82xx/mpc82xx_ads.c | 3 +- arch/powerpc/platforms/83xx/pci.c | 4 +- arch/powerpc/platforms/85xx/Kconfig | 1 - arch/powerpc/platforms/86xx/Kconfig | 1 - arch/powerpc/platforms/chrp/pci.c | 7 +++-- arch/powerpc/platforms/embedded6xx/linkstation.c | 2 +- arch/powerpc/sysdev/fsl_pci.c | 3 +- arch/powerpc/sysdev/grackle.c | 2 +- arch/powerpc/sysdev/indirect_pci.c | 26 +++++++++++----------- arch/powerpc/sysdev/mv64x60_pci.c | 2 +- include/asm-powerpc/pci-bridge.h | 5 +++- 12 files changed, 30 insertions(+), 31 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 3ff90f0..00099ef 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -411,11 +411,6 @@ config PPC_INDIRECT_PCI default y if 40x || 44x default n -config PPC_INDIRECT_PCI_BE - bool - depends PPC_INDIRECT_PCI - default n - config EISA bool diff --git a/arch/powerpc/platforms/82xx/mpc82xx_ads.c b/arch/powerpc/platforms/82xx/mpc82xx_ads.c index da20832..2d1b05b 100644 --- a/arch/powerpc/platforms/82xx/mpc82xx_ads.c +++ b/arch/powerpc/platforms/82xx/mpc82xx_ads.c @@ -553,7 +553,8 @@ static void __init mpc82xx_add_bridge(struct device_node *np) setup_indirect_pci(hose, r.start + offsetof(pci_cpm2_t, pci_cfg_addr), - r.start + offsetof(pci_cpm2_t, pci_cfg_data)); + r.start + offsetof(pci_cpm2_t, pci_cfg_data), + 0); pci_process_bridge_OF_ranges(hose, np, 1); } diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/platforms/83xx/pci.c index c0e2b89..9206946 100644 --- a/arch/powerpc/platforms/83xx/pci.c +++ b/arch/powerpc/platforms/83xx/pci.c @@ -74,11 +74,11 @@ int __init mpc83xx_add_bridge(struct device_node *dev) */ /* PCI 1 */ if ((rsrc.start & 0xfffff) == 0x8500) { - setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304); + setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304, 0); } /* PCI 2 */ if ((rsrc.start & 0xfffff) == 0x8600) { - setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384); + setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384, 0); primary = 0; } diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 526ddde..4661fcc 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -51,7 +51,6 @@ config MPC85xx bool select PPC_UDBG_16550 select PPC_INDIRECT_PCI if PCI - select PPC_INDIRECT_PCI_BE if PCI select MPIC select FSL_PCI if PCI select SERIAL_8250_SHARE_IRQ if SERIAL_8250 diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig index d1c8115..343b76d 100644 --- a/arch/powerpc/platforms/86xx/Kconfig +++ b/arch/powerpc/platforms/86xx/Kconfig @@ -14,7 +14,6 @@ endchoice config MPC8641 bool - select PPC_INDIRECT_PCI_BE if PCI select FSL_PCI if PCI select PPC_UDBG_16550 select MPIC diff --git a/arch/powerpc/platforms/chrp/pci.c b/arch/powerpc/platforms/chrp/pci.c index 3690624..28d1647 100644 --- a/arch/powerpc/platforms/chrp/pci.c +++ b/arch/powerpc/platforms/chrp/pci.c @@ -181,7 +181,7 @@ setup_python(struct pci_controller *hose, struct device_node *dev) } iounmap(reg); - setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010); + setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010, 0); } /* Marvell Discovery II based Pegasos 2 */ @@ -277,13 +277,14 @@ chrp_find_bridges(void) hose->cfg_data = p; gg2_pci_config_base = p; } else if (is_pegasos == 1) { - setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc); + setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc, 0); } else if (is_pegasos == 2) { setup_peg2(hose, dev); } else if (!strncmp(model, "IBM,CPC710", 10)) { setup_indirect_pci(hose, r.start + 0x000f8000, - r.start + 0x000f8010); + r.start + 0x000f8010, + 0); if (index == 0) { dma = of_get_property(dev, "system-dma-base", &len); diff --git a/arch/powerpc/platforms/embedded6xx/linkstation.c b/arch/powerpc/platforms/embedded6xx/linkstation.c index f4d0a7a..bd5ca58 100644 --- a/arch/powerpc/platforms/embedded6xx/linkstation.c +++ b/arch/powerpc/platforms/embedded6xx/linkstation.c @@ -73,7 +73,7 @@ static int __init linkstation_add_bridge(struct device_node *dev) return -ENOMEM; hose->first_busno = bus_range ? bus_range[0] : 0; hose->last_busno = bus_range ? bus_range[1] : 0xff; - setup_indirect_pci(hose, 0xfec00000, 0xfee00000); + setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); /* Interpret the "ranges" property */ /* This also maps the I/O region and sets isa_io/mem_base */ diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index c6a30f9..d7747e0 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -185,7 +185,8 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) hose->first_busno = bus_range ? bus_range[0] : 0x0; hose->last_busno = bus_range ? bus_range[1] : 0xff; - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); + setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, + PPC_INDIRECT_TYPE_BIG_ENDIAN); setup_pci_cmd(hose); /* check PCI express link status */ diff --git a/arch/powerpc/sysdev/grackle.c b/arch/powerpc/sysdev/grackle.c index 4205362..11ad562 100644 --- a/arch/powerpc/sysdev/grackle.c +++ b/arch/powerpc/sysdev/grackle.c @@ -55,7 +55,7 @@ static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable) void __init setup_grackle(struct pci_controller *hose) { - setup_indirect_pci(hose, 0xfec00000, 0xfee00000); + setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); if (machine_is_compatible("PowerMac1,1")) pci_assign_all_buses = 1; if (machine_is_compatible("AAPL,PowerBook1998")) diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c index ad341f5..a8ac2df 100644 --- a/arch/powerpc/sysdev/indirect_pci.c +++ b/arch/powerpc/sysdev/indirect_pci.c @@ -20,12 +20,6 @@ #include <asm/pci-bridge.h> #include <asm/machdep.h> -#ifdef CONFIG_PPC_INDIRECT_PCI_BE -#define PCI_CFG_OUT out_be32 -#else -#define PCI_CFG_OUT out_le32 -#endif - static int indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) @@ -58,9 +52,12 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, else reg = offset & 0xfc; - PCI_CFG_OUT(hose->cfg_addr, - (0x80000000 | (bus_no << 16) - | (devfn << 8) | reg | cfg_type)); + if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN) + out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | + (devfn << 8) | reg | cfg_type)); + else + out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | + (devfn << 8) | reg | cfg_type)); /* * Note: the caller has already checked that offset is @@ -113,9 +110,12 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, else reg = offset & 0xfc; - PCI_CFG_OUT(hose->cfg_addr, - (0x80000000 | (bus_no << 16) - | (devfn << 8) | reg | cfg_type)); + if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN) + out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | + (devfn << 8) | reg | cfg_type)); + else + out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | + (devfn << 8) | reg | cfg_type)); /* surpress setting of PCI_PRIMARY_BUS */ if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS) @@ -149,7 +149,7 @@ static struct pci_ops indirect_pci_ops = }; void __init -setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) +setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data, u32 flags) { unsigned long base = cfg_addr & PAGE_MASK; void __iomem *mbase; diff --git a/arch/powerpc/sysdev/mv64x60_pci.c b/arch/powerpc/sysdev/mv64x60_pci.c index 45db86c..9b3baa7 100644 --- a/arch/powerpc/sysdev/mv64x60_pci.c +++ b/arch/powerpc/sysdev/mv64x60_pci.c @@ -144,7 +144,7 @@ static int __init mv64x60_add_bridge(struct device_node *dev) hose->first_busno = bus_range ? bus_range[0] : 0; hose->last_busno = bus_range ? bus_range[1] : 0xff; - setup_indirect_pci(hose, rsrc.start, rsrc.start + 4); + setup_indirect_pci(hose, rsrc.start, rsrc.start + 4, 0); hose->self_busno = hose->first_busno; printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. " diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h index 13cb0a9..d7d3bf0 100644 --- a/include/asm-powerpc/pci-bridge.h +++ b/include/asm-powerpc/pci-bridge.h @@ -49,11 +49,13 @@ struct pci_controller { * hanging if we don't have link and try to do config cycles to * anything but the PHB. Only allow talking to the PHB if this is * set. + * BIG_ENDIAN - cfg_addr is a big endian register */ #define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001) #define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004) #define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008) +#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010) u32 indirect_type; /* Currently, we limit ourselves to 1 IO range and 3 mem @@ -88,7 +90,7 @@ extern int early_find_capability(struct pci_controller *hose, int bus, int dev_fn, int cap); extern void setup_indirect_pci(struct pci_controller* hose, - u32 cfg_addr, u32 cfg_data); + u32 cfg_addr, u32 cfg_data, u32 flags); extern void setup_grackle(struct pci_controller *hose); #else @@ -128,6 +130,7 @@ struct pci_controller { struct pci_ops *ops; volatile unsigned int __iomem *cfg_addr; volatile void __iomem *cfg_data; + void (*pci_cfg_out)(volatile u32 __iomem *cfg_addr, u32 val); /* Currently, we limit ourselves to 1 IO range and 3 mem * ranges since the common pci_bus structure can't handle more -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 13/25] [POWERPC] Removed setup_indirect_pci_nomap 2007-07-23 20:50 ` [PATCH 13/25] [POWERPC] Removed setup_indirect_pci_nomap Kumar Gala 2007-07-23 20:50 ` [PATCH 14/25] [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime Kumar Gala @ 2007-07-24 1:40 ` Benjamin Herrenschmidt 1 sibling, 0 replies; 39+ messages in thread From: Benjamin Herrenschmidt @ 2007-07-24 1:40 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev On Mon, 2007-07-23 at 15:50 -0500, Kumar Gala wrote: > We don't use setup_indirect_pci_nomap in arch/powerpc and it appears > the users that needed it from arch/ppc are now using setup_indirect_pci. > > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Good riddance ! Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> > --- > arch/powerpc/sysdev/indirect_pci.c | 17 ++++------------- > include/asm-powerpc/pci-bridge.h | 2 -- > 2 files changed, 4 insertions(+), 15 deletions(-) > > diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c > index bc5b4e2..ad341f5 100644 > --- a/arch/powerpc/sysdev/indirect_pci.c > +++ b/arch/powerpc/sysdev/indirect_pci.c > @@ -149,24 +149,15 @@ static struct pci_ops indirect_pci_ops = > }; > > void __init > -setup_indirect_pci_nomap(struct pci_controller* hose, void __iomem * cfg_addr, > - void __iomem * cfg_data) > -{ > - hose->cfg_addr = cfg_addr; > - hose->cfg_data = cfg_data; > - hose->ops = &indirect_pci_ops; > -} > - > -void __init > setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) > { > unsigned long base = cfg_addr & PAGE_MASK; > - void __iomem *mbase, *addr, *data; > + void __iomem *mbase; > > mbase = ioremap(base, PAGE_SIZE); > - addr = mbase + (cfg_addr & ~PAGE_MASK); > + hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK); > if ((cfg_data & PAGE_MASK) != base) > mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE); > - data = mbase + (cfg_data & ~PAGE_MASK); > - setup_indirect_pci_nomap(hose, addr, data); > + hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK); > + hose->ops = &indirect_pci_ops; > } > diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h > index 9754357..13cb0a9 100644 > --- a/include/asm-powerpc/pci-bridge.h > +++ b/include/asm-powerpc/pci-bridge.h > @@ -87,8 +87,6 @@ int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, > extern int early_find_capability(struct pci_controller *hose, int bus, > int dev_fn, int cap); > > -extern void setup_indirect_pci_nomap(struct pci_controller* hose, > - void __iomem *cfg_addr, void __iomem *cfg_data); > extern void setup_indirect_pci(struct pci_controller* hose, > u32 cfg_addr, u32 cfg_data); > extern void setup_grackle(struct pci_controller *hose); ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 04/25] [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link 2007-07-23 20:49 ` [PATCH 04/25] [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link Kumar Gala 2007-07-23 20:49 ` [PATCH 05/25] [POWERPC] FSL: Cleanup how we detect if we are a PCIe controller Kumar Gala @ 2007-07-24 1:39 ` Benjamin Herrenschmidt 2007-07-24 2:28 ` Kumar Gala 1 sibling, 1 reply; 39+ messages in thread From: Benjamin Herrenschmidt @ 2007-07-24 1:39 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev On Mon, 2007-07-23 at 15:49 -0500, Kumar Gala wrote: > Added PPC_INDIRECT_TYPE_NO_PCIE_LINK flag to the indirect pci handling > code to ensure that we don't talk to any device other than the PHB > if we don't have PCIe link. Some controllers will lockup if they try > to do a config cycle to any device on the bus except the PHB. > > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> I would name the quirk a bit more generically, something like "ACCESS_PHB_ONLY" maybe ? If you don't want to change it, that's fair. Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Ben. > arch/powerpc/sysdev/indirect_pci.c | 16 +++++++++++++++- > include/asm-powerpc/pci-bridge.h | 5 +++++ > 2 files changed, 20 insertions(+), 1 deletions(-) > > diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c > index c7e6e85..bc5b4e2 100644 > --- a/arch/powerpc/sysdev/indirect_pci.c > +++ b/arch/powerpc/sysdev/indirect_pci.c > @@ -35,10 +35,17 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, > u8 cfg_type = 0; > u32 bus_no, reg; > > + if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) { > + if (bus->number != hose->first_busno) > + return PCIBIOS_DEVICE_NOT_FOUND; > + if (devfn != 0) > + return PCIBIOS_DEVICE_NOT_FOUND; > + } > + > if (ppc_md.pci_exclude_device) > if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) > return PCIBIOS_DEVICE_NOT_FOUND; > - > + > if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE) > if (bus->number != hose->first_busno) > cfg_type = 1; > @@ -83,6 +90,13 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, > u8 cfg_type = 0; > u32 bus_no, reg; > > + if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) { > + if (bus->number != hose->first_busno) > + return PCIBIOS_DEVICE_NOT_FOUND; > + if (devfn != 0) > + return PCIBIOS_DEVICE_NOT_FOUND; > + } > + > if (ppc_md.pci_exclude_device) > if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) > return PCIBIOS_DEVICE_NOT_FOUND; > diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h > index 7a00b8e..9754357 100644 > --- a/include/asm-powerpc/pci-bridge.h > +++ b/include/asm-powerpc/pci-bridge.h > @@ -45,10 +45,15 @@ struct pci_controller { > * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS > * to determine which bus number to match on when generating type0 > * config cycles > + * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with > + * hanging if we don't have link and try to do config cycles to > + * anything but the PHB. Only allow talking to the PHB if this is > + * set. > */ > #define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001) > #define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) > #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004) > +#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008) > u32 indirect_type; > > /* Currently, we limit ourselves to 1 IO range and 3 mem ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 04/25] [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link 2007-07-24 1:39 ` [PATCH 04/25] [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link Benjamin Herrenschmidt @ 2007-07-24 2:28 ` Kumar Gala 0 siblings, 0 replies; 39+ messages in thread From: Kumar Gala @ 2007-07-24 2:28 UTC (permalink / raw) To: Benjamin Herrenschmidt; +Cc: linuxppc-dev On Jul 23, 2007, at 8:39 PM, Benjamin Herrenschmidt wrote: > On Mon, 2007-07-23 at 15:49 -0500, Kumar Gala wrote: >> Added PPC_INDIRECT_TYPE_NO_PCIE_LINK flag to the indirect pci >> handling >> code to ensure that we don't talk to any device other than the PHB >> if we don't have PCIe link. Some controllers will lockup if they try >> to do a config cycle to any device on the bus except the PHB. >> >> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > > I would name the quirk a bit more generically, something like > "ACCESS_PHB_ONLY" maybe ? If you don't want to change it, that's fair. Will deal with this change after the current patchset. > > Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> > > Ben. - k ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 03/25] [POWERPC] Add the ability to find PCI capabilities early on 2007-07-23 20:49 ` [PATCH 03/25] [POWERPC] Add the ability to find PCI capabilities early on Kumar Gala 2007-07-23 20:49 ` [PATCH 04/25] [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link Kumar Gala @ 2007-07-24 1:37 ` Benjamin Herrenschmidt 1 sibling, 0 replies; 39+ messages in thread From: Benjamin Herrenschmidt @ 2007-07-24 1:37 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev On Mon, 2007-07-23 at 15:49 -0500, Kumar Gala wrote: > Added early_find_capability that wraps pci_bus_find_capability and uses > fake_pci_bus() to allow us to call it before we've fully setup the > pci_controller. > > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> --- I want to try to get rid of the early stuff at one point, but that will not happen before some major rework of powerpc PCI code so for now, that's good to go. Ben. > --- > arch/powerpc/kernel/pci_32.c | 7 +++++++ > include/asm-powerpc/pci-bridge.h | 3 +++ > 2 files changed, 10 insertions(+), 0 deletions(-) > > diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c > index 0adf077..bfcfa14 100644 > --- a/arch/powerpc/kernel/pci_32.c > +++ b/arch/powerpc/kernel/pci_32.c > @@ -1468,3 +1468,10 @@ EARLY_PCI_OP(read, dword, u32 *) > EARLY_PCI_OP(write, byte, u8) > EARLY_PCI_OP(write, word, u16) > EARLY_PCI_OP(write, dword, u32) > + > +extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); > +int early_find_capability(struct pci_controller *hose, int bus, int devfn, > + int cap) > +{ > + return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); > +} > diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h > index e72c2a6..7a00b8e 100644 > --- a/include/asm-powerpc/pci-bridge.h > +++ b/include/asm-powerpc/pci-bridge.h > @@ -79,6 +79,9 @@ int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, > int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, > int where, u32 val); > > +extern int early_find_capability(struct pci_controller *hose, int bus, > + int dev_fn, int cap); > + > extern void setup_indirect_pci_nomap(struct pci_controller* hose, > void __iomem *cfg_addr, void __iomem *cfg_data); > extern void setup_indirect_pci(struct pci_controller* hose, ^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2007-07-24 15:33 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2007-07-23 20:49 [PATCH 00/25] Freescale PCI/PCIe support/fixup/cleanup Kumar Gala
2007-07-23 20:49 ` [PATCH 01/25] [POWERPC] Create common fsl pci/e files based on 86xx platforms Kumar Gala
2007-07-23 20:49 ` [PATCH 02/25] [POWERPC] Rewrite Freescale PCI/PCIe support for 8{3, 5, 6}xx Kumar Gala
2007-07-23 20:49 ` [PATCH 03/25] [POWERPC] Add the ability to find PCI capabilities early on Kumar Gala
2007-07-23 20:49 ` [PATCH 04/25] [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link Kumar Gala
2007-07-23 20:49 ` [PATCH 05/25] [POWERPC] FSL: Cleanup how we detect if we are a PCIe controller Kumar Gala
2007-07-23 20:49 ` [PATCH 06/25] [POWERPC] Add 8548 CDS PCI express controller node and PCI-X device node Kumar Gala
2007-07-23 20:49 ` [PATCH 07/25] [POWERPC] Update PCI nodes in the 83xx/85xx boards device tree Kumar Gala
2007-07-23 20:49 ` [PATCH 08/25] [POWERPC] Use Freescale pci/pcie common code for 85xx boards Kumar Gala
2007-07-23 20:49 ` [PATCH 09/25] [POWERPC] Add basic PCI node for mpc8568mds board Kumar Gala
2007-07-23 20:49 ` [PATCH 10/25] [POWERPC] Fixup resources on pci_bus for PCIe PHB when no device is connected Kumar Gala
2007-07-23 20:49 ` [PATCH 11/25] [POWERPC] 85xx: Added 8568 PCIe support Kumar Gala
2007-07-23 20:49 ` [PATCH 12/25] [POWERPC] 85xx: Add quirk to ignore bogus FPGA on CDS Kumar Gala
2007-07-23 20:50 ` [PATCH 13/25] [POWERPC] Removed setup_indirect_pci_nomap Kumar Gala
2007-07-23 20:50 ` [PATCH 14/25] [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime Kumar Gala
2007-07-23 20:50 ` [PATCH 15/25] [POWERPC] Add basic PCI/PCI Express support for 8544DS board Kumar Gala
2007-07-23 20:50 ` [PATCH 16/25] [POWERPC] Provide ability to setup P2P bridge registers from struct resource Kumar Gala
2007-07-23 20:50 ` [PATCH 17/25] [POWERPC] Make sure virtual P2P bridge registers are setup on PCIe PHB Kumar Gala
2007-07-23 20:50 ` [PATCH 18/25] [POWERPC] FSL: Add support for PCI-X controllers Kumar Gala
2007-07-23 20:50 ` [PATCH 19/25] [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line Kumar Gala
2007-07-23 20:50 ` [PATCH 20/25] [POWERPC] 85xxCDS: Make sure restart resets the PCI bus Kumar Gala
2007-07-23 20:50 ` [PATCH 21/25] [POWERPC] 85xxCDS: Delay 8259 cascade hookup Kumar Gala
2007-07-23 20:50 ` [PATCH 22/25] [POWERPC] 85xxCDS: Misc 8548 PCI Corrections Kumar Gala
2007-07-23 20:50 ` [PATCH 23/25] [POWERPC] 85xxCDS: MPC8548 DTS cleanup Kumar Gala
2007-07-23 20:50 ` [PATCH 24/25] [POWERPC] Add Freescale PCI VENDOR ID and 8641 device IDs Kumar Gala
2007-07-23 20:50 ` [PATCH 25/25] [POWERPC] 85xx: Added needed MPC85xx PCI " Kumar Gala
2007-07-23 21:30 ` [PATCH 23/25] [POWERPC] 85xxCDS: MPC8548 DTS cleanup Scott Wood
2007-07-24 11:52 ` [PATCH 21/25] [POWERPC] 85xxCDS: Delay 8259 cascade hookup Paul Mackerras
2007-07-24 15:34 ` Kumar Gala
2007-07-24 1:48 ` [PATCH 19/25] [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line Benjamin Herrenschmidt
2007-07-24 2:47 ` Kumar Gala
2007-07-24 3:41 ` Kumar Gala
2007-07-24 1:45 ` [PATCH 16/25] [POWERPC] Provide ability to setup P2P bridge registers from struct resource Benjamin Herrenschmidt
2007-07-24 1:43 ` [PATCH 14/25] [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime Benjamin Herrenschmidt
2007-07-24 2:30 ` Kumar Gala
2007-07-24 1:40 ` [PATCH 13/25] [POWERPC] Removed setup_indirect_pci_nomap Benjamin Herrenschmidt
2007-07-24 1:39 ` [PATCH 04/25] [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link Benjamin Herrenschmidt
2007-07-24 2:28 ` Kumar Gala
2007-07-24 1:37 ` [PATCH 03/25] [POWERPC] Add the ability to find PCI capabilities early on Benjamin Herrenschmidt
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