From: Kumar Gala <galak@kernel.crashing.org>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
linuxppc-dev@ozlabs.org
Subject: [PATCH 23/25] [POWERPC] 85xxCDS: MPC8548 DTS cleanup.
Date: Mon, 23 Jul 2007 15:50:10 -0500 [thread overview]
Message-ID: <11852238472931-git-send-email-galak@kernel.crashing.org> (raw)
In-Reply-To: <11852238452609-git-send-email-galak@kernel.crashing.org>
From: Randy Vinson <rvinson@mvista.com>
Added the P2P bridge present on the Arcadia base board and moved the VIA
Southbridge behind the bridge to reflect its actual position in the bus
organization. Added the RTC that's in the VIA Southbridge and expanded
the ranges array for the SOC node to allow proper address translation of
the RTC registers.
Signed-off-by: Randy Vinson <rvinson@mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/boot/dts/mpc8548cds.dts | 124 ++++++++++++++++++++++++----------
1 files changed, 89 insertions(+), 35 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 4770a5b..d215d21 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -44,8 +44,14 @@
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
- ranges = <0 e0000000 00100000>;
- reg = <e0000000 00100000>; // CCSRBAR 1M
+ ranges = <00001000 e0001000 000ff000
+ 80000000 80000000 10000000
+ e2000000 e2000000 00800000
+ 90000000 90000000 10000000
+ e2800000 e2800000 00800000
+ a0000000 a0000000 20000000
+ e3000000 e3000000 01000000>;
+ reg = <e0000000 00001000>; // CCSRBAR
bus-frequency = <0>;
memory-controller@2000 {
@@ -162,8 +168,8 @@
serial@4500 {
device_type = "serial";
compatible = "ns16550";
- reg = <4500 100>; // reg base, size
- clock-frequency = <0>; // should we fill in in uboot?
+ reg = <4500 100>; // reg base, size
+ clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>;
interrupt-parent = <&mpic>;
};
@@ -172,7 +178,7 @@
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>; // reg base, size
- clock-frequency = <0>; // should we fill in in uboot?
+ clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>;
interrupt-parent = <&mpic>;
};
@@ -183,8 +189,8 @@
fsl,has-rstcr;
};
- pci1: pci@8000 {
- interrupt-map-mask = <1f800 0 0 7>;
+ pci@8000 {
+ interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x4 (PCIX Slot 2) */
02000 0 0 1 &mpic 0 1
@@ -244,19 +250,7 @@
0E000 0 0 1 &mpic 0 1
0E000 0 0 2 &mpic 1 1
0E000 0 0 3 &mpic 2 1
- 0E000 0 0 4 &mpic 3 1
-
- /* bus 1 , idsel 0x2 Tsi310 bridge secondary */
- 11000 0 0 1 &mpic 2 1
- 11000 0 0 2 &mpic 3 1
- 11000 0 0 3 &mpic 0 1
- 11000 0 0 4 &mpic 1 1
-
- /* VIA chip */
- 12000 0 0 1 &mpic 0 1
- 12000 0 0 2 &mpic 1 1
- 12000 0 0 3 &mpic 2 1
- 12000 0 0 4 &mpic 3 1>;
+ 0E000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
@@ -271,18 +265,78 @@
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
- i8259@4 {
- clock-frequency = <0>;
- interrupt-controller;
- device_type = "interrupt-controller";
- reg = <12000 0 0 0 1>;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- built-in;
- compatible = "chrp,iic";
- big-endian;
- interrupts = <1>;
- interrupt-parent = <&pci1>;
+ pci_bridge@1c {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x00 (PrPMC Site) */
+ 0000 0 0 1 &mpic 0 1
+ 0000 0 0 2 &mpic 1 1
+ 0000 0 0 3 &mpic 2 1
+ 0000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x04 (VIA chip) */
+ 2000 0 0 1 &mpic 0 1
+ 2000 0 0 2 &mpic 1 1
+ 2000 0 0 3 &mpic 2 1
+ 2000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x05 (8139) */
+ 2800 0 0 1 &mpic 1 1
+
+ /* IDSEL 0x06 (Slot 6) */
+ 3000 0 0 1 &mpic 2 1
+ 3000 0 0 2 &mpic 3 1
+ 3000 0 0 3 &mpic 0 1
+ 3000 0 0 4 &mpic 1 1
+
+ /* IDESL 0x07 (Slot 7) */
+ 3800 0 0 1 &mpic 3 1
+ 3800 0 0 2 &mpic 0 1
+ 3800 0 0 3 &mpic 1 1
+ 3800 0 0 4 &mpic 2 1>;
+
+ reg = <e000 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ ranges = <02000000 0 80000000
+ 02000000 0 80000000
+ 0 20000000
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00080000>;
+ clock-frequency = <1fca055>;
+
+ isa@4 {
+ device_type = "isa";
+ #interrupt-cells = <2>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ reg = <2000 0 0 0 0>;
+ ranges = <1 0 01000000 0 0 00001000>;
+ interrupt-parent = <&i8259>;
+
+ i8259: interrupt-controller@20 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ reg = <1 20 2
+ 1 a0 2
+ 1 4d0 2>;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ built-in;
+ compatible = "chrp,iic";
+ interrupts = <0 1>;
+ interrupt-parent = <&mpic>;
+ };
+
+ rtc@70 {
+ compatible = "pnpPNP,b00";
+ reg = <1 70 2>;
+ };
+ };
};
};
@@ -292,9 +346,9 @@
/* IDSEL 0x15 */
a800 0 0 1 &mpic b 1
- a800 0 0 2 &mpic b 1
- a800 0 0 3 &mpic b 1
- a800 0 0 4 &mpic b 1>;
+ a800 0 0 2 &mpic 1 1
+ a800 0 0 3 &mpic 2 1
+ a800 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
--
1.5.2.2
next prev parent reply other threads:[~2007-07-23 20:51 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-07-23 20:49 [PATCH 00/25] Freescale PCI/PCIe support/fixup/cleanup Kumar Gala
2007-07-23 20:49 ` [PATCH 01/25] [POWERPC] Create common fsl pci/e files based on 86xx platforms Kumar Gala
2007-07-23 20:49 ` [PATCH 02/25] [POWERPC] Rewrite Freescale PCI/PCIe support for 8{3, 5, 6}xx Kumar Gala
2007-07-23 20:49 ` [PATCH 03/25] [POWERPC] Add the ability to find PCI capabilities early on Kumar Gala
2007-07-23 20:49 ` [PATCH 04/25] [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link Kumar Gala
2007-07-23 20:49 ` [PATCH 05/25] [POWERPC] FSL: Cleanup how we detect if we are a PCIe controller Kumar Gala
2007-07-23 20:49 ` [PATCH 06/25] [POWERPC] Add 8548 CDS PCI express controller node and PCI-X device node Kumar Gala
2007-07-23 20:49 ` [PATCH 07/25] [POWERPC] Update PCI nodes in the 83xx/85xx boards device tree Kumar Gala
2007-07-23 20:49 ` [PATCH 08/25] [POWERPC] Use Freescale pci/pcie common code for 85xx boards Kumar Gala
2007-07-23 20:49 ` [PATCH 09/25] [POWERPC] Add basic PCI node for mpc8568mds board Kumar Gala
2007-07-23 20:49 ` [PATCH 10/25] [POWERPC] Fixup resources on pci_bus for PCIe PHB when no device is connected Kumar Gala
2007-07-23 20:49 ` [PATCH 11/25] [POWERPC] 85xx: Added 8568 PCIe support Kumar Gala
2007-07-23 20:49 ` [PATCH 12/25] [POWERPC] 85xx: Add quirk to ignore bogus FPGA on CDS Kumar Gala
2007-07-23 20:50 ` [PATCH 13/25] [POWERPC] Removed setup_indirect_pci_nomap Kumar Gala
2007-07-23 20:50 ` [PATCH 14/25] [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime Kumar Gala
2007-07-23 20:50 ` [PATCH 15/25] [POWERPC] Add basic PCI/PCI Express support for 8544DS board Kumar Gala
2007-07-23 20:50 ` [PATCH 16/25] [POWERPC] Provide ability to setup P2P bridge registers from struct resource Kumar Gala
2007-07-23 20:50 ` [PATCH 17/25] [POWERPC] Make sure virtual P2P bridge registers are setup on PCIe PHB Kumar Gala
2007-07-23 20:50 ` [PATCH 18/25] [POWERPC] FSL: Add support for PCI-X controllers Kumar Gala
2007-07-23 20:50 ` [PATCH 19/25] [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line Kumar Gala
2007-07-23 20:50 ` [PATCH 20/25] [POWERPC] 85xxCDS: Make sure restart resets the PCI bus Kumar Gala
2007-07-23 20:50 ` [PATCH 21/25] [POWERPC] 85xxCDS: Delay 8259 cascade hookup Kumar Gala
2007-07-23 20:50 ` [PATCH 22/25] [POWERPC] 85xxCDS: Misc 8548 PCI Corrections Kumar Gala
2007-07-23 20:50 ` Kumar Gala [this message]
2007-07-23 20:50 ` [PATCH 24/25] [POWERPC] Add Freescale PCI VENDOR ID and 8641 device IDs Kumar Gala
2007-07-23 20:50 ` [PATCH 25/25] [POWERPC] 85xx: Added needed MPC85xx PCI " Kumar Gala
2007-07-23 21:30 ` [PATCH 23/25] [POWERPC] 85xxCDS: MPC8548 DTS cleanup Scott Wood
2007-07-24 11:52 ` [PATCH 21/25] [POWERPC] 85xxCDS: Delay 8259 cascade hookup Paul Mackerras
2007-07-24 15:34 ` Kumar Gala
2007-07-24 1:48 ` [PATCH 19/25] [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line Benjamin Herrenschmidt
2007-07-24 2:47 ` Kumar Gala
2007-07-24 3:41 ` Kumar Gala
2007-07-24 1:45 ` [PATCH 16/25] [POWERPC] Provide ability to setup P2P bridge registers from struct resource Benjamin Herrenschmidt
2007-07-24 1:43 ` [PATCH 14/25] [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime Benjamin Herrenschmidt
2007-07-24 2:30 ` Kumar Gala
2007-07-24 1:40 ` [PATCH 13/25] [POWERPC] Removed setup_indirect_pci_nomap Benjamin Herrenschmidt
2007-07-24 1:39 ` [PATCH 04/25] [POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link Benjamin Herrenschmidt
2007-07-24 2:28 ` Kumar Gala
2007-07-24 1:37 ` [PATCH 03/25] [POWERPC] Add the ability to find PCI capabilities early on Benjamin Herrenschmidt
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