From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id BB73ADDEC2 for ; Tue, 4 Dec 2007 08:04:23 +1100 (EST) Subject: Re: [PATCH] Add IPIC MSI interrupt support From: Benjamin Herrenschmidt To: Li Li In-Reply-To: <1196672870.14353.21.camel@Guyver> References: <1196394519.29683.8.camel@Guyver> <1196654521.13554.32.camel@concordia> <1196672870.14353.21.camel@Guyver> Content-Type: text/plain Date: Tue, 04 Dec 2007 08:03:32 +1100 Message-Id: <1196715812.13230.234.camel@pasglop> Mime-Version: 1.0 Cc: linuxppc-dev , Gala Kumar , Li Tony Reply-To: benh@kernel.crashing.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Mon, 2007-12-03 at 17:07 +0800, Li Li wrote: > > In IPIC, the 8 MSI interrupts is handled as level intrrupt. > I just provide a versatile in case it is changed. Level ? Are you sure ? MSIs are by definition edge interrupts... Or do you have some weird logic that asserts a level input until you go ack something ? Sounds weird... Ben.