[PATCH 0/4] PowerPC: more Sequoia/Rainier updates for 2.6.25

[PATCH 0/4] PowerPC: more Sequoia/Rainier updates for 2.6.25

[Valentine Barshak]

This patch series has a couple of PowerPC 440EPx/GRx fixes and
adds PCI to Sequoia/Rainier DTS.

Thanks,
Valentine.

[PATCH 1/4] PowerPC: Correct 440GRx machine_check callback

[Valentine Barshak]

Correct the PowerPC 440GRx machine check callback.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
 arch/powerpc/kernel/cputable.c |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)

diff -pruN linux-2.6.orig/arch/powerpc/kernel/cputable.c linux-2.6/arch/powerpc/kernel/cputable.c
--- linux-2.6.orig/arch/powerpc/kernel/cputable.c	2007-12-21 17:14:17.000000000 +0300
+++ linux-2.6/arch/powerpc/kernel/cputable.c	2007-12-21 18:05:08.000000000 +0300
@@ -1247,7 +1247,7 @@ static struct cpu_spec __initdata cpu_sp
 		.icache_bsize		= 32,
 		.dcache_bsize		= 32,
 		.cpu_setup		= __setup_cpu_440grx,
-		.machine_check		= machine_check_4xx,
+		.machine_check		= machine_check_440A,
 		.platform		= "ppc440",
 	},
 	{ /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */

[PATCH 2/4] PowerPC: update 440EP(x)/440GR(x) identical PVR issue workaround

[Valentine Barshak]

Commit 3ee133269861dc449ad5be761aa8570b1b05571f introduced
a CPU "model" property and thus broke PowerPC 440EP(x)/440GR(x)
identical PVR workaround. The patch updates it to use the new
model property for CPU identification.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
 arch/powerpc/kernel/prom.c |   37 +++++++++++++++++++++++++------------
 1 files changed, 25 insertions(+), 12 deletions(-)

diff -pruN linux-2.6.orig/arch/powerpc/kernel/prom.c linux-2.6/arch/powerpc/kernel/prom.c
--- linux-2.6.orig/arch/powerpc/kernel/prom.c	2007-12-21 17:14:17.000000000 +0300
+++ linux-2.6/arch/powerpc/kernel/prom.c	2007-12-21 18:42:09.000000000 +0300
@@ -614,6 +614,29 @@ static struct feature_property {
 #endif /* CONFIG_PPC64 */
 };
 
+#if defined(CONFIG_44x) && defined(CONFIG_PPC_FPU)
+static inline void identical_pvr_fixup(unsigned long node)
+{
+	unsigned int pvr;
+	char *model = of_get_flat_dt_prop(node, "model", NULL);
+
+	/*
+	 * Since 440GR(x)/440EP(x) processors have the same pvr,
+	 * we check the node path and set bit 28 in the cur_cpu_spec
+	 * pvr for EP(x) processor version. This bit is always 0 in
+	 * the "real" pvr. Then we call identify_cpu again with
+	 * the new logical pvr to enable FPU support.
+	 */
+	if (model && strstr(model, "440EP")) {
+		pvr = cur_cpu_spec->pvr_value | 0x8;
+		identify_cpu(0, pvr);
+		DBG("Using logical pvr %x for %s\n", pvr, model);
+	}
+}
+#else
+#define identical_pvr_fixup(node) do { } while(0)
+#endif
+
 static void __init check_cpu_feature_properties(unsigned long node)
 {
 	unsigned long i;
@@ -711,18 +734,8 @@ static int __init early_init_dt_scan_cpu
 		prop = of_get_flat_dt_prop(node, "cpu-version", NULL);
 		if (prop && (*prop & 0xff000000) == 0x0f000000)
 			identify_cpu(0, *prop);
-#if defined(CONFIG_44x) && defined(CONFIG_PPC_FPU)
-		/*
-		 * Since 440GR(x)/440EP(x) processors have the same pvr,
-		 * we check the node path and set bit 28 in the cur_cpu_spec
-		 * pvr for EP(x) processor version. This bit is always 0 in
-		 * the "real" pvr. Then we call identify_cpu again with
-		 * the new logical pvr to enable FPU support.
-		 */
-		if (strstr(uname, "440EP")) {
-			identify_cpu(0, cur_cpu_spec->pvr_value | 0x8);
-		}
-#endif
+
+		identical_pvr_fixup(node);
 	}
 
 	check_cpu_feature_properties(node);

[PATCH 3/4] PowerPC: Add PCI entry to 440EPx Sequoia DTS.

[Valentine Barshak]

This adds PCI entry to PowerPC 440EPx Sequoia DTS.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
 arch/powerpc/boot/dts/sequoia.dts |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+)

--- linux-2.6.orig/arch/powerpc/boot/dts/sequoia.dts	2007-12-21 17:14:17.000000000 +0300
+++ linux-2.6/arch/powerpc/boot/dts/sequoia.dts	2007-12-21 17:18:32.000000000 +0300
@@ -324,6 +324,33 @@
 				has-new-stacr-staopc;
 			};
 		};
+
+		PCI0: pci@1ec000000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb440epx-pci", "ibm,plb-pci";
+			primary;
+			reg = <1 eec00000 8	/* Config space access */
+			       1 eed00000 4	/* IACK */
+			       1 eed00000 4	/* Special cycle */
+			       1 ef400000 40>;	/* Internal registers */
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed. Chip supports a second
+			 * IO range but we don't use it for now
+			 */
+			ranges = <02000000 0 80000000 1 80000000 0 10000000
+				01000000 0 00000000 1 e8000000 0 00100000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+			/* All PCI interrupts are routed to IRQ 67 */
+			interrupt-map-mask = <0000 0 0 0>;
+			interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
+		};
 	};
 
 	chosen {

[PATCH 4/4] PowerPC: Add PCI node to 440GRx Rainier DTS.

[Valentine Barshak]

This adds PCI entry to PowerPC 440GRx Rainier DTS.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
 arch/powerpc/boot/dts/rainier.dts |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+)

--- linux-2.6.orig/arch/powerpc/boot/dts/rainier.dts	2007-12-19 16:00:01.000000000 +0300
+++ linux-2.6/arch/powerpc/boot/dts/rainier.dts	2007-12-20 21:59:42.000000000 +0300
@@ -317,6 +317,33 @@
 				has-new-stacr-staopc;
 			};
 		};
+
+		PCI0: pci@1ec000000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb440grx-pci", "ibm,plb-pci";
+			primary;
+			reg = <1 eec00000 8	/* Config space access */
+			       1 eed80000 4	/* IACK */
+			       1 eed80000 4	/* Special cycle */
+			       1 ef400000 40>;	/* Internal registers */
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed. Chip supports a second
+			 * IO range but we don't use it for now
+			 */
+			ranges = <02000000 0 80000000 1 80000000 0 10000000
+				01000000 0 00000000 1 e8000000 0 00100000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+			/* All PCI interrupts are routed to IRQ 67 */
+			interrupt-map-mask = <0000 0 0 0>;
+			interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
+		};
 	};
 
 	chosen {

Re: [PATCH 2/4] PowerPC: update 440EP(x)/440GR(x) identical PVR issue workaround

[Josh Boyer]

On Fri, 21 Dec 2007 19:24:02 +0300
Valentine Barshak <vbarshak@ru.mvista.com> wrote:

> Commit 3ee133269861dc449ad5be761aa8570b1b05571f introduced
> a CPU "model" property and thus broke PowerPC 440EP(x)/440GR(x)
> identical PVR workaround. The patch updates it to use the new
> model property for CPU identification.

Good catch.  I'll have to look more closely to see if anything else
would be broken by changing the cpu node name from "PowerPC,xxxx@0" to
"cpu@0".

josh

Re: [PATCH 4/4] PowerPC: Add PCI node to 440GRx Rainier DTS.

[Valentine Barshak]

> +			reg = <1 eec00000 8	/* Config space access */
> +			       1 eed80000 4	/* IACK */
> +			       1 eed80000 4	/* Special cycle */

Please, discard this one, since it contains the typos pasted from 
previous bamboo dts, which have been fixed :).

I'll send the corrected patch right away.
Thanks,
Valentine.

[PATCH 4/4] PowerPC: Add PCI entry to 440GRx Rainier DTS.

[Valentine Barshak]

This adds PCI entry to PowerPC 440GRx Rainier DTS.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
 arch/powerpc/boot/dts/rainier.dts |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+)

--- linux-2.6.orig/arch/powerpc/boot/dts/rainier.dts	2007-12-19 16:00:01.000000000 +0300
+++ linux-2.6/arch/powerpc/boot/dts/rainier.dts	2007-12-20 21:59:42.000000000 +0300
@@ -317,6 +317,33 @@
 				has-new-stacr-staopc;
 			};
 		};
+
+		PCI0: pci@1ec000000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb440grx-pci", "ibm,plb-pci";
+			primary;
+			reg = <1 eec00000 8	/* Config space access */
+			       1 eed00000 4	/* IACK */
+			       1 eed00000 4	/* Special cycle */
+			       1 ef400000 40>;	/* Internal registers */
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed. Chip supports a second
+			 * IO range but we don't use it for now
+			 */
+			ranges = <02000000 0 80000000 1 80000000 0 10000000
+				01000000 0 00000000 1 e8000000 0 00100000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+			/* All PCI interrupts are routed to IRQ 67 */
+			interrupt-map-mask = <0000 0 0 0>;
+			interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
+		};
 	};
 
 	chosen {

Re: [PATCH 2/4] PowerPC: update 440EP(x)/440GR(x) identical PVR issue workaround

[Valentine Barshak]

Josh Boyer wrote:
> On Fri, 21 Dec 2007 19:24:02 +0300
> Valentine Barshak <vbarshak@ru.mvista.com> wrote:
> 
>> Commit 3ee133269861dc449ad5be761aa8570b1b05571f introduced
>> a CPU "model" property and thus broke PowerPC 440EP(x)/440GR(x)
>> identical PVR workaround. The patch updates it to use the new
>> model property for CPU identification.
> 
> Good catch.  I'll have to look more closely to see if anything else
> would be broken by changing the cpu node name from "PowerPC,xxxx@0" to
> "cpu@0".
> 
> josh

Looks like we need a u-boot update for 405Ex Kilauea board.
Mine (U-Boot 1.3.0-rc3-gccc2fe86-dirty (Oct 25 2007 - 12:18:41))
fails to boot with new cpu node changes:

    Uncompressing Kernel Image ... OK
    Booting using the fdt at 0x400000
le to update property /cpus/PowerPC,405EX@0:timebase-frequency, 
err=FDT_ERR_NOTFOUND
Unable to update property /cpus/PowerPC,405EX@0:clock-frequency, 
err=FDT_ERR_NOTFOUND

Thanks,
Valentine.

Re: [PATCH 2/4] PowerPC: update 440EP(x)/440GR(x) identical PVR issue workaround

[Stefan Roese]

Hi Valentine,

On Friday 21 December 2007, Valentine Barshak wrote:
> > Good catch.  I'll have to look more closely to see if anything else
> > would be broken by changing the cpu node name from "PowerPC,xxxx@0" to
> > "cpu@0".
> >
> > josh
>
> Looks like we need a u-boot update for 405Ex Kilauea board.
> Mine (U-Boot 1.3.0-rc3-gccc2fe86-dirty (Oct 25 2007 - 12:18:41))
> fails to boot with new cpu node changes:
>
>     Uncompressing Kernel Image ... OK
>     Booting using the fdt at 0x400000
> le to update property /cpus/PowerPC,405EX@0:timebase-frequency,
> err=FDT_ERR_NOTFOUND
> Unable to update property /cpus/PowerPC,405EX@0:clock-frequency,
> err=FDT_ERR_NOTFOUND

Already done. :) Please take a look at the current implementation in the 
for-1.3.2 branch of the u-boot-ppc4xx custodian repo:

http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot/u-boot-ppc4xx.git;a=shortlog;h=for-1.3.2

This works for both cpu node names.

Best regards,
Stefan

Re: [PATCH 3/4] PowerPC: Add PCI entry to 440EPx Sequoia DTS.

[Benjamin Herrenschmidt]

On Fri, 2007-12-21 at 19:26 +0300, Valentine Barshak wrote:
> +
> +                       /* All PCI interrupts are routed to IRQ 67 */
> +                       interrupt-map-mask = <0000 0 0 0>;
> +                       interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
> +               };
>         };

Wow, all 4 lines of all slots ?

Ben.

Re: [PATCH 4/4] PowerPC: Add PCI node to 440GRx Rainier DTS.

[Benjamin Herrenschmidt]

On Fri, 2007-12-21 at 19:27 +0300, Valentine Barshak wrote:
> +                       /* All PCI interrupts are routed to IRQ 67 */
> +                       interrupt-map-mask = <0000 0 0 0>;
> +                       interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
> +               };

Same question as for Sequoia...

Ben.

Re: [PATCH 3/4] PowerPC: Add PCI entry to 440EPx Sequoia DTS.

[Stefan Roese]

On Friday 21 December 2007, Benjamin Herrenschmidt wrote:
> On Fri, 2007-12-21 at 19:26 +0300, Valentine Barshak wrote:
> > +
> > +                       /* All PCI interrupts are routed to IRQ 67 */
> > +                       interrupt-map-mask = <0000 0 0 0>;
> > +                       interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
> > +               };
> >         };
>
> Wow, all 4 lines of all slots ?

Yes, that's unfortunately correct. :-(

Best regards,
Stefan

Re: [PATCH 4/4] PowerPC: Add PCI node to 440GRx Rainier DTS.

[Stefan Roese]

On Friday 21 December 2007, Benjamin Herrenschmidt wrote:
> On Fri, 2007-12-21 at 19:27 +0300, Valentine Barshak wrote:
> > +                       /* All PCI interrupts are routed to IRQ 67 */
> > +                       interrupt-map-mask = <0000 0 0 0>;
> > +                       interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
> > +               };
>
> Same question as for Sequoia...

Correct here too. Rainier (440GRx) is basically a stripped of version of the 
Sequioa (440EPx).

Berst regards,
Stefan

Re: [PATCH 4/4] PowerPC: Add PCI node to 440GRx Rainier DTS.

[Benjamin Herrenschmidt]

On Sat, 2007-12-22 at 06:54 +0100, Stefan Roese wrote:
> On Friday 21 December 2007, Benjamin Herrenschmidt wrote:
> > On Fri, 2007-12-21 at 19:27 +0300, Valentine Barshak wrote:
> > > +                       /* All PCI interrupts are routed to IRQ 67 */
> > > +                       interrupt-map-mask = <0000 0 0 0>;
> > > +                       interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
> > > +               };
> >
> > Same question as for Sequoia...
> 
> Correct here too. Rainier (440GRx) is basically a stripped of version of the 
> Sequioa (440EPx).

I hope they accompany it with a design note: "don't do that in your
actual products" :-)

Ben.

Re: [PATCH 2/4] PowerPC: update 440EP(x)/440GR(x) identical PVR issue workaround

[Valentine Barshak]

Stefan Roese wrote:
> Hi Valentine,
> 
> On Friday 21 December 2007, Valentine Barshak wrote:
>>> Good catch.  I'll have to look more closely to see if anything else
>>> would be broken by changing the cpu node name from "PowerPC,xxxx@0" to
>>> "cpu@0".
>>>
>>> josh
>> Looks like we need a u-boot update for 405Ex Kilauea board.
>> Mine (U-Boot 1.3.0-rc3-gccc2fe86-dirty (Oct 25 2007 - 12:18:41))
>> fails to boot with new cpu node changes:
>>
>>     Uncompressing Kernel Image ... OK
>>     Booting using the fdt at 0x400000
>> le to update property /cpus/PowerPC,405EX@0:timebase-frequency,
>> err=FDT_ERR_NOTFOUND
>> Unable to update property /cpus/PowerPC,405EX@0:clock-frequency,
>> err=FDT_ERR_NOTFOUND
> 
> Already done. :) Please take a look at the current implementation in the 
> for-1.3.2 branch of the u-boot-ppc4xx custodian repo:
> 
> http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot/u-boot-ppc4xx.git;a=shortlog;h=for-1.3.2
> 
> This works for both cpu node names.

Great, thanks :)
Valentine.

> 
> Best regards,
> Stefan

Re: [PATCH 3/4] PowerPC: Add PCI entry to 440EPx Sequoia DTS.

[Sergei Shtylyov]

Valentine Barshak wrote:

> This adds PCI entry to PowerPC 440EPx Sequoia DTS.

> Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>

> --- linux-2.6.orig/arch/powerpc/boot/dts/sequoia.dts	2007-12-21 17:14:17.000000000 +0300
> +++ linux-2.6/arch/powerpc/boot/dts/sequoia.dts	2007-12-21 17:18:32.000000000 +0300
> @@ -324,6 +324,33 @@
>  				has-new-stacr-staopc;
>  			};
>  		};
> +
> +		PCI0: pci@1ec000000 {
> +			device_type = "pci";
> +			#interrupt-cells = <1>;
> +			#size-cells = <2>;
> +			#address-cells = <3>;
> +			compatible = "ibm,plb440epx-pci", "ibm,plb-pci";
> +			primary;
> +			reg = <1 eec00000 8	/* Config space access */
> +			       1 eed00000 4	/* IACK */
> +			       1 eed00000 4	/* Special cycle */
> +			       1 ef400000 40>;	/* Internal registers */
> +
> +			/* Outbound ranges, one memory and one IO,
> +			 * later cannot be changed. Chip supports a second
> +			 * IO range but we don't use it for now
> +			 */
> +			ranges = <02000000 0 80000000 1 80000000 0 10000000

    I wonder why the AMCC's Sequoia/Rainier manual has PCI memory mapped at 
0x80000000-0xbfffffff? The 0x80000000-0x8fffffff mapping was assumed by 
arch/ppc/ code.  What/why changed here?
    As we now both know, having PCI memory space mapped beyound 4 GB makes 
some drivers misbehave as they use 'unsigned long' to store the result of 
pci_resource_start() and later ioremap() this truncated value -- which is 
64-bit on Sequoia due to CONFIG_RESOURCE_64BIT=y that is needed to store the 
beyond-4GB addresses.

> +				01000000 0 00000000 1 e8000000 0 00100000>;
> +
> +			/* Inbound 2GB range starting at 0 */
> +			dma-ranges = <42000000 0 0 0 0 0 80000000>;
> +
> +			/* All PCI interrupts are routed to IRQ 67 */
> +			interrupt-map-mask = <0000 0 0 0>;
> +			interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
> +		};
>  	};

WBR, Sergei

Re: [PATCH 3/4] PowerPC: Add PCI entry to 440EPx Sequoia DTS.

[Valentine Barshak]

Sergei Shtylyov wrote:
> Valentine Barshak wrote:
> 
>> This adds PCI entry to PowerPC 440EPx Sequoia DTS.
> 
>> Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
> 
>> --- linux-2.6.orig/arch/powerpc/boot/dts/sequoia.dts    2007-12-21 
>> 17:14:17.000000000 +0300
>> +++ linux-2.6/arch/powerpc/boot/dts/sequoia.dts    2007-12-21 
>> 17:18:32.000000000 +0300
>> @@ -324,6 +324,33 @@
>>                  has-new-stacr-staopc;
>>              };
>>          };
>> +
>> +        PCI0: pci@1ec000000 {
>> +            device_type = "pci";
>> +            #interrupt-cells = <1>;
>> +            #size-cells = <2>;
>> +            #address-cells = <3>;
>> +            compatible = "ibm,plb440epx-pci", "ibm,plb-pci";
>> +            primary;
>> +            reg = <1 eec00000 8    /* Config space access */
>> +                   1 eed00000 4    /* IACK */
>> +                   1 eed00000 4    /* Special cycle */
>> +                   1 ef400000 40>;    /* Internal registers */
>> +
>> +            /* Outbound ranges, one memory and one IO,
>> +             * later cannot be changed. Chip supports a second
>> +             * IO range but we don't use it for now
>> +             */
>> +            ranges = <02000000 0 80000000 1 80000000 0 10000000
> 
>    I wonder why the AMCC's Sequoia/Rainier manual has PCI memory mapped 
> at 0x80000000-0xbfffffff? The 0x80000000-0x8fffffff mapping was assumed 
> by arch/ppc/ code.  What/why changed here?

The addresses in the manual are relative to bus base. PCI controller is 
located on the PLB and PLB base address is 0x100000000ULL on Sequoia.
Older PPC code has ioremap64 function that did the 64 to 32-bit trick
It's been abolished. The kernel has support for 64-bit physical 
addresses on 32-bit. IMHO there's no big reason to keep doing that 
address trick. However, there are some drivers that use unsigned long 
for storing physical addresses. This is wrong, since 
pci_resource_start() returns a resource_size_t value. I think it's these 
drivers that have to be fixed instead of adding workarounds to ppc4xx code.
Thanks,
Valentine.

>    As we now both know, having PCI memory space mapped beyound 4 GB 
> makes some drivers misbehave as they use 'unsigned long' to store the 
> result of pci_resource_start() and later ioremap() this truncated value 
> -- which is 64-bit on Sequoia due to CONFIG_RESOURCE_64BIT=y that is 
> needed to store the beyond-4GB addresses.
> 
>> +                01000000 0 00000000 1 e8000000 0 00100000>;
>> +
>> +            /* Inbound 2GB range starting at 0 */
>> +            dma-ranges = <42000000 0 0 0 0 0 80000000>;
>> +
>> +            /* All PCI interrupts are routed to IRQ 67 */
>> +            interrupt-map-mask = <0000 0 0 0>;
>> +            interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
>> +        };
>>      };
> 
> WBR, Sergei

Re: [PATCH 3/4] PowerPC: Add PCI entry to 440EPx Sequoia DTS.

[Sergei Shtylyov]

Hello.

Valentine Barshak wrote:

>>> --- linux-2.6.orig/arch/powerpc/boot/dts/sequoia.dts    2007-12-21 
>>> 17:14:17.000000000 +0300
>>> +++ linux-2.6/arch/powerpc/boot/dts/sequoia.dts    2007-12-21 
>>> 17:18:32.000000000 +0300
>>> @@ -324,6 +324,33 @@
>>>                  has-new-stacr-staopc;
>>>              };
>>>          };
>>> +
>>> +        PCI0: pci@1ec000000 {
>>> +            device_type = "pci";
>>> +            #interrupt-cells = <1>;
>>> +            #size-cells = <2>;
>>> +            #address-cells = <3>;
>>> +            compatible = "ibm,plb440epx-pci", "ibm,plb-pci";
>>> +            primary;
>>> +            reg = <1 eec00000 8    /* Config space access */
>>> +                   1 eed00000 4    /* IACK */
>>> +                   1 eed00000 4    /* Special cycle */
>>> +                   1 ef400000 40>;    /* Internal registers */
>>> +
>>> +            /* Outbound ranges, one memory and one IO,
>>> +             * later cannot be changed. Chip supports a second
>>> +             * IO range but we don't use it for now
>>> +             */
>>> +            ranges = <02000000 0 80000000 1 80000000 0 10000000

>>    I wonder why the AMCC's Sequoia/Rainier manual has PCI memory 
>> mapped at 0x80000000-0xbfffffff? The 0x80000000-0x8fffffff mapping was 
>> assumed by arch/ppc/ code.  What/why changed here?

> The addresses in the manual are relative to bus base.

    Hm, that's hard to infer from the manual, and even from arch/ppc/ sources...

> PCI controller is 
> located on the PLB and PLB base address is 0x100000000ULL on Sequoia.

     The question is where cam one read about that. :-)

> Older PPC code has ioremap64 function that did the 64 to 32-bit trick

    Ah, seeing fixup_bigphys_addr() at last -- it has escaped me before...

> It's been abolished. The kernel has support for 64-bit physical 
> addresses on 32-bit. IMHO there's no big reason to keep doing that 
> address trick. However, there are some drivers that use unsigned long 
> for storing physical addresses. This is wrong, since 
> pci_resource_start() returns a resource_size_t value. I think it's these 
> drivers that have to be fixed instead of adding workarounds to ppc4xx code.

    Well, I'm not arguing with that. Just tried to clarify the PCI mapping 
thing for myself. :-)

>>    As we now both know, having PCI memory space mapped beyound 4 GB 
>> makes some drivers misbehave as they use 'unsigned long' to store the 
>> result of pci_resource_start() and later ioremap() this truncated 
>> value -- which is 64-bit on Sequoia due to CONFIG_RESOURCE_64BIT=y 
>> that is needed to store the beyond-4GB addresses.

    Luckily, this one concerns the memory resources, as the I/O resources are 
actually limited to 'unsigned long' anyway...

WBR, Sergei