From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Stefan Roese <sr@denx.de>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: [PATCH 1/2] [POWERPC] Add PPC4xx L2-cache support (440GX & 460EX/GT)
Date: Thu, 20 Mar 2008 17:54:52 +1100 [thread overview]
Message-ID: <1205996092.26869.420.camel@pasglop> (raw)
In-Reply-To: <1205847389-17771-1-git-send-email-sr@denx.de>
On Tue, 2008-03-18 at 14:36 +0100, Stefan Roese wrote:
> This patch adds support for the 256k L2 cache found on some IBM/AMCC
> 4xx PPC's. It introduces a common 4xx SoC file (sysdev/ppc4xx_soc.c)
> which currently "only" adds the L2 cache init code. Other common 4xx
> stuff can be added later here.
>
> The L2 cache handling code is just a copy of Eugene's code in arch/ppc
> with small modifications.
>
> Tested on AMCC Taishan 440GX and Canyonlands 460EX.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
It's my understanding that on some 44x platforms, the l2 needs to be
explicitely invalidated on DMAs. Do we know more about that ? I think it
depends on something like the number of masters on the PLB4 or so. I
don't remember the details.
Ben.
next prev parent reply other threads:[~2008-03-20 6:55 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-03-18 13:36 [PATCH 1/2] [POWERPC] Add PPC4xx L2-cache support (440GX & 460EX/GT) Stefan Roese
2008-03-19 23:27 ` Stephen Rothwell
2008-03-20 6:35 ` Stefan Roese
2008-03-20 6:54 ` Benjamin Herrenschmidt [this message]
2008-03-20 7:12 ` Stefan Roese
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