[PATCH 1/5 v2] powerpc: DTS file for the C2K

[PATCH 1/5 v2] powerpc: DTS file for the C2K

[Remi Machet]

Support for the C2K cPCI Single Board Computer from GEFanuc
(PowerPC MPC7448 with a Marvell MV64460 chipset)
All features of the board are not supported yet, but the board
boots, flash works, all Ethernet ports are working and PCI 
devices are all found (USB and SATA on PCI1 do not work yet).

Part 1 of 5: DTS file describing the board peripherals. As far as I know
all peripherals except the FPGA are listed in there (I did not included
the FPGA because a lot of work is needed there).

Signed-off-by: Remi Machet <rmachet@slac.stanford.edu>
---
Changes:
v1: original patch
v2: cleaned up the file: removed i2c device_type, changed the name of
the cpu node and added aliases for the pci buses.

 c2k.dts |  355 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 355 insertions(+)

diff --git a/arch/powerpc/boot/dts/c2k.dts b/arch/powerpc/boot/dts/c2k.dts
new file mode 100644
index 0000000..29867cb
--- /dev/null
+++ b/arch/powerpc/boot/dts/c2k.dts
@@ -0,0 +1,355 @@
+/* Device Tree Source for GEFanuc C2K
+ *
+ * Author: Remi Machet <rmachet@slac.stanford.edu>
+ * 
+ * Originated from prpmc2800.dts
+ *
+ * 2008 (c) Stanford University
+ * 2007 (c) MontaVista, Software, Inc.  
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "C2K";
+	compatible = "GEFanuc,C2K";
+	coherency-off;
+
+	aliases {
+		pci0 = &PCI0;
+		pci1 = &PCI1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "PowerPC,7447";
+			reg = <0>;
+			clock-frequency = <996000000>;	/* 996 MHz */
+			bus-frequency = <166666667>;	/* 166.6666 MHz */
+			timebase-frequency = <41666667>;	/* 166.6666/4 MHz */
+			i-cache-line-size = <32>;
+			d-cache-line-size = <32>;
+			i-cache-size = <32768>;
+			d-cache-size = <32768>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>;	/* 1GB */
+	};
+
+	system-controller@d8000000 { /* Marvell Discovery */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		model = "mv64460";
+		compatible = "marvell,mv64360";
+		clock-frequency = <166666667>;		/* 166.66... MHz */
+		reg = <0xd8000000 0x00010000>;
+		virtual-reg = <0xd8000000>;
+		ranges = <0xd4000000 0xd4000000 0x01000000	/* PCI 0 I/O Space */
+			  0x80000000 0x80000000 0x08000000	/* PCI 0 MEM Space */
+			  0xd0000000 0xd0000000 0x01000000	/* PCI 1 I/O Space */
+			  0xa0000000 0xa0000000 0x08000000	/* PCI 1 MEM Space */
+			  0xf8000000 0xf8000000 0x08000000	/* User FLASH */
+			  0x00000000 0xd8000000 0x00010000	/* Bridge's regs */
+			  0xd8140000 0xd8140000 0x00040000>;	/* Integrated SRAM */
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "marvell,mv64360-mdio";
+			PHY0: ethernet-phy@0 {
+				device_type = "ethernet-phy";
+				interrupts = <76>;	/* GPP 12 */
+				interrupt-parent = <&PIC>;
+				reg = <0>;
+			};
+			PHY1: ethernet-phy@1 {
+				device_type = "ethernet-phy";
+				interrupts = <76>;	/* GPP 12 */
+				interrupt-parent = <&PIC>;
+				reg = <1>;
+			};
+			PHY2: ethernet-phy@2 {
+				device_type = "ethernet-phy";
+				interrupts = <76>;	/* GPP 12 */
+				interrupt-parent = <&PIC>;
+				reg = <2>;
+			};
+		};
+
+		ethernet-group@2000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "marvell,mv64360-eth-group";
+			reg = <0x2000 0x2000>;
+			ethernet@0 {
+				device_type = "network";
+				compatible = "marvell,mv64360-eth";
+				reg = <0>;
+				interrupts = <32>;
+				interrupt-parent = <&PIC>;
+				phy = <&PHY0>;
+				local-mac-address = [ 00 00 00 00 00 00 ];
+			};
+			ethernet@1 {
+				device_type = "network";
+				compatible = "marvell,mv64360-eth";
+				reg = <1>;
+				interrupts = <33>;
+				interrupt-parent = <&PIC>;
+				phy = <&PHY1>;
+				local-mac-address = [ 00 00 00 00 00 00 ];
+			};
+			ethernet@2 {
+				device_type = "network";
+				compatible = "marvell,mv64360-eth";
+				reg = <2>;
+				interrupts = <34>;
+				interrupt-parent = <&PIC>;
+				phy = <&PHY2>;
+				local-mac-address = [ 00 00 00 00 00 00 ];
+			};
+		};
+
+		SDMA0: sdma@4000 {
+			compatible = "marvell,mv64360-sdma";
+			reg = <0x4000 0xc18>;
+			virtual-reg = <0xd8004000>;
+			interrupt-base = <0>;
+			interrupts = <36>;
+			interrupt-parent = <&PIC>;
+		};
+
+		SDMA1: sdma@6000 {
+			compatible = "marvell,mv64360-sdma";
+			reg = <0x6000 0xc18>;
+			virtual-reg = <0xd8006000>;
+			interrupt-base = <0>;
+			interrupts = <38>;
+			interrupt-parent = <&PIC>;
+		};
+
+		BRG0: brg@b200 {
+			compatible = "marvell,mv64360-brg";
+			reg = <0xb200 0x8>;
+			clock-src = <8>;
+			clock-frequency = <133333333>;
+			current-speed = <115200>;
+		};
+
+		BRG1: brg@b208 {
+			compatible = "marvell,mv64360-brg";
+			reg = <0xb208 0x8>;
+			clock-src = <8>;
+			clock-frequency = <133333333>;
+			current-speed = <115200>;
+		};
+
+		CUNIT: cunit@f200 {
+			reg = <0xf200 0x200>;
+		};
+
+		MPSCROUTING: mpscrouting@b400 {
+			reg = <0xb400 0xc>;
+		};
+
+		MPSCINTR: mpscintr@b800 {
+			reg = <0xb800 0x100>;
+			virtual-reg = <0xd800b800>;
+		};
+
+		MPSC0: mpsc@8000 {
+			device_type = "serial";
+			compatible = "marvell,mv64360-mpsc";
+			reg = <0x8000 0x38>;
+			virtual-reg = <0xd8008000>;
+			sdma = <&SDMA0>;
+			brg = <&BRG0>;
+			cunit = <&CUNIT>;
+			mpscrouting = <&MPSCROUTING>;
+			mpscintr = <&MPSCINTR>;
+			cell-index = <0>;
+			interrupts = <40>;
+			interrupt-parent = <&PIC>;
+		};
+
+		MPSC1: mpsc@9000 {
+			device_type = "serial";
+			compatible = "marvell,mv64360-mpsc";
+			reg = <0x9000 0x38>;
+			virtual-reg = <0xd8009000>;
+			sdma = <&SDMA1>;
+			brg = <&BRG1>;
+			cunit = <&CUNIT>;
+			mpscrouting = <&MPSCROUTING>;
+			mpscintr = <&MPSCINTR>;
+			cell-index = <1>;
+			interrupts = <42>;
+			interrupt-parent = <&PIC>;
+		};
+
+		wdt@b410 {			/* watchdog timer */
+			compatible = "marvell,mv64360-wdt";
+			reg = <0xb410 0x8>;
+		};
+
+		i2c@c000 {
+			compatible = "marvell,mv64360-i2c";
+			reg = <0xc000 0x20>;
+			virtual-reg = <0xd800c000>;
+			interrupts = <37>;
+			interrupt-parent = <&PIC>;
+		};
+
+		PIC: pic {
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			compatible = "marvell,mv64360-pic";
+			reg = <0x0000 0x88>;
+			interrupt-controller;
+		};
+
+		mpp@f000 {
+			compatible = "marvell,mv64360-mpp";
+			reg = <0xf000 0x10>;
+		};
+
+		gpp@f100 {
+			compatible = "marvell,mv64360-gpp";
+			reg = <0xf100 0x20>;
+		};
+
+		PCI0: pci@80000000 {
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			compatible = "marvell,mv64360-pci";
+			reg = <0x0cf8 0x8>;
+			ranges = <0x01000000 0x0 0x00000000 0xd4000000 0x0 0x01000000
+				  0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>;
+			bus-range = <0 255>;
+			clock-frequency = <66000000>;
+			interrupt-pci-iack = <0x0c34>;
+			interrupt-parent = <&PIC>;
+			interrupt-map-mask = <0x0000 0x0 0x0 0x7>;
+			interrupt-map = <
+				/* Only one interrupt line for PMC0 slot (INTA) */
+				0x0000 0 0 1 &PIC 88
+			>;
+		};
+
+
+		PCI1: pci@a0000000 {
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			compatible = "marvell,mv64360-pci";
+			reg = <0x0c78 0x8>;
+			ranges = <0x01000000 0x0 0x00000000 0xd0000000 0x0 0x01000000
+				  0x02000000 0x0 0x80000000 0xa0000000 0x0 0x08000000>;
+			bus-range = <0 255>;
+			clock-frequency = <66000000>;
+			interrupt-pci-iack = <0x0cb4>;
+			interrupt-parent = <&PIC>;
+			interrupt-map-mask = <0xf800 0x00 0x00 0x7>;
+			interrupt-map = <
+				/* IDSEL 0x01: PMC1 ? */
+				0x0800 0 0 1 &PIC 88
+				/* IDSEL 0x02: cPCI bridge */
+				0x1000 0 0 1 &PIC 88
+				/* IDSEL 0x03: USB controller */
+				0x1800 0 0 1 &PIC 91
+				/* IDSEL 0x04: SATA controller */
+				0x2000 0 0 1 &PIC 95
+			>;
+		};
+
+		cpu-error@0070 {
+			compatible = "marvell,mv64360-cpu-error";
+			reg = <0x0070 0x10 0x0128 0x28>;
+			interrupts = <3>;
+			interrupt-parent = <&PIC>;
+		};
+
+		sram-ctrl@0380 {
+			compatible = "marvell,mv64360-sram-ctrl";
+			reg = <0x0380 0x80>;
+			interrupts = <13>;
+			interrupt-parent = <&PIC>;
+		};
+
+		pci-error@1d40 {
+			compatible = "marvell,mv64360-pci-error";
+			reg = <0x1d40 0x40 0x0c28 0x4>;
+			interrupts = <12>;
+			interrupt-parent = <&PIC>;
+		};
+
+		pci-error@1dc0 {
+			compatible = "marvell,mv64360-pci-error";
+			reg = <0x1dc0 0x40 0x0ca8 0x4>;
+			interrupts = <16>;
+			interrupt-parent = <&PIC>;
+		};
+
+		mem-ctrl@1400 {
+			compatible = "marvell,mv64360-mem-ctrl";
+			reg = <0x1400 0x60>;
+			interrupts = <17>;
+			interrupt-parent = <&PIC>;
+		};
+		/* Devices attached to the device controller */
+		devicebus {
+			compatible = "marvell,mv64306-devctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			nor_flash {
+				compatible = "cfi-flash";
+				reg = <0xf8000000 0x8000000>; /* 128MB */
+				bank-width = <4>;
+				device-width = <1>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				partition@0 {
+					label = "boot";
+					reg = <0x00000000 0x00080000>;
+				};
+				partition@40000 {
+					label = "kernel";
+					reg = <0x00080000 0x00400000>;
+				};
+				partition@440000 {
+					label = "initrd";
+					reg = <0x00480000 0x00B80000>;
+				};
+				partition@1000000 {
+					label = "rootfs";
+					reg = <0x01000000 0x06800000>;
+				};
+				partition@7800000 {
+					label = "recovery";
+					reg = <0x07800000 0x00800000>;
+					read-only;
+				};
+			};
+		};
+	};
+	chosen {
+		bootargs = "ip=off root=/dev/mtdblock3 rootfstype=jffs2";
+		linux,stdout-path = &MPSC0;
+	};
+};

Re: [PATCH 1/5 v2] powerpc: DTS file for the C2K

[David Gibson]

On Fri, May 16, 2008 at 12:28:48PM -0700, Remi Machet wrote:
> Support for the C2K cPCI Single Board Computer from GEFanuc
> (PowerPC MPC7448 with a Marvell MV64460 chipset)
> All features of the board are not supported yet, but the board
> boots, flash works, all Ethernet ports are working and PCI 
> devices are all found (USB and SATA on PCI1 do not work yet).
> 
> Part 1 of 5: DTS file describing the board peripherals. As far as I know
> all peripherals except the FPGA are listed in there (I did not included
> the FPGA because a lot of work is needed there).

Looking pretty good, but a hanful more comments below.

[snip]
> +		mdio {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "marvell,mv64360-mdio";

Surely this needs a "reg" property, otherwise how to you access the
mdio bus?

> +			PHY0: ethernet-phy@0 {
> +				device_type = "ethernet-phy";
> +				interrupts = <76>;	/* GPP 12 */
> +				interrupt-parent = <&PIC>;
> +				reg = <0>;
> +			};

[snip]
> +		CUNIT: cunit@f200 {
> +			reg = <0xf200 0x200>;
> +		};
> +
> +		MPSCROUTING: mpscrouting@b400 {
> +			reg = <0xb400 0xc>;
> +		};
> +
> +		MPSCINTR: mpscintr@b800 {
> +			reg = <0xb800 0x100>;
> +			virtual-reg = <0xd800b800>;
> +		};
> +
> +		MPSC0: mpsc@8000 {
> +			device_type = "serial";
> +			compatible = "marvell,mv64360-mpsc";
> +			reg = <0x8000 0x38>;
> +			virtual-reg = <0xd8008000>;
> +			sdma = <&SDMA0>;
> +			brg = <&BRG0>;
> +			cunit = <&CUNIT>;
> +			mpscrouting = <&MPSCROUTING>;
> +			mpscintr = <&MPSCINTR>;
> +			cell-index = <0>;

Heh.  The more I look at this, the more I suspect it should be
structured like the ethernet-group stuff.  Oh well, not your fault.

[snip]
> +		/* Devices attached to the device controller */
> +		devicebus {
> +			compatible = "marvell,mv64306-devctrl";
> +			#address-cells = <1>;
> +			#size-cells = <1>;

This looks like it needs either a "reg" or a "ranges" property.  If
the address space of this "devicebus" is the same as the parent bus
you need an empty "ranges" property.  *No* ranges property means the
subordinate devices can't be directly accessed at all from the parent
bus.

> +			nor_flash {

This needs a unit address, "nor_flash@f8000000".

> +				compatible = "cfi-flash";
> +				reg = <0xf8000000 0x8000000>; /* 128MB */
> +				bank-width = <4>;
> +				device-width = <1>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				partition@0 {
> +					label = "boot";
> +					reg = <0x00000000 0x00080000>;
> +				};
> +				partition@40000 {
> +					label = "kernel";
> +					reg = <0x00080000 0x00400000>;
> +				};
> +				partition@440000 {
> +					label = "initrd";
> +					reg = <0x00480000 0x00B80000>;
> +				};
> +				partition@1000000 {
> +					label = "rootfs";
> +					reg = <0x01000000 0x06800000>;
> +				};
> +				partition@7800000 {
> +					label = "recovery";
> +					reg = <0x07800000 0x00800000>;
> +					read-only;
> +				};
> +			};
> +		};
> +	};
> +	chosen {
> +		bootargs = "ip=off root=/dev/mtdblock3 rootfstype=jffs2";

You don't usually want to encode a default bootargs into the dts file;
kernel command line arguments should usually be left to the user.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [PATCH 1/5 v2] powerpc: DTS file for the C2K

[David Gibson]

On Mon, May 19, 2008 at 10:53:42AM +1000, David Gibson wrote:
> On Fri, May 16, 2008 at 12:28:48PM -0700, Remi Machet wrote:
> > Support for the C2K cPCI Single Board Computer from GEFanuc

[snip]
> [snip]
> > +		/* Devices attached to the device controller */
> > +		devicebus {
> > +			compatible = "marvell,mv64306-devctrl";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> 
> This looks like it needs either a "reg" or a "ranges" property.  If
> the address space of this "devicebus" is the same as the parent bus
> you need an empty "ranges" property.  *No* ranges property means the
> subordinate devices can't be directly accessed at all from the parent
> bus.

Oh, one other comment here.  Is this another of these random
peripheral busses with a bunch of registers controlling which chip
selects appear at which address offsets and so forth (like ebc on 4xx
or localbus on freescale)?  If so, the normal convention to describe
such busses is *not* to have a 1:1 address mapping, but actually
encode the addresses of the subordinate devices as <chipselect
offset>, then have an appropriate "ranges" property to map those into
the addresses on the parent bus (the ranges property can be filled in
by the bootwrapper from the actual bridge configuration registers, if
necessary).  The rationale is again to have the device tree describe
hardware, not configuration as much as possible.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [PATCH 1/5 v2] powerpc: DTS file for the C2K

[Remi Machet]

> On Mon, 2008-05-19 at 10:53 +1000, David Gibson wrote: 
> On Fri, May 16, 2008 at 12:28:48PM -0700, Remi Machet wrote:
> > Support for the C2K cPCI Single Board Computer from GEFanuc
> > (PowerPC MPC7448 with a Marvell MV64460 chipset)
> > All features of the board are not supported yet, but the board
> > boots, flash works, all Ethernet ports are working and PCI 
> > devices are all found (USB and SATA on PCI1 do not work yet).
> > 
> > Part 1 of 5: DTS file describing the board peripherals. As far as I know
> > all peripherals except the FPGA are listed in there (I did not included
> > the FPGA because a lot of work is needed there).
> 
> Looking pretty good, but a hanful more comments below.
> 
> [snip]
> > +		mdio {
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			compatible = "marvell,mv64360-mdio";
> 
> Surely this needs a "reg" property, otherwise how to you access the
> mdio bus?
I am afraid this is another situation where the driver is not fully
using the OF description ... the PHY registers address is hard-coded in
drivers/net/mv643xx_eth.c. In any case I will add the reg property, and
later on can try to modify the driver to make use of it.

> [snip]
> > +		/* Devices attached to the device controller */
> > +		devicebus {
> > +			compatible = "marvell,mv64306-devctrl";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> 
> This looks like it needs either a "reg" or a "ranges" property.  If
> the address space of this "devicebus" is the same as the parent bus
> you need an empty "ranges" property.  *No* ranges property means the
> subordinate devices can't be directly accessed at all from the parent
> bus.
This is a static bus with chip selects, I will look at other dts files
to properly implement it (with the chipselect and range properties).

> 
> > +			nor_flash {
> 
> This needs a unit address, "nor_flash@f8000000".
> 
[ snip ]

> > +	chosen {
> > +		bootargs = "ip=off root=/dev/mtdblock3 rootfstype=jffs2";
> 
> You don't usually want to encode a default bootargs into the dts file;
> kernel command line arguments should usually be left to the user.
Ok I will remove that.

Thanks for all the comments, I will re-submit a patch as soon as I have
fixed all that.

Remi

Re: [PATCH 1/5 v2] powerpc: DTS file for the C2K

[David Gibson]

On Mon, May 19, 2008 at 10:53:02AM -0700, Remi Machet wrote:
> > On Mon, 2008-05-19 at 10:53 +1000, David Gibson wrote: 
> > On Fri, May 16, 2008 at 12:28:48PM -0700, Remi Machet wrote:
> > > Support for the C2K cPCI Single Board Computer from GEFanuc
> > > (PowerPC MPC7448 with a Marvell MV64460 chipset)
> > > All features of the board are not supported yet, but the board
> > > boots, flash works, all Ethernet ports are working and PCI 
> > > devices are all found (USB and SATA on PCI1 do not work yet).
> > > 
> > > Part 1 of 5: DTS file describing the board peripherals. As far as I know
> > > all peripherals except the FPGA are listed in there (I did not included
> > > the FPGA because a lot of work is needed there).
> > 
> > Looking pretty good, but a hanful more comments below.
> > 
> > [snip]
> > > +		mdio {
> > > +			#address-cells = <1>;
> > > +			#size-cells = <0>;
> > > +			compatible = "marvell,mv64360-mdio";
> > 
> > Surely this needs a "reg" property, otherwise how to you access the
> > mdio bus?
> I am afraid this is another situation where the driver is not fully
> using the OF description ... the PHY registers address is hard-coded in
> drivers/net/mv643xx_eth.c. In any case I will add the reg property, and
> later on can try to modify the driver to make use of it.

Yes, do that.  Again, the device tree describes hardware not
software's use of it, so just because the driver doesn't use it
properly yet isn't a reason to leave things out.

> > [snip]
> > > +		/* Devices attached to the device controller */
> > > +		devicebus {
> > > +			compatible = "marvell,mv64306-devctrl";
> > > +			#address-cells = <1>;
> > > +			#size-cells = <1>;
> > 
> > This looks like it needs either a "reg" or a "ranges" property.  If
> > the address space of this "devicebus" is the same as the parent bus
> > you need an empty "ranges" property.  *No* ranges property means the
> > subordinate devices can't be directly accessed at all from the parent
> > bus.
> This is a static bus with chip selects, I will look at other dts files
> to properly implement it (with the chipselect and range properties).

ebony.dts and bamboo.dts have examples of the 4xx EBC, and the
ibm4xx_fixup_ebc_ranges() function in arch/powerpc/boot/4xx.c gives an
example of constructing the ranges property from the bridge register
configuration.  booting-without-of.txt has a binding for the freescale
chipselect / localbus.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson