[PATCH] powerpc/booke: Add support for new e500mc core

[PATCH] powerpc/booke: Add support for new e500mc core

[Kumar Gala]

The new e500mc core from Freescale is based on the e500v2 but with the
following changes:

* Supports only the Enhanced Debug Architecture (DSRR0/1, etc)
* Floating Point
* No SPE
* Supports lwsync
* Doorbell Exceptions
* Hypervisor

---

In my powerpc-next tree.

 arch/powerpc/kernel/cputable.c         |   15 +++++++++++++++
 arch/powerpc/kernel/head_booke.h       |    6 +++++-
 arch/powerpc/kernel/head_fsl_booke.S   |   10 ++++++++--
 arch/powerpc/platforms/Kconfig.cputype |   10 ++++++++--
 include/asm-powerpc/cache.h            |    3 +++
 include/asm-powerpc/cputable.h         |    6 ++++--
 include/asm-powerpc/synch.h            |    2 +-
 7 files changed, 44 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index e44d553..36fa061 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1522,6 +1522,21 @@ static struct cpu_spec __initdata cpu_specs[] = {
 		.machine_check		= machine_check_e500,
 		.platform		= "ppc8548",
 	},
+	{	/* e500mc */
+		.pvr_mask		= 0xffff0000,
+		.pvr_value		= 0x80230000,
+		.cpu_name		= "e500mc",
+		/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
+		.cpu_features		= CPU_FTRS_E500MC,
+		.cpu_user_features	= COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+		.icache_bsize		= 64,
+		.dcache_bsize		= 64,
+		.num_pmcs		= 4,
+		.oprofile_cpu_type	= "ppc/e500", /* xxx - galak, e500mc? */
+		.oprofile_type		= PPC_OPROFILE_FSL_EMB,
+		.machine_check		= machine_check_e500,
+		.platform		= "ppc4080",
+	},
 	{	/* default match */
 		.pvr_mask		= 0x00000000,
 		.pvr_value		= 0x00000000,
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index 9501c58..505494f 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -68,9 +68,13 @@
 #define MCHECK_STACK_BASE	mcheckirq_ctx
 #define CRIT_STACK_BASE		critirq_ctx

-/* only on e200 for now */
+/* only on e500mc/e200 */
 #define DEBUG_STACK_BASE	dbgirq_ctx
+#ifdef CONFIG_PPC_E500MC
+#define DEBUG_SPRG		SPRN_SPRG9
+#else
 #define DEBUG_SPRG		SPRN_SPRG6W
+#endif

 #define EXC_LVL_FRAME_OVERHEAD	(THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)

diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 503f860..7c2b653 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -304,7 +304,7 @@ skpinv:	addi	r6,r6,1				/* Increment */
 	SET_IVOR(13, DataTLBError);
 	SET_IVOR(14, InstructionTLBError);
 	SET_IVOR(15, DebugDebug);
-#if defined(CONFIG_E500)
+#if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
 	SET_IVOR(15, DebugCrit);
 #endif
 	SET_IVOR(32, SPEUnavailable);
@@ -313,6 +313,9 @@ skpinv:	addi	r6,r6,1				/* Increment */
 #ifndef CONFIG_E200
 	SET_IVOR(35, PerformanceMonitor);
 #endif
+#ifdef CONFIG_PPC_E500MC
+	SET_IVOR(36, Doorbell);
+#endif

 	/* Establish the interrupt vector base */
 	lis	r4,interrupt_base@h	/* IVPR only uses the high 16-bits */
@@ -750,10 +753,13 @@ interrupt_base:
 	/* Performance Monitor */
 	EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)

+#ifdef CONFIG_PPC_E500MC
+	EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_EE)
+#endif

 	/* Debug Interrupt */
 	DEBUG_DEBUG_EXCEPTION
-#if defined(CONFIG_E500)
+#if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
 	DEBUG_CRIT_EXCEPTION
 #endif

diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index f7efaa9..9e67cf1 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -95,6 +95,12 @@ config E500
 	select FSL_EMB_PERFMON
 	bool

+config PPC_E500MC
+	bool "e500mc Support"
+	select PPC_FPU
+	depends on E500
+	default n
+
 config PPC_FPU
 	bool
 	default y if PPC64
@@ -157,7 +163,7 @@ config ALTIVEC

 config SPE
 	bool "SPE Support"
-	depends on E200 || E500
+	depends on E200 || (E500 && !PPC_E500MC)
 	default y
 	---help---
 	  This option enables kernel support for the Signal Processing
@@ -201,7 +207,7 @@ config VIRT_CPU_ACCOUNTING
 	  If in doubt, say Y here.

 config SMP
-	depends on PPC_STD_MMU
+	depends on PPC_STD_MMU || FSL_BOOKE
 	bool "Symmetric multi-processing support"
 	---help---
 	  This enables support for systems with more than one CPU. If you have
diff --git a/include/asm-powerpc/cache.h b/include/asm-powerpc/cache.h
index 5350704..81de6eb 100644
--- a/include/asm-powerpc/cache.h
+++ b/include/asm-powerpc/cache.h
@@ -8,6 +8,9 @@
 #if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
 #define L1_CACHE_SHIFT		4
 #define MAX_COPY_PREFETCH	1
+#elif defined(CONFIG_PPC_E500MC)
+#define L1_CACHE_SHIFT		6
+#define MAX_COPY_PREFETCH	4
 #elif defined(CONFIG_PPC32)
 #define L1_CACHE_SHIFT		5
 #define MAX_COPY_PREFETCH	4
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 1e79673..a3dce17 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -351,6 +351,8 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 	    CPU_FTR_NODSISRALIGN)
 #define CPU_FTRS_E500_2	(CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
 	    CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
+#define CPU_FTRS_E500MC	(CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS | \
+	    CPU_FTR_NODSISRALIGN)
 #define CPU_FTRS_GENERIC_32	(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)

 /* 64-bit CPUs */
@@ -421,7 +423,7 @@ enum {
 	    CPU_FTRS_E200 |
 #endif
 #ifdef CONFIG_E500
-	    CPU_FTRS_E500 | CPU_FTRS_E500_2 |
+	    CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
 #endif
 	    0,
 };
@@ -461,7 +463,7 @@ enum {
 	    CPU_FTRS_E200 &
 #endif
 #ifdef CONFIG_E500
-	    CPU_FTRS_E500 & CPU_FTRS_E500_2 &
+	    CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
 #endif
 	    CPU_FTRS_POSSIBLE,
 };
diff --git a/include/asm-powerpc/synch.h b/include/asm-powerpc/synch.h
index 2cda3c3..42a1ef5 100644
--- a/include/asm-powerpc/synch.h
+++ b/include/asm-powerpc/synch.h
@@ -4,7 +4,7 @@

 #include <linux/stringify.h>

-#ifdef __powerpc64__
+#if defined(__powerpc64__) || defined(CONFIG_PPC_E500MC)
 #define __SUBARCH_HAS_LWSYNC
 #endif

-- 
1.5.5.1

Re: [PATCH] powerpc/booke: Add support for new e500mc core

[Becky Bruce]

On Jun 16, 2008, at 10:46 AM, Kumar Gala wrote:

> The new e500mc core from Freescale is based on the e500v2 but with the
> following changes:
>
> * Supports only the Enhanced Debug Architecture (DSRR0/1, etc)
> * Floating Point
> * No SPE
> * Supports lwsync
> * Doorbell Exceptions
> * Hypervisor
>
> ---
>
> In my powerpc-next tree.
>
>  arch/powerpc/kernel/cputable.c         |   15 +++++++++++++++
>  arch/powerpc/kernel/head_booke.h       |    6 +++++-
>  arch/powerpc/kernel/head_fsl_booke.S   |   10 ++++++++--
>  arch/powerpc/platforms/Kconfig.cputype |   10 ++++++++--
>  include/asm-powerpc/cache.h            |    3 +++
>  include/asm-powerpc/cputable.h         |    6 ++++--
>  include/asm-powerpc/synch.h            |    2 +-
>  7 files changed, 44 insertions(+), 8 deletions(-)
>
> diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/ 
> cputable.c
> index e44d553..36fa061 100644
> --- a/arch/powerpc/kernel/cputable.c
> +++ b/arch/powerpc/kernel/cputable.c
> @@ -1522,6 +1522,21 @@ static struct cpu_spec __initdata cpu_specs 
> [] = {
>  		.machine_check		= machine_check_e500,
>  		.platform		= "ppc8548",
>  	},
> +	{	/* e500mc */
> +		.pvr_mask		= 0xffff0000,
> +		.pvr_value		= 0x80230000,
> +		.cpu_name		= "e500mc",
> +		/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
> +		.cpu_features		= CPU_FTRS_E500MC,
> +		.cpu_user_features	= COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
> +		.icache_bsize		= 64,
> +		.dcache_bsize		= 64,
> +		.num_pmcs		= 4,
> +		.oprofile_cpu_type	= "ppc/e500", /* xxx - galak, e500mc? */
> +		.oprofile_type		= PPC_OPROFILE_FSL_EMB,
> +		.machine_check		= machine_check_e500,
> +		.platform		= "ppc4080",
> +	},
>  	{	/* default match */
>  		.pvr_mask		= 0x00000000,
>  		.pvr_value		= 0x00000000,

Did you intend to leave your 2 "xxx - galak" comments in here?

Also, I think you have a problem - you allow CONFIG_SMP to be set  
with CONFIG_FSL_BOOKE now, but if you actually turn on CONFIG_SMP, in  
pgtable_32.c you're going to have build problems.  CONFIG_SMP enables  
hash_page_sync(), which we don't have on BookE.  You need to add a ! 
BOOKE to the config protections in pgtable_32.c for hash_page_sync()  
declaration and callers.

Cheers,
Becky

Re: [PATCH] powerpc/booke: Add support for new e500mc core

[Kumar Gala]

On Jun 16, 2008, at 11:56 AM, Becky Bruce wrote:

>
> On Jun 16, 2008, at 10:46 AM, Kumar Gala wrote:
>
>> The new e500mc core from Freescale is based on the e500v2 but with  
>> the
>> following changes:
>>
>> * Supports only the Enhanced Debug Architecture (DSRR0/1, etc)
>> * Floating Point
>> * No SPE
>> * Supports lwsync
>> * Doorbell Exceptions
>> * Hypervisor
>>
>> ---
>>
>> In my powerpc-next tree.
>>
>> arch/powerpc/kernel/cputable.c         |   15 +++++++++++++++
>> arch/powerpc/kernel/head_booke.h       |    6 +++++-
>> arch/powerpc/kernel/head_fsl_booke.S   |   10 ++++++++--
>> arch/powerpc/platforms/Kconfig.cputype |   10 ++++++++--
>> include/asm-powerpc/cache.h            |    3 +++
>> include/asm-powerpc/cputable.h         |    6 ++++--
>> include/asm-powerpc/synch.h            |    2 +-
>> 7 files changed, 44 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/ 
>> cputable.c
>> index e44d553..36fa061 100644
>> --- a/arch/powerpc/kernel/cputable.c
>> +++ b/arch/powerpc/kernel/cputable.c
>> @@ -1522,6 +1522,21 @@ static struct cpu_spec __initdata  
>> cpu_specs[] = {
>> 		.machine_check		= machine_check_e500,
>> 		.platform		= "ppc8548",
>> 	},
>> +	{	/* e500mc */
>> +		.pvr_mask		= 0xffff0000,
>> +		.pvr_value		= 0x80230000,
>> +		.cpu_name		= "e500mc",
>> +		/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
>> +		.cpu_features		= CPU_FTRS_E500MC,
>> +		.cpu_user_features	= COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
>> +		.icache_bsize		= 64,
>> +		.dcache_bsize		= 64,
>> +		.num_pmcs		= 4,
>> +		.oprofile_cpu_type	= "ppc/e500", /* xxx - galak, e500mc? */
>> +		.oprofile_type		= PPC_OPROFILE_FSL_EMB,
>> +		.machine_check		= machine_check_e500,
>> +		.platform		= "ppc4080",
>> +	},
>> 	{	/* default match */
>> 		.pvr_mask		= 0x00000000,
>> 		.pvr_value		= 0x00000000,
>
> Did you intend to leave your 2 "xxx - galak" comments in here?

Yes, the _CAN_DOZE exists on all e500's right now and will go away  
once we resolve the e500 PM patch from Dave Liu.  The perf mon comment  
I plan on keeping around for now.

> Also, I think you have a problem - you allow CONFIG_SMP to be set  
> with CONFIG_FSL_BOOKE now, but if you actually turn on CONFIG_SMP,  
> in pgtable_32.c you're going to have build problems.  CONFIG_SMP  
> enables hash_page_sync(), which we don't have on BookE.  You need to  
> add a !BOOKE to the config protections in pgtable_32.c for  
> hash_page_sync() declaration and callers.

Yeah, I'll drop the CONFIG_SMP bits since the full blown SMP support  
for fsl booke isnt in the tree (at which time we will address the  
issue you raise).

- k

Re: [PATCH] powerpc/booke: Add support for new e500mc core

[Olof Johansson]

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On Jun 16, 2008, at 10:46 AM, Kumar Gala wrote:
>
> --- a/arch/powerpc/kernel/cputable.c
> +++ b/arch/powerpc/kernel/cputable.c
> @@ -1522,6 +1522,21 @@ static struct cpu_spec __initdata cpu_specs[]  
> = {
> 		.machine_check		= machine_check_e500,
> 		.platform		= "ppc8548",
> 	},
> +	{	/* e500mc */
> +		.pvr_mask		= 0xffff0000,
> +		.pvr_value		= 0x80230000,
> +		.cpu_name		= "e500mc",
> +		/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
> +		.cpu_features		= CPU_FTRS_E500MC,
> +		.cpu_user_features	= COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
> +		.icache_bsize		= 64,
> +		.dcache_bsize		= 64,
> +		.num_pmcs		= 4,
> +		.oprofile_cpu_type	= "ppc/e500", /* xxx - galak, e500mc? */
> +		.oprofile_type		= PPC_OPROFILE_FSL_EMB,
> +		.machine_check		= machine_check_e500,
> +		.platform		= "ppc4080",

Do you really want the platform to be this specific?

> diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/ 
> platforms/Kconfig.cputype
> index f7efaa9..9e67cf1 100644
> --- a/arch/powerpc/platforms/Kconfig.cputype
> +++ b/arch/powerpc/platforms/Kconfig.cputype
> @@ -95,6 +95,12 @@ config E500
> 	select FSL_EMB_PERFMON
> 	bool
>
> +config PPC_E500MC
> +	bool "e500mc Support"
> +	select PPC_FPU
> +	depends on E500
> +	default n
> +
> config PPC_FPU
> 	bool
> 	default y if PPC64
> @@ -157,7 +163,7 @@ config ALTIVEC
>
> config SPE
> 	bool "SPE Support"
> -	depends on E200 || E500
> +	depends on E200 || (E500 && !PPC_E500MC)

Why make E500MC a config option, if it's so similar? This way you  
can't make a kernel with SPE support that can boot on both e500{,v2}  
and e500mc...


> config SMP
> -	depends on PPC_STD_MMU
> +	depends on PPC_STD_MMU || FSL_BOOKE

Isn't there quite a bit more needed than just enabling this config  
option for SMP to work? I.e. why not save this for when the rest is  
posted?




-Olof

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Re: [PATCH] powerpc/booke: Add support for new e500mc core

[Benjamin Herrenschmidt]

On Mon, 2008-06-16 at 10:46 -0500, Kumar Gala wrote:
> The new e500mc core from Freescale is based on the e500v2 but with the
> following changes:
> 
> * Supports only the Enhanced Debug Architecture (DSRR0/1, etc)
> * Floating Point
> * No SPE
> * Supports lwsync
             ^^^^^^

It supports SMP ? Is tlbivax broadcast ? Is there a local form ?

Cheers,
Ben.

Re: [PATCH] powerpc/booke: Add support for new e500mc core

[Kumar Gala]

On Jun 16, 2008, at 7:06 PM, Benjamin Herrenschmidt wrote:

> On Mon, 2008-06-16 at 10:46 -0500, Kumar Gala wrote:
>> The new e500mc core from Freescale is based on the e500v2 but with  
>> the
>> following changes:
>>
>> * Supports only the Enhanced Debug Architecture (DSRR0/1, etc)
>> * Floating Point
>> * No SPE
>> * Supports lwsync
>             ^^^^^^
>
> It supports SMP ? Is tlbivax broadcast ? Is there a local form ?

All e500 (v1, v2, mc) have supported tlbivax broadcast, and e500mc  
does support local forms.

- k

Re: [PATCH] powerpc/booke: Add support for new e500mc core

[Kumar Gala]

On Jun 16, 2008, at 2:26 PM, Olof Johansson wrote:

> On Jun 16, 2008, at 10:46 AM, Kumar Gala wrote:
>>
>> --- a/arch/powerpc/kernel/cputable.c
>> +++ b/arch/powerpc/kernel/cputable.c
>> @@ -1522,6 +1522,21 @@ static struct cpu_spec __initdata  
>> cpu_specs[] = {
>> 		.machine_check		= machine_check_e500,
>> 		.platform		= "ppc8548",
>> 	},
>> +	{	/* e500mc */
>> +		.pvr_mask		= 0xffff0000,
>> +		.pvr_value		= 0x80230000,
>> +		.cpu_name		= "e500mc",
>> +		/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
>> +		.cpu_features		= CPU_FTRS_E500MC,
>> +		.cpu_user_features	= COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
>> +		.icache_bsize		= 64,
>> +		.dcache_bsize		= 64,
>> +		.num_pmcs		= 4,
>> +		.oprofile_cpu_type	= "ppc/e500", /* xxx - galak, e500mc? */
>> +		.oprofile_type		= PPC_OPROFILE_FSL_EMB,
>> +		.machine_check		= machine_check_e500,
>> +		.platform		= "ppc4080",
>
> Do you really want the platform to be this specific?

I need to look at how this is being used.  I remember having a  
discussion with Paul about this when introduced platform.

>
>> diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/ 
>> platforms/Kconfig.cputype
>> index f7efaa9..9e67cf1 100644
>> --- a/arch/powerpc/platforms/Kconfig.cputype
>> +++ b/arch/powerpc/platforms/Kconfig.cputype
>> @@ -95,6 +95,12 @@ config E500
>> 	select FSL_EMB_PERFMON
>> 	bool
>>
>> +config PPC_E500MC
>> +	bool "e500mc Support"
>> +	select PPC_FPU
>> +	depends on E500
>> +	default n
>> +
>> config PPC_FPU
>> 	bool
>> 	default y if PPC64
>> @@ -157,7 +163,7 @@ config ALTIVEC
>>
>> config SPE
>> 	bool "SPE Support"
>> -	depends on E200 || E500
>> +	depends on E200 || (E500 && !PPC_E500MC)
>
> Why make E500MC a config option, if it's so similar? This way you  
> can't make a kernel with SPE support that can boot on both e500{,v2}  
> and e500mc...

I need it for the various things that are compile time, like cache  
line size, and lwsync support.  If we can get rid of it in the future  
great.

Since I have to have PPC_E500MC I might as well not provide the option  
to enable SPE since it doesnt exist on e500mc.

>>
>> config SMP
>> -	depends on PPC_STD_MMU
>> +	depends on PPC_STD_MMU || FSL_BOOKE
>
> Isn't there quite a bit more needed than just enabling this config  
> option for SMP to work? I.e. why not save this for when the rest is  
> posted?
>
yes.  I'll drop these bits.

- k

Re: [PATCH] powerpc/booke: Add support for new e500mc core

[Olof Johansson]

On Jun 17, 2008, at 8:56 AM, Kumar Gala wrote:

>
> On Jun 16, 2008, at 2:26 PM, Olof Johansson wrote:
>
>> On Jun 16, 2008, at 10:46 AM, Kumar Gala wrote:
>>> +		.machine_check		= machine_check_e500,
>>> +		.platform		= "ppc4080",
>>
>> Do you really want the platform to be this specific?
>
> I need to look at how this is being used.  I remember having a  
> discussion with Paul about this when introduced platform.

It's used by the AUX vector (AT_PLATFORM), i.e. ld.so can use it to  
load platform-optimized libraries. As such, you probably want it to be  
e500mc instead.

>>> diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/ 
>>> platforms/Kconfig.cputype
>>> index f7efaa9..9e67cf1 100644
>>> --- a/arch/powerpc/platforms/Kconfig.cputype
>>> +++ b/arch/powerpc/platforms/Kconfig.cputype
>>> @@ -95,6 +95,12 @@ config E500
>>> 	select FSL_EMB_PERFMON
>>> 	bool
>>>
>>> +config PPC_E500MC
>>> +	bool "e500mc Support"
>>> +	select PPC_FPU
>>> +	depends on E500
>>> +	default n
>>> +
>>> config PPC_FPU
>>> 	bool
>>> 	default y if PPC64
>>> @@ -157,7 +163,7 @@ config ALTIVEC
>>>
>>> config SPE
>>> 	bool "SPE Support"
>>> -	depends on E200 || E500
>>> +	depends on E200 || (E500 && !PPC_E500MC)
>>
>> Why make E500MC a config option, if it's so similar? This way you  
>> can't make a kernel with SPE support that can boot on both  
>> e500{,v2} and e500mc...
>
> I need it for the various things that are compile time, like cache  
> line size, and lwsync support.  If we can get rid of it in the  
> future great.

I got away without doing that on pa6t since we had the same cacheline  
size but ppc64 has a larger value by default so all that hurt by it  
was some padding/alignment being larger than required. I'm sure some  
of the lowend guys won't be happy if you increase the alignment so  
raising the default is out of the picture, I agree with that.

But: since the cacheline is available in cputable, it can still be  
used at runtime, so as long as the alignments are large enough, stuff  
like the dcbz loops should still be OK (might need an audit though to  
make sure there's nothing missed). With that, you could at least still  
boot an E500MC kernel on E500.

> Since I have to have PPC_E500MC I might as well not provide the  
> option to enable SPE since it doesnt exist on e500mc.

With the above, if the line size is used from cputable you should be  
able to boot an e500mc kernel on e500.


-Olof

Re: [PATCH] powerpc/booke: Add support for new e500mc core

[Kumar Gala]

On Jun 17, 2008, at 9:32 AM, Olof Johansson wrote:

> On Jun 17, 2008, at 8:56 AM, Kumar Gala wrote:
>
>>
>> On Jun 16, 2008, at 2:26 PM, Olof Johansson wrote:
>>
>>> On Jun 16, 2008, at 10:46 AM, Kumar Gala wrote:
>>>> +		.machine_check		= machine_check_e500,
>>>> +		.platform		= "ppc4080",
>>>
>>> Do you really want the platform to be this specific?
>>
>> I need to look at how this is being used.  I remember having a  
>> discussion with Paul about this when introduced platform.
>
> It's used by the AUX vector (AT_PLATFORM), i.e. ld.so can use it to  
> load platform-optimized libraries. As such, you probably want it to  
> be e500mc instead.

Yeah, already changed it to ppce500mc.

>>> Why make E500MC a config option, if it's so similar? This way you  
>>> can't make a kernel with SPE support that can boot on both  
>>> e500{,v2} and e500mc...
>>
>> I need it for the various things that are compile time, like cache  
>> line size, and lwsync support.  If we can get rid of it in the  
>> future great.
>
> I got away without doing that on pa6t since we had the same  
> cacheline size but ppc64 has a larger value by default so all that  
> hurt by it was some padding/alignment being larger than required.  
> I'm sure some of the lowend guys won't be happy if you increase the  
> alignment so raising the default is out of the picture, I agree with  
> that.
>
> But: since the cacheline is available in cputable, it can still be  
> used at runtime, so as long as the alignments are large enough,  
> stuff like the dcbz loops should still be OK (might need an audit  
> though to make sure there's nothing missed). With that, you could at  
> least still boot an E500MC kernel on E500.

Its not as simple as that since there are assumptions about how many  
bytes a dcbz will clear.

>> Since I have to have PPC_E500MC I might as well not provide the  
>> option to enable SPE since it doesnt exist on e500mc.
>
> With the above, if the line size is used from cputable you should be  
> able to boot an e500mc kernel on e500.

This is a goal I have, but we need to work towards it.  For example  
LWSYNC vs SYNC is a #define right now.

- k

Re: [PATCH] powerpc/booke: Add support for new e500mc core

[Olof Johansson]

On Jun 17, 2008, at 9:42 AM, Kumar Gala wrote:

>> But: since the cacheline is available in cputable, it can still be  
>> used at runtime, so as long as the alignments are large enough,  
>> stuff like the dcbz loops should still be OK (might need an audit  
>> though to make sure there's nothing missed). With that, you could  
>> at least still boot an E500MC kernel on E500.
>
> Its not as simple as that since there are assumptions about how many  
> bytes a dcbz will clear.

Ok, ppc64 already gets that info from the cputable, not from compile  
time options. I guess ppc32 lacks that so far.


-Olof

Re: [PATCH] powerpc/booke: Add support for new e500mc core

[Kumar Gala]

On Jun 17, 2008, at 10:04 AM, Olof Johansson wrote:

> On Jun 17, 2008, at 9:42 AM, Kumar Gala wrote:
>
>>> But: since the cacheline is available in cputable, it can still be  
>>> used at runtime, so as long as the alignments are large enough,  
>>> stuff like the dcbz loops should still be OK (might need an audit  
>>> though to make sure there's nothing missed). With that, you could  
>>> at least still boot an E500MC kernel on E500.
>>
>> Its not as simple as that since there are assumptions about how  
>> many bytes a dcbz will clear.
>
> Ok, ppc64 already gets that info from the cputable, not from compile  
> time options. I guess ppc32 lacks that so far.

Yeah, if you look at the asm/cache.h the defines in there are used all  
over the place for ppc32 (like copy_32.S, misc_32.S)

- k