From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Kumar Gala <galak@kernel.crashing.org>
Cc: linuxppc-dev list <linuxppc-dev@ozlabs.org>
Subject: Re: SW TLB MMU rework and SMP issues (pte read/write)
Date: Thu, 17 Jul 2008 07:41:58 +1000 [thread overview]
Message-ID: <1216244518.7740.205.camel@pasglop> (raw)
In-Reply-To: <B2B96B0D-960F-4FB1-A5C1-6146EFB7E563@kernel.crashing.org>
On Wed, 2008-07-16 at 15:57 -0500, Kumar Gala wrote:
> This makes sense. I think we need to order the stores in set_pte_at
> regardless of CONFIG_SMP.
Nah, that shouldn't be necessary.
> Also, I think we should change pte_clear to
> use pte_update() so we only clear the low-order flag bits. Patch will
> be sent shortly for review.
Well... at one point at least we did rely on a PTE page with all PTEs
cleared to be blank. It don't know if that's still the case, I need to
look.
Ben.
next prev parent reply other threads:[~2008-07-16 21:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-07-15 21:58 SW TLB MMU rework and SMP issues Kumar Gala
2008-07-16 2:07 ` Benjamin Herrenschmidt
2008-07-16 20:57 ` SW TLB MMU rework and SMP issues (pte read/write) Kumar Gala
2008-07-16 21:15 ` Kumar Gala
2008-07-16 21:41 ` Benjamin Herrenschmidt [this message]
2008-07-16 22:12 ` Kumar Gala
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