From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E4685DE026 for ; Thu, 17 Jul 2008 07:45:30 +1000 (EST) Subject: Re: SW TLB MMU rework and SMP issues (pte read/write) From: Benjamin Herrenschmidt To: Kumar Gala In-Reply-To: References: <1216174045.7740.152.camel@pasglop> Content-Type: text/plain Date: Thu, 17 Jul 2008 07:41:58 +1000 Message-Id: <1216244518.7740.205.camel@pasglop> Mime-Version: 1.0 Cc: linuxppc-dev list Reply-To: benh@kernel.crashing.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Wed, 2008-07-16 at 15:57 -0500, Kumar Gala wrote: > This makes sense. I think we need to order the stores in set_pte_at > regardless of CONFIG_SMP. Nah, that shouldn't be necessary. > Also, I think we should change pte_clear to > use pte_update() so we only clear the low-order flag bits. Patch will > be sent shortly for review. Well... at one point at least we did rely on a PTE page with all PTEs cleared to be blank. It don't know if that's still the case, I need to look. Ben.