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From: Zhou Rui <vancasperz@yahoo.com.cn>
To: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: Why does one "stw" fail with address translation disabled in PPC405EP?
Date: Sat, 23 Aug 2008 10:26:32 +0200	[thread overview]
Message-ID: <1219479992.7565.17.camel@localhost> (raw)
In-Reply-To: <20080822184213.GA24526@yoda.jdub.homelinux.org>

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在 2008-08-22五的 14:42 -0400,Josh Boyer写道:
> On Fri, Aug 22, 2008 at 08:27:15PM +0200, Zhou Rui wrote:
> >Hi, all:
> >    I think I meet an odd problem with PPC405EP (PPChameleonEVB Board).
> 
> What kernel version are you using?

linux-2.6.19.2 from ELDK4.1
> 
> >    I am running a kernel module which will execute a user space
> >application. The entry point of the application is 0x100000a0. At the
> 
> That should be the first clue that you are doing it wrong.  Don't do
> stuff like that in modules...

Oh, but our project needs a function like that ...
> 
> >moment when the processor tries to execute the application, 0x100000a0
> >is not in TLB (this can be seen from BDI by printing out TLB entries),
> >so DTLBMiss is called automatically and then finish_tlb_load. However,
> >InstructionAccess is followed and the problem arises here.
> >InstructionAccess starts from 0x400, and after instruction "0xc0000434
> ><InstructionAccess+52>:      stw     r12,64(r11)", machine check occurs.
> >This instruction will store the value of r12, which is 0x0 at this
> >moment, to address 0x03072de0. I am puzzled why this action leads to
> >machine check. Is it illegal to store 0x0 in a memory address? Or is
> >there some other cause of the machine check here?
> 
> I have no idea if you're using physical or virtual addresses here, so
> there isn't much we can do to help you.

It is physical address at this moment. Address translation is disabled
automatically (MSR[IR, DR] = [0, 0]) because of TLB Miss Exception and
Instrunction Storage Exception.
> 
> Do you have enough DRAM to cover that?  Some of those boards only come
> with 32MiB of DRAM.

My board only has 32MB DRAM. Do you mean 32MB is not enough for that?
The same codes can run well in a PPC440EP (Yosemite Board) which owns
256MB DRAM. At the beginning of my work, I thought memory size may be
the cause of failure. But I did not know how to demonstrate it. So if
the limitation of 32MB DRAM leads to the failure, are there any methods
for the codes to solve it?

Thank you very much for your reply!

Best Wishes

Zhou Rui
2008-08-23

> 
> josh

__________________________________________________
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  reply	other threads:[~2008-08-23  8:05 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-08-22 18:27 Why does one "stw" fail with address translation disabled in PPC405EP? Zhou Rui
2008-08-22 18:42 ` Josh Boyer
2008-08-23  8:26   ` Zhou Rui [this message]
2008-08-23 22:49     ` Benjamin Herrenschmidt
2008-08-24 18:55     ` Wolfgang Denk
2008-08-25 19:16       ` Zhou Rui
2008-08-28 15:53         ` Zhou Rui
2008-08-31 11:50         ` [Evolves!] " Zhou Rui
2008-09-01  5:42           ` Benjamin Herrenschmidt
2008-09-01  7:22             ` Zhou Rui
2008-09-01  7:17               ` Benjamin Herrenschmidt
2008-09-01  8:19                 ` Zhou Rui
2008-08-23 21:18   ` Zhou Rui

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