From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 33E56DDE9E for ; Wed, 24 Sep 2008 20:19:56 +1000 (EST) Subject: Re: [PATCH HACK] powerpc: quick hack to get a functional eHEA with hardirq preemption From: Benjamin Herrenschmidt To: Milton Miller In-Reply-To: <200809240958.m8O9wM7k010996@sullivan.realtime.net> References: <200809231743.23828.ossthema@de.ibm.com> , <20080915100406.342e027a@bull.net> <200809240958.m8O9wM7k010996@sullivan.realtime.net> Content-Type: text/plain Date: Wed, 24 Sep 2008 20:17:47 +1000 Message-Id: <1222251467.8277.73.camel@pasglop> Mime-Version: 1.0 Cc: linux-kernel@vger.kernel.org, linuxppc-dev@ozlabs.org, Sebastien Dugue , Christoph Raisch , Paul Mackerras , Jan-Bernd Themann Reply-To: benh@kernel.crashing.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Wed, 2008-09-24 at 04:58 -0500, Milton Miller wrote: > The per-interrupt mask and unmask calls have to go through RTAS, a > single-threaded global context, which in addition to increasing > path length will really limit scalability. The interrupt controller > poll and reject facilities are accessed through hypervisor calls > which are comparable to a fast syscall, and parallel to all cpus. Note also that the XICS code thus assumes, iirc, as does the cell IIC code, that eoi is called on the -same- cpu that fetched the interrupt initially. That assumption can be broken with IRQ threads no ? Ben.