Add kexec support for fsl-book-e [V2]

Add kexec support for fsl-book-e [V2]

[Sebastian Andrzej Siewior]

This is the kernel part of the kexec support for mpc8544 / FSL BookE.
This version should fix the two things Ben noticed during his review.

Changelog:
 v1: - Removed runtime detection between fsl-book-e & no-mmu part
     - Marked the mmu-setup part as FSL BookE because it does not work
       on BooKE in general

Sebastian

[PATCH 1/2] powerpc: add kexec support on FSL-Book-E

[Sebastian Andrzej Siewior]

From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

The relocate_new_kernel() code usually disables the MMU and the small code
operates on physicall pages while moving the kernel to its final position.
Book-E doesn't support this so a 1:1 mapping must be created.
This patch adds support for FSL-BOOK-E implementation.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
 arch/powerpc/kernel/machine_kexec_32.c |    5 +-
 arch/powerpc/kernel/misc_32.S          |  129 ++++++++++++++++++++++++++++++-
 2 files changed, 127 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/kernel/machine_kexec_32.c b/arch/powerpc/kernel/machine_kexec_32.c
index ae63a96..6fa8ed3 100644
--- a/arch/powerpc/kernel/machine_kexec_32.c
+++ b/arch/powerpc/kernel/machine_kexec_32.c
@@ -16,10 +16,10 @@
 #include <asm/hw_irq.h>
 #include <asm/io.h>
 
-typedef NORET_TYPE void (*relocate_new_kernel_t)(
+typedef void (*relocate_new_kernel_t)(
 				unsigned long indirection_page,
 				unsigned long reboot_code_buffer,
-				unsigned long start_address) ATTRIB_NORET;
+				unsigned long start_address);
 
 /*
  * This is a generic machine_kexec function suitable at least for
@@ -57,6 +57,7 @@ void default_machine_kexec(struct kimage *image)
 	/* now call it */
 	rnk = (relocate_new_kernel_t) reboot_code_buffer;
 	(*rnk)(page_list, reboot_code_buffer_phys, image->start);
+	BUG();
 }
 
 int default_machine_kexec_prepare(struct kimage *image)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 7a6dfbc..68ab147 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -878,9 +878,120 @@ relocate_new_kernel:
 	/* r4 = reboot_code_buffer */
 	/* r5 = start_address      */
 
-	li	r0, 0
+	mflr	r28
+	mr	r29, r3
+	mr	r30, r4
+	mr	r31, r5
+
+#ifdef CONFIG_FSL_BOOKE
+
+	li	r25, 0			/* phys kernel start (low) */
+
+/* 1. Find the index of the entry we're executing in */
+	bl	invstr			/* Find our address */
+invstr:
+	mflr	r6			/* Make it accessible */
+	mfmsr	r7
+	rlwinm	r4,r7,27,31,31		/* extract MSR[IS] */
+	mfspr	r7, SPRN_PID0
+	slwi	r7,r7,16
+	or	r7,r7,r4
+	mtspr	SPRN_MAS6,r7
+	tlbsx	0,r6			/* search MSR[IS], SPID=PID0 */
+	mfspr	r7,SPRN_MAS1
+	andis.	r7,r7,MAS1_VALID@h
+	bne	match_TLB
 
 	/*
+	 * We search just in PID0 because kernel's global mapping has to be
+	 * there. We simply return to the caller if we didn't find the mapping
+	 * since we didn't (yet) pass the point of no return. This should not
+	 * happen.
+	 */
+	mtlr	r28
+	blr
+
+match_TLB:
+	mfspr	r7,SPRN_MAS0
+	rlwinm	r3,r7,16,20,31		/* Extract MAS0(Entry) */
+
+	mfspr	r7,SPRN_MAS1		/* Insure IPROT set */
+	oris	r7,r7,MAS1_IPROT@h
+	mtspr	SPRN_MAS1,r7
+	tlbwe
+
+/* 2. Invalidate all entries except the entry we're executing in */
+	mfspr	r9,SPRN_TLB1CFG
+	andi.	r9,r9,0xfff
+	li	r6,0			/* Set Entry counter to 0 */
+1:
+	lis	r7,0x1000		/* Set MAS0(TLBSEL) = 1 */
+	rlwimi	r7,r6,16,4,15		/* Setup MAS0 = TLBSEL | ESEL(r6) */
+	mtspr   SPRN_MAS0,r7
+	tlbre
+	mfspr	r7,SPRN_MAS1
+	rlwinm  r7,r7,0,2,31		/* Clear MAS1 Valid and IPROT */
+	cmpw	r3,r6
+	beq	skpinv			/* Dont update the current execution TLB */
+	mtspr	SPRN_MAS1,r7
+	tlbwe
+	isync
+skpinv:
+	addi	r6,r6,1			/* Increment */
+	cmpw	r6,r9			/* Are we done? */
+	bne	1b			/* If not, repeat */
+
+	/* Invalidate TLB0 */
+	li	r6,0x04
+	tlbivax	0,r6
+	TLBSYNC
+	/* Invalidate TLB1 */
+	li	r6,0x0c
+	tlbivax	0,r6
+	TLBSYNC
+
+/* 3. Setup a temp mapping and jump to it */
+	andi.	r5, r3, 0x1		/* Find an entry not used and is non-zero */
+	addi	r5, r5, 0x1
+	lis	r7, 0x1000		/* Set MAS0(TLBSEL) = 1 */
+	rlwimi	r7, r3, 16, 4, 15	/* Setup MAS0 = TLBSEL | ESEL(r3) */
+	mtspr	SPRN_MAS0,r7
+	tlbre
+
+	/* Just modify the entry ID and EPN for the temp mapping */
+	lis	r7,0x1000		/* Set MAS0(TLBSEL) = 1 */
+	rlwimi	r7,r5,16,4,15		/* Setup MAS0 = TLBSEL | ESEL(r5) */
+	mtspr	SPRN_MAS0,r7
+
+	xori	r6,r4,1			/* Setup TMP mapping in the other Address space */
+	slwi	r6,r6,12
+	oris	r6,r6,(MAS1_VALID|MAS1_IPROT)@h
+	ori	r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_1GB))@l
+	mtspr	SPRN_MAS1,r6
+
+	lis	r7, MAS2_I | MAS2_G
+	mtspr	SPRN_MAS2,r7
+
+	li	r8, 0
+	ori	r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
+	mtspr   SPRN_MAS3,r8
+
+	tlbwe
+
+	xori	r6, r4, 1
+	slwi	r5, r6, 4		/* DS setup new context with other address space */
+	slwi	r6, r6, 5		/* IS setup new context with other address space */
+	or	r6, r6, r5
+
+	/* find our address */
+	addi	r7, r30, final_copy_code - relocate_new_kernel
+
+	mtspr	SPRN_SRR0,r7
+	mtspr	SPRN_SRR1,r6
+	rfi
+#else
+	li	r0, 0
+	/*
 	 * Set Machine Status Register to a known status,
 	 * switch the MMU off and jump to 1: in a single step.
 	 */
@@ -888,14 +999,22 @@ relocate_new_kernel:
 	mr	r8, r0
 	ori     r8, r8, MSR_RI|MSR_ME
 	mtspr	SPRN_SRR1, r8
-	addi	r8, r4, 1f - relocate_new_kernel
+	addi	r8, r4, final_copy_code - relocate_new_kernel
 	mtspr	SPRN_SRR0, r8
 	sync
 	rfi
+#endif
 
-1:
-	/* from this point address translation is turned off */
-	/* and interrupts are disabled */
+final_copy_code:
+
+	mr	r3, r29
+	mr	r4, r30
+	mr	r5, r31
+
+	li	r0, 0
+
+	/* from this point address translation is turned off or we have  */
+	/* a 1:1 mapping and interrupts are disabled */
 
 	/* set a new stack at the bottom of our page... */
 	/* (not really needed now) */
-- 
1.5.6.5

[PATCH 2/2] powerpc: enable kexec support on mpc8544ds

[Sebastian Andrzej Siewior]

From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
 arch/powerpc/Kconfig                     |    2 +-
 arch/powerpc/platforms/85xx/mpc85xx_ds.c |    6 ++++++
 2 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 587da5e..c2c6a20 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -304,7 +304,7 @@ config ARCH_ENABLE_MEMORY_HOTREMOVE
 
 config KEXEC
 	bool "kexec system call (EXPERIMENTAL)"
-	depends on (PPC_PRPMC2800 || PPC_MULTIPLATFORM) && EXPERIMENTAL
+	depends on (PPC_PRPMC2800 || PPC_MULTIPLATFORM || MPC85xx_DS) && EXPERIMENTAL
 	help
 	  kexec is a system call that implements the ability to shutdown your
 	  current kernel, and to start another kernel.  It is like a reboot
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 3d5f21b..ae573e8 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -30,6 +30,7 @@
 #include <asm/udbg.h>
 #include <asm/mpic.h>
 #include <asm/i8259.h>
+#include <linux/kexec.h>
 
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
@@ -227,6 +228,11 @@ define_machine(mpc8544_ds) {
 	.restart		= fsl_rstcr_restart,
 	.calibrate_decr		= generic_calibrate_decr,
 	.progress		= udbg_progress,
+#ifdef CONFIG_KEXEC
+	.machine_kexec          = default_machine_kexec,
+	.machine_kexec_prepare  = default_machine_kexec_prepare,
+	.machine_crash_shutdown = default_machine_crash_shutdown,
+#endif
 };
 
 define_machine(mpc8572_ds) {
-- 
1.5.6.5

Re: [PATCH 1/2] powerpc: add kexec support on FSL-Book-E

[Sebastian Andrzej Siewior]

wilbur.chan wrote:
> Hi  Sebastian,
Hi Wilbur,

> Recently I've implemented  non-SMP kexec on MPC8572 and P2020ds(2G ram).
> 
> 
> 
> I modified your
> 
> misc_32.S that , I setuped  two '1G' entries  after the "rfi"
> instruction, so that I did
> not  need to setup  mapping for instruction address.
If you send some patches I could add them to my tree so we have
everything together.

> As for SMP supporting,I tried to close one of the CPUs in
> default_machine_kexec,
> 
> and found that , when cpu1  closed  ,and if the second kernel is NON-
> 
> SMP,everything went well.so I added some code in
> 
> kexec-tools, to make sure the 'kexec' process was running on CPU 0.
I remember that ppc64 had some code to suspend and start the second CPU in
the purgatory code. Not sure if there is a generic way for this on ppc32
or it is a book-e thing. Haven't look at it (yet).

> So, there left one problem, I can not start the second SMP-kernel,
> even if I  closed
> 
> CPU1.  Any suggestions?
The interesting thing is where do you hang/crash. It could be possible
that the kernel is waiting for the non-boot cpus to show up and it
doesn't. Have you look how u-boot prepares the cpus and how kernel
disables them on shutdown?


> PTW:
> 
> no-smp ---> no-smp.........OK
> no-smp --->smp...............OK
Does this mean your smp kernel has more that one CPU or just one?

> smp(with cpu1 closed)---->no-smp..............OK
> smpw(with cpu1 closed)---->smp ................FAILED
> 
> 
> regards,
> 
> wilbur

Sebastian

Re: [PATCH 1/2] powerpc: add kexec support on FSL-Book-E

[wilbur.chan]

2009/8/29, Sebastian Andrzej Siewior <bigeasy@linutronix.de>:

> If you send some patches I could add them to my tree so we have
> everything together.

Hmmm..I don't know how to make a patch like yours.. So , I just
manually  list my

codes below which are added to  machine_kexec_32.c and misc_32.S respectively.




1) machine_kexec_32.c (only test on MPC8572, MPC8541 , P2020DS, so I

used macro here, the param of image->segment[image->nr_segments - 1].mem

is the dtb address)

//default_machine_kexec

+ #if defined(CONFIG_MPC8572_PC) || defined(CONFIG_P2020) ||
defined(CONFIG_MPC8560_ADS)
+ (*rnk)(page_list, reboot_code_buffer, image->start,
image->segment[image->nr_segments - 1].mem);
 +#else
 rnk = (relocate_new_kernel_t) reboot_code_buffer;
	(*rnk)(page_list, reboot_code_buffer_phys, image->start);
 +#endif



2) misc_32.S:


 define macro to setup mapping:


+#define FSL_BOOKE_MAS0(tlbsel,esel,nv) \
+ (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))

+#define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \
 + ((((v) << 31) & MAS1_VALID)             |\
  +(((iprot) << 30) & MAS1_IPROT)          |\
 + (MAS1_TID(tid))    |\
  +(((ts) << 12) & MAS1_TS)                |\
 + (MAS1_TSIZE(tsize)))


+#define FSL_BOOKE_MAS2(epn, wimge) \
  +(((epn) & MAS3_RPN) | (wimge))

+#define FSL_BOOKE_MAS3(rpn, user, perms) \
 + (((rpn) & MAS3_RPN) | (user) | (perms))




+ #ifdef CONFIG_E500

/* 1. Find the index of the entry we're executing in */
 bl invstr   /* Find our address */
 invstr:
 mflr r6   /* Make it accessible */
 mfmsr r7
 rlwinm r4,r7,27,31,31  /* extract MSR[IS] */
 mfspr r7, SPRN_PID0
 slwi r7,r7,16
 or r7,r7,r4
 mtspr SPRN_MAS6,r7
 tlbsx 0,r6   /* search MSR[IS], SPID=PID0 */
 mfspr r7,SPRN_MAS1
 andis. r7,r7,MAS1_VALID@h
 bne match_TLB

 /*
  * We search just in PID0 because kernel's global mapping has to be
  * there. We simply return to the caller if we didn't find the mapping
  * since we didn't (yet) pass the point of no return. This should not
  * happen.
  */
 mtlr r28
 blr

match_TLB:
 mfspr r7,SPRN_MAS0
 rlwinm r3,r7,16,20,31  /* Extract MAS0(Entry) */

 mfspr r7,SPRN_MAS1  /* Insure IPROT set */
 oris r7,r7,MAS1_IPROT@h
 mtspr SPRN_MAS1,r7
 tlbwe

/* 2. Invalidate all entries except the entry we're executing in */
 mfspr r9,SPRN_TLB1CFG
 andi. r9,r9,0xfff
 li r6,0   /* Set Entry counter to 0 */
1:
 lis r7,0x1000  /* Set MAS0(TLBSEL) = 1 */
 rlwimi r7,r6,16,4,15  /* Setup MAS0 = TLBSEL | ESEL(r6) */
 mtspr   SPRN_MAS0,r7
 tlbre
 mfspr r7,SPRN_MAS1
 rlwinm  r7,r7,0,2,31  /* Clear MAS1 Valid and IPROT */
 cmpw r3,r6
 beq skpinv   /* Dont update the current execution TLB */
 mtspr SPRN_MAS1,r7
 tlbwe
 isync
skpinv:
 addi r6,r6,1   /* Increment */
 cmpw r6,r9   /* Are we done? */
 bne 1b   /* If not, repeat */

 /* Invalidate TLB0 */
 li r6,0x04
 tlbivax 0,r6
 TLBSYNC
 /* Invalidate TLB1 */
 li r6,0x0c
 tlbivax 0,r6
 TLBSYNC


+#ifdef  CONFIG_MPC8572_PC || CONFIG_P2020
+ lis     r6,FSL_BOOKE_MAS0(1, 13, 0)@h
+ ori     r6,r6,FSL_BOOKE_MAS0(1, 13, 0)@l

 +lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1GB)@h
 +ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1GB)@l

+ lis     r8,FSL_BOOKE_MAS2(0x00000000, (MAS2_I|MAS2_G))@h
 +ori     r8,r8,FSL_BOOKE_MAS2(0x00000000, (MAS2_I|MAS2_G))@l

+ lis     r9,FSL_BOOKE_MAS3(0x00000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+ ori     r9,r9,FSL_BOOKE_MAS3(0x00000000, 0,  (MAS3_SX|MAS3_SW|MAS3_SR))@l

 +mtspr   SPRN_MAS0,r6
+ mtspr   SPRN_MAS1,r7
 +mtspr   SPRN_MAS2,r8
 +mtspr   SPRN_MAS3,r9
+ isync
+ msync
 +tlbwe

+ lis     r6,FSL_BOOKE_MAS0(1, 12, 0)@h
+ ori     r6,r6,FSL_BOOKE_MAS0(1, 12, 0)@l

 +lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1GB)@h
 +ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1GB)@l

 +lis     r8,FSL_BOOKE_MAS2(0x40000000, (MAS2_I|MAS2_G))@h
 +ori     r8,r8,FSL_BOOKE_MAS2(0x40000000, (MAS2_I|MAS2_G))@l

 +lis     r9,FSL_BOOKE_MAS3(0x40000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
 +ori     r9,r9,FSL_BOOKE_MAS3(0x40000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l

 +mtspr   SPRN_MAS0,r6
+ mtspr   SPRN_MAS1,r7
+ mtspr   SPRN_MAS2,r8
 +mtspr   SPRN_MAS3,r9
 +isync
 +msync
+ tlbwe

+#endif

+#ifdef  CONFIG_MPC8560_ADS
+ lis     r6,FSL_BOOKE_MAS0(1, 13, 0)@h
 +ori     r6,r6,FSL_BOOKE_MAS0(1, 13, 0)@l

+ lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)@h
+ ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)@l

 +lis     r8,FSL_BOOKE_MAS2(0x00000000, (MAS2_I|MAS2_G))@h
 +ori     r8,r8,FSL_BOOKE_MAS2(0x00000000, (MAS2_I|MAS2_G))@l

+ lis     r9,FSL_BOOKE_MAS3(0x00000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
 +ori     r9,r9,FSL_BOOKE_MAS3(0x00000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l

 +mtspr   SPRN_MAS0,r6
 +mtspr   SPRN_MAS1,r7
+ mtspr   SPRN_MAS2,r8
 +mtspr   SPRN_MAS3,r9
 +isync
+ msync
 +tlbwe

+ lis     r6,FSL_BOOKE_MAS0(1, 12, 0)@h
 +ori     r6,r6,FSL_BOOKE_MAS0(1, 12, 0)@l

 +lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)@h
 +ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)@l

+ lis     r8,FSL_BOOKE_MAS2(0x10000000, (MAS2_I|MAS2_G))@h
+ ori     r8,r8,FSL_BOOKE_MAS2(0x10000000, (MAS2_I|MAS2_G))@l

 +lis     r9,FSL_BOOKE_MAS3(0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
 +ori     r9,r9,FSL_BOOKE_MAS3(0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l

+ mtspr   SPRN_MAS0,r6
 +mtspr   SPRN_MAS1,r7
 +mtspr   SPRN_MAS2,r8
 +mtspr   SPRN_MAS3,r9
 +isync
 +msync
 +tlbwe


 +lis     r6,FSL_BOOKE_MAS0(1, 11, 0)@h
+ ori     r6,r6,FSL_BOOKE_MAS0(1, 11, 0)@l

+ lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)@h
 +ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)@l

+ lis     r8,FSL_BOOKE_MAS2(0x20000000, (MAS2_I|MAS2_G))@h
+ ori     r8,r8,FSL_BOOKE_MAS2(0x20000000, (MAS2_I|MAS2_G))@l

+ lis     r9,FSL_BOOKE_MAS3(0x20000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
 +ori     r9,r9,FSL_BOOKE_MAS3(0x20000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l

 +mtspr   SPRN_MAS0,r6
+ mtspr   SPRN_MAS1,r7
+ mtspr   SPRN_MAS2,r8
+ mtspr   SPRN_MAS3,r9
 +isync
+ msync
+ tlbwe

+ lis     r6,FSL_BOOKE_MAS0(1, 10, 0)@h
 +ori     r6,r6,FSL_BOOKE_MAS0(1, 10, 0)@l

 +lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)@h
 +ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)@l

+ lis     r8,FSL_BOOKE_MAS2(0x30000000, (MAS2_I|MAS2_G))@h
 +ori     r8,r8,FSL_BOOKE_MAS2(0x30000000, (MAS2_I|MAS2_G))@l

 +lis     r9,FSL_BOOKE_MAS3(0x30000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
 +ori     r9,r9,FSL_BOOKE_MAS3(0x30000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l

+ mtspr   SPRN_MAS0,r6
 +mtspr   SPRN_MAS1,r7
 +mtspr   SPRN_MAS2,r8
+ mtspr   SPRN_MAS3,r9
 +isync
 +msync
 +tlbwe
+#endif

+#endif

 mr r3, r29
 mr r5, r31