From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4CE11DDD0B for ; Mon, 1 Dec 2008 19:11:40 +1100 (EST) Subject: Re: AMCC PPC460EX Canyonlands does not see PCIe end point with only non-prefetchable memory (both 2.6.27.7 and -next) From: Benjamin Herrenschmidt To: Leon Woestenberg In-Reply-To: References: Content-Type: text/plain Date: Mon, 01 Dec 2008 19:11:32 +1100 Message-Id: <1228119092.7356.117.camel@pasglop> Mime-Version: 1.0 Cc: linux-pci@vger.kernel.org, linuxppc-dev@ozlabs.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Fri, 2008-11-28 at 11:54 +0100, Leon Woestenberg wrote: > > I found out that re-programming the end point FPGA again *just* after > *uboot* read it, and before Linux kernel has started, makes the end > point appear properly. > > Either u-boot leaves the end point in bad state, or the root complex > reset also requires an end point reset. (or a third option I could not > think of yet). I think you are getting a reset yes, maybe your FPGA loses its programming or something similar ? > I'll pick this up on ppc and u-boot mailing list with new info, > especially with the ppc4xx maintainers. > CC me, Ben.