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Subject: Re: [PATCH] powerpc: Fix bogus cache flushing on all 40x and BookE
	processors
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Trent Piepho <tpiepho@freescale.com>
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Date: Thu, 04 Dec 2008 11:06:07 +1100
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On Wed, 2008-12-03 at 15:09 -0800, Trent Piepho wrote:

> #ifdef __powerpc64__
> #define LONG_ASM_CONST(x)               ASM_CONST(x)
> #else
> #define LONG_ASM_CONST(x)               0
> #endif
> 
> #define CPU_FTR_NOEXECUTE               LONG_ASM_CONST(0x0000000800000000)
> 
> Am I not looking at the right code?  Since e200 and e500 aren't powerpc64,
> doesn't adding CPU_FTR_NOEXECUTE have no effect at all?

No, you are right, this is a case where I didn't actually verify that
the patch had the expected effect :-(

We are running out of low FTR bits, heck, I might make them 64-bit
for everybody soon.

I'll fix that up, thanks for spotting it.

Cheers,
Ben.