From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9B1E7DDFF7 for ; Mon, 12 Jan 2009 16:17:10 +1100 (EST) Subject: Re: [PATCH 1/5] powerpc: Add platform support for AmigaOne From: Benjamin Herrenschmidt To: Scott Wood In-Reply-To: <20090107190718.GA17427@ld0162-tx32.am.freescale.net> References: <20090107135457.234150@gmx.net> <20090107190718.GA17427@ld0162-tx32.am.freescale.net> Content-Type: text/plain Date: Mon, 12 Jan 2009 16:08:07 +1100 Message-Id: <1231736887.22571.18.camel@pasglop> Mime-Version: 1.0 Cc: linuxppc-dev@ozlabs.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , > > + /* Flush and disable I/D cache. */ > > + __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); > > + __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); > > + __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); > > + __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); > > Don't do this; instead, have one multi-line asm statement (or better yet, > just use mfspr()/mtspr()/sync()/isync()). > > GCC is perfectly free to trash your registers in between statements. Also there's already some code around to properly flush & disable the caches on those processors. Ben.