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Subject: RE: Broken PCI on Sequoia
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Feng Kan <fkan@amcc.com>
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Date: Sat, 31 Jan 2009 15:42:33 +1100
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Cc: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>,
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On Fri, 2009-01-30 at 17:19 -0800, Feng Kan wrote:
> Hi:
>    It looks like the top bit is hard coded to 1. There doesn't seem to
> be anyway
> Of changing it. 

Thanks !

Would it be possible for you to check other 4xx parts using that PCI
controller as to whether the top bit is always hard-coded to 1 or it
changes from part to part ?

Thanks !

Cheers,
Ben.

> Feng Kan
> AMCC Engineering
> 
> -----Original Message-----
> From: linuxppc-dev-bounces+fkan=amcc.com@ozlabs.org
> [mailto:linuxppc-dev-bounces+fkan=amcc.com@ozlabs.org] On Behalf Of
> Benjamin Herrenschmidt
> Sent: Friday, January 30, 2009 1:30 PM
> To: Geert Uytterhoeven
> Cc: Linux/PPC Development
> Subject: Re: Broken PCI on Sequoia
> 
> 
> > For that sort of 4xx PHB (ie, the PCI 2.x ones, not the PCI-X nor the
> > PCI-E), we only know how to program 32-bit of PLB address. IE. The old
> > code would have cropped the plb_addr when writing to the register, the
> > new code complains.
> > 
> > I suspect some implementation support a register to put the "high"
> part
> > of the PLB address, and that it already contains 1, so the old code
> > would have worked by chance, the new code doesn't because it bails
> out.
> 
> Hrm... from the doco it's also one 32-bit register... I'm starting to
> think that those guys always assume the top 1 bit is set or something
> like that ...
> 
> The doc is unclear. Maybe somebody form AMCC can confirm ?
> 
> Cheers,
> Ben.
> 
> 
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