From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Kumar Gala <galak@kernel.crashing.org>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: [PATCH v2] powerpc: Add support for CoreInt delivery of interrupts on MPIC
Date: Sat, 21 Mar 2009 09:08:26 +1100 [thread overview]
Message-ID: <1237586906.25062.610.camel@pasglop> (raw)
In-Reply-To: <051D5D14-4CD9-4138-879A-23DA2B02AB7F@kernel.crashing.org>
On Fri, 2009-03-20 at 06:47 -0500, Kumar Gala wrote:
> On Mar 20, 2009, at 12:48 AM, Benjamin Herrenschmidt wrote:
>
> > On Wed, 2009-03-11 at 10:18 -0500, Kumar Gala wrote:
> >> CoreInt provides a mechansim to deliver the IRQ vector directly
> >> into the core on an interrupt (via the SPR EPR) rather than having
> >> to go IACK on the PIC. This is suppose to provide an improvment
> >> in interrupt latency by reducing the time to get the IRQ vector.
> >>
> >> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> >> ---
> >> * Fixed MPIC_GREG_GCONF_COREINT flag to be 0x60000000 as per spec
> >> and pointed about by Dave
> >
> > Are you sure ? That's 2 bits ...
>
> Yeah. We expanded the mode field to two bits (mask would be 0x60000000)
>
> 0x00 = pass through (interrupts routed to IRQ0)
> 0x01 = Mixed mode
> 0x10 = reserved
> 0x11 = External proxy / coreint
Ah ok, that's a bit funny but should do. Maybe worth a comment though.
Cheers,
Ben.
prev parent reply other threads:[~2009-03-20 22:08 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-03-11 15:18 [PATCH v2] powerpc: Add support for CoreInt delivery of interrupts on MPIC Kumar Gala
2009-03-20 5:48 ` Benjamin Herrenschmidt
2009-03-20 11:47 ` Kumar Gala
2009-03-20 22:08 ` Benjamin Herrenschmidt [this message]
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