From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 03376DE0E2 for ; Fri, 17 Apr 2009 18:33:09 +1000 (EST) Subject: Re: pci32 code - early_*config* From: Benjamin Herrenschmidt To: Roderick Colenbrander In-Reply-To: References: <8393884A-D1B0-4081-980C-CF464A38FD6C@kernel.crashing.org> <1239953159.7443.33.camel@pasglop> Content-Type: text/plain Date: Fri, 17 Apr 2009 10:33:02 +0200 Message-Id: <1239957182.7443.58.camel@pasglop> Mime-Version: 1.0 Cc: Linuxppc-dev Development List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Fri, 2009-04-17 at 10:03 +0200, Roderick Colenbrander wrote: > > There are cases when it is really needed (or you would have to access > the address and data bus by hand). In my case I'm using a Xilinx PLB > soft-core and if certain options in the configuration header aren't > set (which aren't set by default) the soft-core is basically disabled. > Cases like this look like valid cases in which early config should be > used. I still wonder whether we could just setup the pci_controller data structure and use "normal" PCI config access routines... Cheers, Ben.