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Subject: Re: [RFC][PATCH v5] MPC5121 TLB errata workaround
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Wolfgang Denk <wd@denx.de>
In-Reply-To: <20090606220723.A38DA832E416@gemini.denx.de>
References: <200903161652.09747.david.jander@protonic.nl>
	<20090606220723.A38DA832E416@gemini.denx.de>
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Date: Sun, 07 Jun 2009 08:42:04 +1000
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Cc: linuxppc-dev@ozlabs.org, David Jander <david.jander@protonic.nl>,
	gunnar@genesi-usa.com, Paul Mackerras <paulus@samba.org>
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On Sun, 2009-06-07 at 00:07 +0200, Wolfgang Denk wrote:
> Dear David Jander,
> 
> In message <200903161652.09747.david.jander@protonic.nl> you wrote:
> > Complete workaround for DTLB errata in e300c2/c3/c4 processors.
> > 
> > Due to the bug, the hardware-implemented LRU algorythm always goes to way
> > 1 of the TLB. This fix implements the proposed software workaround in
> > form of a LRW table for chosing the TLB-way.
> > 
> > Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> > Signed-off-by: David Jander <david@protonic.nl>
> 
> What is the actual status of this patch?
> 
> Patchwork (http://patchwork.ozlabs.org/patch/24502/) says it's
> "superseded" - but by what?
> 
> I can't see such code in mainline - what happened to it?

I can see the code in mainline ... but only in the -data- TLB miss
handler, not the instruction one...

Kumar ? Shouldn't we have the workaround in both ?

Cheers,
Ben.