Re: PPC PCI bus registers

[Benjamin Herrenschmidt <benh@kernel.crashing.org>]

On Wed, 2009-09-02 at 16:44 -0700, Eddie Dawydiuk wrote:
> Hello,
> 
> I have a question regarding reading PCI bus registers from a user space 
> application running on a PPC SBC. Seeing as though the PCI bus is little endian 
> and PPC is big endian is it typical that one must perform a byte swap on all 16 
> and 32 bit register reads?
> 
> I've found this is true on a custom board I am working on(with an FPGA connected 
> via the PCI bus) and as a result I've added a byte swap command in busybox to 
> accommodate this feature...

Note that powerpc has efficient load/store reverse instructions that
perform the byteswap for you. We use them for IOs in the kernel for
example.

Also, if you're going to access a PCI device directly, beware of other
issues such as ordering. PPC is an out of order architecture, you need
to ensure you add the appropriate memory barriers if you want to ensure
you accesses are done in the order you write them in your program.

For "standard" stuff that doesn't involve DMA or locks, an eieio after
both MMIO loads and stores should do the trick.

If you need to order vs. DMA and/or locks, you may want to look at what
the kernel does in io.h

Cheers,
Ben.