From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Cc: Scott Wood <scottwood@freescale.com>,
"linuxppc-dev@ozlabs.org" <linuxppc-dev@ozlabs.org>,
Rex Feany <RFeany@mrv.com>
Subject: Re: [PATCH 2/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU.
Date: Thu, 08 Oct 2009 08:14:52 +1100 [thread overview]
Message-ID: <1254950092.2409.7.camel@pasglop> (raw)
In-Reply-To: <1254948364-30074-3-git-send-email-Joakim.Tjernlund@transmode.se>
On Wed, 2009-10-07 at 22:46 +0200, Joakim Tjernlund wrote:
> + andi. r11, r10, _PAGE_USER | _PAGE_ACCESSED
> + cmpwi cr0, r11, _PAGE_USER | _PAGE_ACCESSED
> + bne- cr0, 2f
Did you mean _PAGE_PRESENT | _PAGE_ACCESSED ?
> +2:
> + mfspr r11, SRR1
> + rlwinm r11, r11, 0, 5, 3 /* clear guarded */
> + mtspr SRR1, r11
What is the above for ?
> + mfspr r10, SPRN_M_TW /* Restore registers */
> + lwz r11, 0(r0)
> + mtcr r11
> + lwz r11, 4(r0)
> +#ifdef CONFIG_8xx_CPU6
> + lwz r3, 8(r0)
> +#endif
> + b InstructionAccess
>
.../...
> + andi. r11, r10, _PAGE_ACCESSED
> + bne+ cr0, 5f /* branch if access allowed */
> + rlwinm r10, r10, 0, 21, 19 /* Clear _PAGE_USER */
> + ori r10, r10, _PAGE_RW /* Set RW bit for xor below to clear it */
> +5: xori r10, r10, _PAGE_RW /* invert RW bit */
Why are you clearing _PAGE_USER ? One needs to differenciate usr
from kernel pages or user will be access to write to kernel...
Why don't you do the trick I proposed in my email with loading a
constant that contains all the bit combinations and shifting it
by the amount defined by _PAGE_RW and _PAGE_USER used as a two
bits index ?
> /* The Linux PTE won't go exactly into the MMU TLB.
> - * Software indicator bits 21, 22 and 28 must be clear.
> + * Software indicator bits 22 and 28 must be clear.
> * Software indicator bits 24, 25, 26, and 27 must be
> * set. All other Linux PTE bits control the behavior
> * of the MMU.
> @@ -472,8 +470,8 @@ DataTLBError:
> /* First, make sure this was a store operation.
> */
> mfspr r10, SPRN_DSISR
> - andis. r11, r10, 0x4800 /* no translation, no permission. */
> - bne 2f /* branch if either is set */
> + andis. r11, r10, 0x4000 /* no translation */
> + bne 2f /* branch if set */
>
> /* The EA of a data TLB miss is automatically stored in the MD_EPN
> * register. The EA of a data TLB error is automatically stored in
> @@ -522,26 +520,20 @@ DataTLBError:
> mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
> lwz r10, 0(r11) /* Get the pte */
>
> - andi. r11, r10, _PAGE_RW /* Is it writeable? */
> - beq 2f /* Bail out if not */
> -
> - /* Update 'changed', among others.
> - */
> -#ifdef CONFIG_SWAP
> + mfspr r11, DSISR
> + andis. r11, r11, 0x0200 /* store */
> + beq 5f
> + andi. r11, r10, _PAGE_RW /* writeable? */
> + beq 2f /* nope */
> ori r10, r10, _PAGE_DIRTY|_PAGE_HWWRITE
> - /* do not set the _PAGE_ACCESSED bit of a non-present page */
> - andi. r11, r10, _PAGE_PRESENT
> - beq 4f
> - ori r10, r10, _PAGE_ACCESSED
> -4:
> -#else
> - ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
> -#endif
> - mfspr r11, SPRN_MD_TWC /* Get pte address again */
> +5: ori r10, r10, _PAGE_ACCESSED
> + mfspr r11, MD_TWC /* Get pte address again */
> stw r10, 0(r11) /* and update pte in table */
>
> + xori r10, r10, _PAGE_RW /* RW bit is inverted */
> +
> /* The Linux PTE won't go exactly into the MMU TLB.
> - * Software indicator bits 21, 22 and 28 must be clear.
> + * Software indicator bits 22 and 28 must be clear.
> * Software indicator bits 24, 25, 26, and 27 must be
> * set. All other Linux PTE bits control the behavior
> * of the MMU.
I still don't find how any of the above is useful... why not just go
straight to C code ?
Cheers,
Ben.
next prev parent reply other threads:[~2009-10-07 21:15 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-10-07 20:45 [PATCH 0/6] 8xx TLB fixes Joakim Tjernlund
2009-10-07 20:45 ` [PATCH 1/6] 8xx: DTLB Error must check for more errors Joakim Tjernlund
2009-10-07 20:46 ` [PATCH 2/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU Joakim Tjernlund
2009-10-07 20:46 ` [PATCH 3/6] 8xx: invalidate non present TLBs Joakim Tjernlund
2009-10-07 20:46 ` [PATCH 4/6] 8xx: Tag DAR with 0x00f0 to catch buggy instructions Joakim Tjernlund
2009-10-07 20:46 ` [PATCH 5/6] 8xx: Fixup DAR from buggy dcbX instructions Joakim Tjernlund
2009-10-07 20:46 ` [PATCH 6/6] 8xx: start using dcbX instructions in various copy routines Joakim Tjernlund
2009-10-07 21:18 ` [PATCH 4/6] 8xx: Tag DAR with 0x00f0 to catch buggy instructions Benjamin Herrenschmidt
2009-10-07 22:13 ` Joakim Tjernlund
2009-10-07 22:21 ` Benjamin Herrenschmidt
2009-10-07 23:12 ` Joakim Tjernlund
2009-10-07 21:18 ` [PATCH 3/6] 8xx: invalidate non present TLBs Benjamin Herrenschmidt
2009-10-07 22:12 ` Joakim Tjernlund
2009-10-07 22:20 ` Benjamin Herrenschmidt
2009-10-08 19:22 ` Joakim Tjernlund
2009-10-08 20:11 ` Dan Malek
2009-10-08 20:18 ` Benjamin Herrenschmidt
2009-10-08 20:28 ` Benjamin Herrenschmidt
2009-10-08 22:08 ` Dan Malek
2009-10-08 22:23 ` Benjamin Herrenschmidt
2009-10-08 23:01 ` Joakim Tjernlund
2009-10-09 0:56 ` Benjamin Herrenschmidt
2009-10-09 0:36 ` Dan Malek
2009-10-09 0:57 ` Benjamin Herrenschmidt
2009-10-08 20:37 ` Joakim Tjernlund
2009-10-08 20:44 ` Benjamin Herrenschmidt
2009-10-09 0:05 ` Dan Malek
2009-10-08 20:42 ` Benjamin Herrenschmidt
2009-10-07 21:14 ` Benjamin Herrenschmidt [this message]
2009-10-07 22:08 ` [PATCH 2/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU Joakim Tjernlund
2009-10-07 22:20 ` Benjamin Herrenschmidt
2009-10-07 23:11 ` Joakim Tjernlund
2009-10-08 0:04 ` Benjamin Herrenschmidt
2009-10-08 0:19 ` Joakim Tjernlund
2009-10-08 0:28 ` Benjamin Herrenschmidt
2009-10-08 6:45 ` Joakim Tjernlund
2009-10-08 20:21 ` Benjamin Herrenschmidt
[not found] ` <OFCA7943E6.AFEF924A-ONC1257648.007E27B0-C1257648.007F62E9@LocalDomain>
2009-10-07 23:34 ` Joakim Tjernlund
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