Re: Regarding FPGA based cascaded PIC

Re: Regarding FPGA based cascaded PIC

[Thirumalai]

----- Original Message ----- 
From: "Benjamin Herrenschmidt" <benh@kernel.crashing.org>
To: "Thirumalai" <thirumalai.p@datapatterns.co.in>
Cc: <scottwood@freescale.com>
Sent: Wednesday, November 04, 2009 11:55 AM
Subject: Re: Regarding FPGA based cascaded PIC


> On Wed, 2009-11-04 at 10:48 +0530, Thirumalai wrote:
>> Hi Ben,
>>         I am a having MPC8640D based board on which i am in the process 
>> of
>> writing cascaded interrupt handler for my FPGA based PIC. I need some
>> clarification on writing customized cascaded interrupt handler. As for as 
>> my
>> understanding we need to use  irq_alloc_host() function for allocating 
>> the
>> irq_host for my FPGA pic and we should use irq_of_parse_and_map() 
>> function
>> for parsing and assignment of virtual IRQ from my device tree. In my case 
>> my
>> FPGA based PIC is giving interrupts to 3 external interrupt of MPC8640D 
>> i.e
>> 1,2,3 . So i have written my fpga-pic node as follows on my device tree.
>
> Please post to the mailing list linuxppc-dev@lists.ozlabs.org for such
> questions.
>
>> fpga-pic@dc000000 {
>>                         compatible = "dp,fpga-pic";
>>                         reg = <0xdc000000 0x7fff>;
>>                         interrupt-controller;
>>                         #interrupt-cells = <3>;
>>                         interrupts = <1 1 2 1 3 1>;
>>                         interrupt-parent = <&mpic>;
>> };
>
> 3 cells per interrupt ? that's a lot :-) What do you put in there ?
>
>>  mpic: pic@40000 {
>>                         clock-frequency = <0>;
>>                         interrupt-controller;
>>                         #address-cells = <0>;
>>                         #interrupt-cells = <2>;
>>                         reg = <0x40000 0x40000>;
>>                         compatible = "chrp,open-pic";
>>                         device_type = "open-pic";
>>                         big-endian;
>>                 };
>
> So far it looks reasonable...
>
>> The function irq_of_parse_and_map is returning VIRQ as 16,17,18
>> successfully. i hooked my chained interrupt handler for this VIRQ using
>> set_irq_chained_handler function. On my user defined interrupt handler 
>> when
>> i am searching the vector need to be returned i am getting 0 as vector. 
>> ie
>> using the function irq_linear_revmap.
>>
>> So here my doubt:
>> ============
>> Even irq_alloc_host has returned a irq_host for my pic, Why my custom map
>> funtion is not called during irq_of_parse_and_map function. Instead of my
>> map/xlate function it is calling mpic's map/xlate function?
>
> That's where I don't follow you...
>
> So interrupts 1,2,3 in your example are outputs of the FPGA PIC
> connected to inputs 1,2,3 of the MPIC. Those get mapped to virq 16.17
> and 18. Those are really MPIC interrupts.
>
> At some stage some interrupts -below- your FPGA PIC (whatever devices
> you have on the FPGA) are going to fire. it's -those- interrupts that
> will use map/xlate from the FPGA host when irq_of_parse_and_map() is
> called for them
>

you understood correctly. Here the problem lies.Correct me if i am wrong. So 
you are telling that irq_of_parse_and_map() will invoke the map/xlate of my 
FPGA pic. Right.

But this is what not happening. Instead of calling my map/xlate functions 
the irq_of_parse_and_map() function is invoking mpic's map/xlate function.

Here is the piece of code that we are using.

fpga_pic_irq_host = irq_alloc_host(pic, IRQ_HOST_MAP_LINEAR,
                        DPVPX0659_FPGA_NUM_IRQS,&fpga_pic_host_ops,
                        NO_IRQ);
        if (fpga_pic_irq_host == NULL) {
                printk("FPGA PIC: Unable to allocate host\n");
                return;
        }

        for (i = 0; i < 3; i++) {
                fpga_irqs[i] = irq_of_parse_and_map(pic, i);
                if (fpga_irqs[i] == NO_IRQ) {
                        printk("FPGA PIC: can't get irq %d.\n", i);
                        continue;
                }
                printk("interrupt from device tree : %d \n",fpga_irqs[i]);
                set_irq_chained_handler(dpvpx0659_fpga_irqs[i],dpvpx0659_fpga_pic_cascade);
        }

> IE. When -those- fire, the FPGA emits one of the 3 interrupts, and your
> cascade handler gets called. It will then fetch off the FPGA PIC what
> interrupts happened and revmap that.
>
> Cheers,
> Ben.
>
>> Kindly reply me soon.
>> Regards
>> Thirumalai
>>
>>
Thank you
Thirumalai 


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Re: Regarding FPGA based cascaded PIC

[Benjamin Herrenschmidt]

On Wed, 2009-11-04 at 18:09 +0530, Thirumalai wrote:
> you understood correctly. Here the problem lies.Correct me if i am wrong. So 
> you are telling that irq_of_parse_and_map() will invoke the map/xlate of my 
> FPGA pic. Right.
> 
> But this is what not happening. Instead of calling my map/xlate functions 
> the irq_of_parse_and_map() function is invoking mpic's map/xlate function.

irq_of_parse_and_map() will call the map/xlate function of the parent
PIC for the given interrupt.

In your case, the interrupts you are calling it for are defined as being
interrupts wiring the FPGA to the MPIC, hence are MPIC inputs, and thus
will be parsed/mapped by the MPIC. From the MPIC standpoint, the FPGA is
just a device.

So the code is doing what you tell it to do :-)

I don't understand what you are actually trying to acheive. If those 3
interrupts aren't outputs from the FPGA to the MPIC but input to the
FPGA then they shouldn't be there, they should be device interrupts
connected to the FPGA. Those will end up with map/xlate called in the
FPGA host.

Ben.

> Here is the piece of code that we are using.
> 
> fpga_pic_irq_host = irq_alloc_host(pic, IRQ_HOST_MAP_LINEAR,
>                         DPVPX0659_FPGA_NUM_IRQS,&fpga_pic_host_ops,
>                         NO_IRQ);
>         if (fpga_pic_irq_host == NULL) {
>                 printk("FPGA PIC: Unable to allocate host\n");
>                 return;
>         }
> 
>         for (i = 0; i < 3; i++) {
>                 fpga_irqs[i] = irq_of_parse_and_map(pic, i);
>                 if (fpga_irqs[i] == NO_IRQ) {
>                         printk("FPGA PIC: can't get irq %d.\n", i);
>                         continue;
>                 }
>                 printk("interrupt from device tree : %d \n",fpga_irqs[i]);
>                 set_irq_chained_handler(dpvpx0659_fpga_irqs[i],dpvpx0659_fpga_pic_cascade);
>         }
> 
> 

Re: Regarding FPGA based cascaded PIC

[thirumalai.p]

On Thu, 05 Nov 2009 07:51:22 +1100, Benjamin Herrenschmidt
<benh@kernel.crashing.org> wrote:
> On Wed, 2009-11-04 at 18:09 +0530, Thirumalai wrote:
>> you understood correctly. Here the problem lies.Correct me if i am
wrong.
>> So
>> you are telling that irq_of_parse_and_map() will invoke the map/xlate of
>> my
>> FPGA pic. Right.
>> 
>> But this is what not happening. Instead of calling my map/xlate
functions
>>
>> the irq_of_parse_and_map() function is invoking mpic's map/xlate
>> function.
> 
> irq_of_parse_and_map() will call the map/xlate function of the parent
> PIC for the given interrupt.
> 
> In your case, the interrupts you are calling it for are defined as being
> interrupts wiring the FPGA to the MPIC, hence are MPIC inputs, and thus
> will be parsed/mapped by the MPIC. From the MPIC standpoint, the FPGA is
> just a device.
> 
> So the code is doing what you tell it to do :-)
> 
> I don't understand what you are actually trying to acheive. If those 3
> interrupts aren't outputs from the FPGA to the MPIC but input to the
> FPGA then they shouldn't be there, they should be device interrupts
> connected to the FPGA. Those will end up with map/xlate called in the
> FPGA host.
> 
I Understood the thing. Thank you very much. So you mean to say that my
map/xlate functions will get invoked only for the devices which is
connected the FPGA PIC. So for example suppose if i have an WDT connected
to my FPGA then the interrupt-parent tag should point to FPGA-PIC. So at
that time the irq_of_parse_and_map() will invoke my map/xlate functions
right.


So i need to define the nodes on my device tree for the devices which are
all going to generate interrupts for FPGA and keeping the interrupt-parent
property as fpga-pic.

So my device node for WDT is something like the following

                    wdt@4,2000 {
                       #interrupt-cells = <2>;
                       device_type = "watchdog";
                       compatible = "gef,fpga-wdt";
                       reg = <0x4 0x2000 0x8>;
                       interrupts = <0x1a 0x4>;
                       interrupt-parent = <&fpga_pic>;
               };
Correct me if i am wrong.

> Ben.
> 
>> Here is the piece of code that we are using.
>> 
>> fpga_pic_irq_host = irq_alloc_host(pic, IRQ_HOST_MAP_LINEAR,
>>                         DPVPX0659_FPGA_NUM_IRQS,&fpga_pic_host_ops,
>>                         NO_IRQ);
>>         if (fpga_pic_irq_host == NULL) {
>>                 printk("FPGA PIC: Unable to allocate host\n");
>>                 return;
>>         }
>> 
>>         for (i = 0; i < 3; i++) {
>>                 fpga_irqs[i] = irq_of_parse_and_map(pic, i);
>>                 if (fpga_irqs[i] == NO_IRQ) {
>>                         printk("FPGA PIC: can't get irq %d.\n", i);
>>                         continue;
>>                 }
>>                 printk("interrupt from device tree : %d
>>                 \n",fpga_irqs[i]);
>>                
set_irq_chained_handler(dpvpx0659_fpga_irqs[i],dpvpx0659_fpga_pic_cascade);
>>         }
>> 
>>
Thank you
Thirumalai

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Re: Regarding FPGA based cascaded PIC

[Benjamin Herrenschmidt]

On Thu, 2009-11-05 at 08:16 +0530, thirumalai.p wrote:
> 
> I Understood the thing. Thank you very much. So you mean to say that
> my map/xlate functions will get invoked only for the devices which is
> connected the FPGA PIC. 

Right, and I fail to see how it would make any sense the other way
around :-)

Seriously, the map and xlate functions are used to hook up interrupt to
the PIC inputs. So logically, the 3 cascade interrupts are -inputs- to
the parent controller and as such get mapped by that controller. IE. The
parent is the only one to "understand" the format of the "interrupts"
properties for those and the interrupt numbers for those are HW numbers
in the parent space. It wouldn't make -any- sense to call map/xlate of
the child. In fact, for the code in question, the child PIC is just a
device, the fact that that device is itself a PIC is irrelevant.

> So for example suppose if i have an WDT connected
> to my FPGA then the interrupt-parent tag should point to FPGA-PIC. So
> at
> that time the irq_of_parse_and_map() will invoke my map/xlate
> functions
> right.

Yes.

> So i need to define the nodes on my device tree for the devices which
> are
> all going to generate interrupts for FPGA and keeping the
> interrupt-parent
> property as fpga-pic.

Or you can just keep track of the irq_host * of the FPGA and manually
call irq_create_mapping() passing it a HW number in the FPGA irq space
if you don't want to create device nodes for those children but the
device-node approach is preferred. 

> So my device node for WDT is something like the following
> 
>                     wdt@4,2000 {
>                        #interrupt-cells = <2>;
>                        device_type = "watchdog";
>                        compatible = "gef,fpga-wdt";
>                        reg = <0x4 0x2000 0x8>;
>                        interrupts = <0x1a 0x4>;
>                        interrupt-parent = <&fpga_pic>;
>                };
> Correct me if i am wrong.

It looks ok except that if I remember correctly, your FPGA PIC has a
#interrupt-cells value of '3' which means that it expects 3 numbers in
the "interrupts" property to define an interrupt (which your xlate
function is then going to translate into the appropriate HW number and
sense/polarity flags for linux).

So if you use only 2 numbers, you need to fix your #interrupt-cells
property value.

Cheers,
Ben.
 
> > Ben.
> > 
> >> Here is the piece of code that we are using.
> >> 
> >> fpga_pic_irq_host = irq_alloc_host(pic, IRQ_HOST_MAP_LINEAR,
> >>                         DPVPX0659_FPGA_NUM_IRQS,&fpga_pic_host_ops,
> >>                         NO_IRQ);
> >>         if (fpga_pic_irq_host == NULL) {
> >>                 printk("FPGA PIC: Unable to allocate host\n");
> >>                 return;
> >>         }
> >> 
> >>         for (i = 0; i < 3; i++) {
> >>                 fpga_irqs[i] = irq_of_parse_and_map(pic, i);
> >>                 if (fpga_irqs[i] == NO_IRQ) {
> >>                         printk("FPGA PIC: can't get irq %d.\n", i);
> >>                         continue;
> >>                 }
> >>                 printk("interrupt from device tree : %d
> >>                 \n",fpga_irqs[i]);
> >>                
> set_irq_chained_handler(dpvpx0659_fpga_irqs[i],dpvpx0659_fpga_pic_cascade);
> >>         }
> >> 
> >>
> Thank you
> Thirumalai