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Subject: Re: [PATCH 04/10] 8xx: Always pin kernel instruction TLB
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
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Date: Wed, 09 Dec 2009 15:19:59 +1100
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Cc: Scott Wood <scottwood@freescale.com>,
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On Fri, 2009-11-20 at 11:21 +0100, Joakim Tjernlund wrote:
> Various kernel asm modifies SRR0/SRR1 just before executing
> a rfi. If such code crosses a page boundary you risk a TLB miss
> which will clobber SRR0/SRR1. Avoid this by always pinning
> kernel instruction TLB space.
> 
> Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
> ---
>  arch/powerpc/kernel/head_8xx.S |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
> index a9f1ace..e70503d 100644
> --- a/arch/powerpc/kernel/head_8xx.S
> +++ b/arch/powerpc/kernel/head_8xx.S
> @@ -705,7 +705,7 @@ start_here:
>   */
>  initial_mmu:
>  	tlbia			/* Invalidate all TLB entries */
> -#ifdef CONFIG_PIN_TLB
> +#if 1 /* CONFIG_PIN_TLB */
>  	lis	r8, MI_RSV4I@h
>  	ori	r8, r8, 0x1c00
>  #else

Not nice. Either remove the config option or make sure all those code
sequences are appropriately aligned so it doesn't happen. I recommend
the later :-)

I'll apply the other patches.

Cheers,
Ben.