Kexec support for FSL-BookE, take two

Kexec support for FSL-BookE, take two

[Sebastian Andrzej Siewior]

This is take two :)
SMP support did not work in the first one and due to the lack of a working
SMP machine it is still absent. I took the e500v1 problem into account and
the result is that I now use multiple 256MiB mappings.
The final mapping covers the first 2GiB so the part of the highmem should
be also covered and not just kernel memory.

The first three patches prepare the entry code to work outside of the
first page. Patch 4 simply moves code and finally patch 5 implements the
kexec functionality.


Sebastian

[PATCH 1/5] powerpc/head fsl: fix the case where we are not in the first page

[Sebastian Andrzej Siewior]

From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

During boot we change the mapping a few times until we have a "defined"
mapping. During this procedure a small 4KiB mapping is created and after
that one a 64MiB. Currently the offset of the 4KiB page in that we run
is zero because the complete startup up code is in first page which
starts at RPN zero.
If the code is recycled and moved to another location then its execution
will fail because the start address in the 64 MiB mapping is computed
wrongly. It does not consider the offset to the page from the begin of
the memory.
This patch fixes this. Usually (system boot) r25 is zero so this does
not change anything unless the code is recycled.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
 arch/powerpc/kernel/head_fsl_booke.S |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 7f4bd7f..799ddbe 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -275,6 +275,7 @@ skpinv:	addi	r6,r6,1				/* Increment */
 1:	mflr	r9
 	rlwimi	r6,r9,0,20,31
 	addi	r6,r6,(2f - 1b)
+	add	r6, r6, r25
 	mtspr	SPRN_SRR0,r6
 	mtspr	SPRN_SRR1,r7
 	rfi				/* start execution out of TLB1[0] entry */
-- 
1.6.2.5

Re: [PATCH 1/5] powerpc/head fsl: fix the case where we are not in the first page

[Kumar Gala]

On Jan 15, 2010, at 10:41 AM, Sebastian Andrzej Siewior wrote:

> From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
>=20
> During boot we change the mapping a few times until we have a =
"defined"
> mapping. During this procedure a small 4KiB mapping is created and =
after
> that one a 64MiB. Currently the offset of the 4KiB page in that we run
> is zero because the complete startup up code is in first page which
> starts at RPN zero.
> If the code is recycled and moved to another location then its =
execution
> will fail because the start address in the 64 MiB mapping is computed
> wrongly. It does not consider the offset to the page from the begin of
> the memory.
> This patch fixes this. Usually (system boot) r25 is zero so this does
> not change anything unless the code is recycled.
>=20
> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
> ---
> arch/powerpc/kernel/head_fsl_booke.S |    1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)

I don't get this.  Why would would we not run at KERNELBASE?

- k

>=20
> diff --git a/arch/powerpc/kernel/head_fsl_booke.S =
b/arch/powerpc/kernel/head_fsl_booke.S
> index 7f4bd7f..799ddbe 100644
> --- a/arch/powerpc/kernel/head_fsl_booke.S
> +++ b/arch/powerpc/kernel/head_fsl_booke.S
> @@ -275,6 +275,7 @@ skpinv:	addi	r6,r6,1				=
/* Increment */
> 1:	mflr	r9
> 	rlwimi	r6,r9,0,20,31
> 	addi	r6,r6,(2f - 1b)
> +	add	r6, r6, r25
> 	mtspr	SPRN_SRR0,r6
> 	mtspr	SPRN_SRR1,r7
> 	rfi				/* start execution out of =
TLB1[0] entry */
> --=20
> 1.6.2.5

Re: [PATCH 1/5] powerpc/head fsl: fix the case where we are not in the first page

[Sebastian Andrzej Siewior]

* Kumar Gala | 2010-02-17 21:07:49 [-0600]:

>
>On Jan 15, 2010, at 10:41 AM, Sebastian Andrzej Siewior wrote:
>
>> From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
>> 
>> During boot we change the mapping a few times until we have a "defined"
>> mapping. During this procedure a small 4KiB mapping is created and after
>> that one a 64MiB. Currently the offset of the 4KiB page in that we run
>> is zero because the complete startup up code is in first page which
>> starts at RPN zero.
>> If the code is recycled and moved to another location then its execution
>> will fail because the start address in the 64 MiB mapping is computed
>> wrongly. It does not consider the offset to the page from the begin of
>> the memory.
>> This patch fixes this. Usually (system boot) r25 is zero so this does
>> not change anything unless the code is recycled.
>> 
>> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
>> ---
>> arch/powerpc/kernel/head_fsl_booke.S |    1 +
>> 1 files changed, 1 insertions(+), 0 deletions(-)
>
>I don't get this.  Why would would we not run at KERNELBASE?
We don't. The ld script makes sure that the entry code is at the begin
of our vmlinux and is linked against offset 0. This makes sure it starts
at RPN 0. If it would be linked against 4096 _or_ we would have other
code in front of us (atleast 4KiB) then the rfi down there would fail
because the code assumes that it was started at 0.
Right now this is basically a nop because the kernel always starts at 0.
This is only required because I grab the same code in kexec /
default_machine_kexec() and run it in a random page which is not RPN 0.

>- k
>
>> diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
>> index 7f4bd7f..799ddbe 100644
>> --- a/arch/powerpc/kernel/head_fsl_booke.S
>> +++ b/arch/powerpc/kernel/head_fsl_booke.S
>> @@ -275,6 +275,7 @@ skpinv:	addi	r6,r6,1				/* Increment */
>> 1:	mflr	r9
>> 	rlwimi	r6,r9,0,20,31
>> 	addi	r6,r6,(2f - 1b)
>> +	add	r6, r6, r25
>> 	mtspr	SPRN_SRR0,r6
>> 	mtspr	SPRN_SRR1,r7
>> 	rfi				/* start execution out of TLB1[0] entry */

Sebastian

[PATCH 2/5] powerpc/head fsl: move the temp 4KiB mapping to TLB0

[Sebastian Andrzej Siewior]

From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

Right now the setup code takes ESEL of the current mapping and puts the
temporary into ESEL (old_ESEL & 1 ) + 1 which is either one or two.
This is actually not required since all slots in TLB0 are invalid by now
and can be used.
This patch moved the temp mapping to TLB0, ESEL[0]. The invalidation of
TLB0 does not care about IPPROT so that part can go as well.
The benefit is that now the setup code may set every slot of TLB1 while
before that it was not allowed to touch ESEL one or two depending on the
old_ESEL.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
 arch/powerpc/kernel/head_fsl_booke.S |   20 +++++---------------
 1 files changed, 5 insertions(+), 15 deletions(-)

diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 799ddbe..cc76952 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -165,8 +165,6 @@ skpinv:	addi	r6,r6,1				/* Increment */
 	TLBSYNC
 
 /* 3. Setup a temp mapping and jump to it */
-	andi.	r5, r3, 0x1	/* Find an entry not used and is non-zero */
-	addi	r5, r5, 0x1
 	lis	r7,0x1000	/* Set MAS0(TLBSEL) = 1 */
 	rlwimi	r7,r3,16,4,15	/* Setup MAS0 = TLBSEL | ESEL(r3) */
 	mtspr	SPRN_MAS0,r7
@@ -194,12 +192,11 @@ skpinv:	addi	r6,r6,1				/* Increment */
 	ori	r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
 
 	/* Just modify the entry ID and EPN for the temp mapping */
-	lis	r7,0x1000	/* Set MAS0(TLBSEL) = 1 */
-	rlwimi	r7,r5,16,4,15	/* Setup MAS0 = TLBSEL | ESEL(r5) */
+	li	r7, 0		/* Set MAS0(TLBSEL) = 0 | ESEL(0) */
 	mtspr	SPRN_MAS0,r7
 	xori	r6,r4,1		/* Setup TMP mapping in the other Address space */
 	slwi	r6,r6,12
-	oris	r6,r6,(MAS1_VALID|MAS1_IPROT)@h
+	oris	r6,r6,(MAS1_VALID)@h
 	ori	r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
 	mtspr	SPRN_MAS1,r6
 	mfspr	r6,SPRN_MAS2
@@ -281,16 +278,9 @@ skpinv:	addi	r6,r6,1				/* Increment */
 	rfi				/* start execution out of TLB1[0] entry */
 
 /* 8. Clear out the temp mapping */
-2:	lis	r7,0x1000	/* Set MAS0(TLBSEL) = 1 */
-	rlwimi	r7,r5,16,4,15	/* Setup MAS0 = TLBSEL | ESEL(r5) */
-	mtspr	SPRN_MAS0,r7
-	tlbre
-	mfspr	r8,SPRN_MAS1
-	rlwinm	r8,r8,0,2,0	/* clear IPROT */
-	mtspr	SPRN_MAS1,r8
-	tlbwe
-	/* Invalidate TLB1 */
-	li	r9,0x0c
+2:
+	/* Invalidate TLB0 */
+	li	r9,0x04
 	tlbivax 0,r9
 	TLBSYNC
 
-- 
1.6.2.5

Re: [PATCH 2/5] powerpc/head fsl: move the temp 4KiB mapping to TLB0

[Kumar Gala]

On Jan 15, 2010, at 10:41 AM, Sebastian Andrzej Siewior wrote:

> From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
>=20
> Right now the setup code takes ESEL of the current mapping and puts =
the
> temporary into ESEL (old_ESEL & 1 ) + 1 which is either one or two.
> This is actually not required since all slots in TLB0 are invalid by =
now
> and can be used.
> This patch moved the temp mapping to TLB0, ESEL[0]. The invalidation =
of
> TLB0 does not care about IPPROT so that part can go as well.
> The benefit is that now the setup code may set every slot of TLB1 =
while
> before that it was not allowed to touch ESEL one or two depending on =
the
> old_ESEL.
>=20
> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
> ---
> arch/powerpc/kernel/head_fsl_booke.S |   20 +++++---------------
> 1 files changed, 5 insertions(+), 15 deletions(-)

this is problematic, we can't assume that TLB0 is safe.  It possible =
some other software is running on a second core and does a broadcast =
tlbivax which will wipe what's in TLB0.

- k=

Re: [PATCH 2/5] powerpc/head fsl: move the temp 4KiB mapping to TLB0

[Sebastian Andrzej Siewior]

* Kumar Gala | 2010-02-17 21:09:08 [-0600]:

>
>On Jan 15, 2010, at 10:41 AM, Sebastian Andrzej Siewior wrote:
>
>> From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
>> 
>> Right now the setup code takes ESEL of the current mapping and puts the
>> temporary into ESEL (old_ESEL & 1 ) + 1 which is either one or two.
>> This is actually not required since all slots in TLB0 are invalid by now
>> and can be used.
>> This patch moved the temp mapping to TLB0, ESEL[0]. The invalidation of
>> TLB0 does not care about IPPROT so that part can go as well.
>> The benefit is that now the setup code may set every slot of TLB1 while
>> before that it was not allowed to touch ESEL one or two depending on the
>> old_ESEL.
>> 
>> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
>> ---
>> arch/powerpc/kernel/head_fsl_booke.S |   20 +++++---------------
>> 1 files changed, 5 insertions(+), 15 deletions(-)
>
>this is problematic, we can't assume that TLB0 is safe.  It possible some other software is running on a second core and does a broadcast tlbivax which will wipe what's in TLB0.

Ah right SMP. So if CPU0 would wait until CPU1-X are up and kick them
one by one could make it work but is not that pretty.
So let me think of something. I will probably just skip the current
mapping while making new ones for kexec.

>- k

Sebastian

[PATCH 3/5] powerpc/head fsl: replace a hardcoded constant

[Sebastian Andrzej Siewior]

From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

24 is offset between the opcode past bl and past rfi. This makes it more
obvious.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
 arch/powerpc/kernel/head_fsl_booke.S |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index cc76952..445eddd 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -211,11 +211,11 @@ skpinv:	addi	r6,r6,1				/* Increment */
 	bl	1f		/* Find our address */
 1:	mflr	r9
 	rlwimi	r7,r9,0,20,31
-	addi	r7,r7,24
+	addi	r7,r7,(2f - 1b)
 	mtspr	SPRN_SRR0,r7
 	mtspr	SPRN_SRR1,r6
 	rfi
-
+2:
 /* 4. Clear out PIDs & Search info */
 	li	r6,0
 	mtspr   SPRN_MAS6,r6
-- 
1.6.2.5

Re: [PATCH 3/5] powerpc/head fsl: replace a hardcoded constant

[Kumar Gala]

On Jan 15, 2010, at 10:41 AM, Sebastian Andrzej Siewior wrote:

> From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
> 
> 24 is offset between the opcode past bl and past rfi. This makes it more
> obvious.
> 
> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
> ---
> arch/powerpc/kernel/head_fsl_booke.S |    4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)

applied to next

- k

[PATCH 4/5] powerpc/fsl head: move the entry setup code into a seperate file

[Sebastian Andrzej Siewior]

From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

This patch moves only the initial entry code which setups the mapping
from what ever to KERNELBASE into a seperate file. No code change has
been made here.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
 arch/powerpc/kernel/fsl_booke_entry_mapping.S |  189 +++++++++++++++++++++++++
 arch/powerpc/kernel/head_fsl_booke.S          |  189 +------------------------
 2 files changed, 190 insertions(+), 188 deletions(-)
 create mode 100644 arch/powerpc/kernel/fsl_booke_entry_mapping.S

diff --git a/arch/powerpc/kernel/fsl_booke_entry_mapping.S b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
new file mode 100644
index 0000000..d629618
--- /dev/null
+++ b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
@@ -0,0 +1,189 @@
+/* 1. Find the index of the entry we're executing in */
+	bl	invstr				/* Find our address */
+invstr:	mflr	r6				/* Make it accessible */
+	mfmsr	r7
+	rlwinm	r4,r7,27,31,31			/* extract MSR[IS] */
+	mfspr	r7, SPRN_PID0
+	slwi	r7,r7,16
+	or	r7,r7,r4
+	mtspr	SPRN_MAS6,r7
+	tlbsx	0,r6				/* search MSR[IS], SPID=PID0 */
+	mfspr	r7,SPRN_MAS1
+	andis.	r7,r7,MAS1_VALID@h
+	bne	match_TLB
+
+	mfspr	r7,SPRN_MMUCFG
+	rlwinm	r7,r7,21,28,31			/* extract MMUCFG[NPIDS] */
+	cmpwi	r7,3
+	bne	match_TLB			/* skip if NPIDS != 3 */
+
+	mfspr	r7,SPRN_PID1
+	slwi	r7,r7,16
+	or	r7,r7,r4
+	mtspr	SPRN_MAS6,r7
+	tlbsx	0,r6				/* search MSR[IS], SPID=PID1 */
+	mfspr	r7,SPRN_MAS1
+	andis.	r7,r7,MAS1_VALID@h
+	bne	match_TLB
+	mfspr	r7, SPRN_PID2
+	slwi	r7,r7,16
+	or	r7,r7,r4
+	mtspr	SPRN_MAS6,r7
+	tlbsx	0,r6				/* Fall through, we had to match */
+
+match_TLB:
+	mfspr	r7,SPRN_MAS0
+	rlwinm	r3,r7,16,20,31			/* Extract MAS0(Entry) */
+
+	mfspr	r7,SPRN_MAS1			/* Insure IPROT set */
+	oris	r7,r7,MAS1_IPROT@h
+	mtspr	SPRN_MAS1,r7
+	tlbwe
+
+/* 2. Invalidate all entries except the entry we're executing in */
+	mfspr	r9,SPRN_TLB1CFG
+	andi.	r9,r9,0xfff
+	li	r6,0				/* Set Entry counter to 0 */
+1:	lis	r7,0x1000			/* Set MAS0(TLBSEL) = 1 */
+	rlwimi	r7,r6,16,4,15			/* Setup MAS0 = TLBSEL | ESEL(r6) */
+	mtspr	SPRN_MAS0,r7
+	tlbre
+	mfspr	r7,SPRN_MAS1
+	rlwinm	r7,r7,0,2,31			/* Clear MAS1 Valid and IPROT */
+	cmpw	r3,r6
+	beq	skpinv				/* Dont update the current execution TLB */
+	mtspr	SPRN_MAS1,r7
+	tlbwe
+	isync
+skpinv:	addi	r6,r6,1				/* Increment */
+	cmpw	r6,r9				/* Are we done? */
+	bne	1b				/* If not, repeat */
+
+	/* Invalidate TLB0 */
+	li	r6,0x04
+	tlbivax 0,r6
+	TLBSYNC
+	/* Invalidate TLB1 */
+	li	r6,0x0c
+	tlbivax 0,r6
+	TLBSYNC
+
+/* 3. Setup a temp mapping and jump to it */
+	lis	r7,0x1000	/* Set MAS0(TLBSEL) = 1 */
+	rlwimi	r7,r3,16,4,15	/* Setup MAS0 = TLBSEL | ESEL(r3) */
+	mtspr	SPRN_MAS0,r7
+	tlbre
+
+	/* grab and fixup the RPN */
+	mfspr	r6,SPRN_MAS1	/* extract MAS1[SIZE] */
+	rlwinm	r6,r6,25,27,31
+	li	r8,-1
+	addi	r6,r6,10
+	slw	r6,r8,r6	/* convert to mask */
+
+	bl	1f		/* Find our address */
+1:	mflr	r7
+
+	mfspr	r8,SPRN_MAS3
+#ifdef CONFIG_PHYS_64BIT
+	mfspr	r23,SPRN_MAS7
+#endif
+	and	r8,r6,r8
+	subfic	r9,r6,-4096
+	and	r9,r9,r7
+
+	or	r25,r8,r9
+	ori	r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
+
+	/* Just modify the entry ID and EPN for the temp mapping */
+	li	r7, 0		/* Set MAS0(TLBSEL) = 0 | ESEL(0) */
+	mtspr	SPRN_MAS0,r7
+	xori	r6,r4,1		/* Setup TMP mapping in the other Address space */
+	slwi	r6,r6,12
+	oris	r6,r6,(MAS1_VALID)@h
+	ori	r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
+	mtspr	SPRN_MAS1,r6
+	mfspr	r6,SPRN_MAS2
+	li	r7,0		/* temp EPN = 0 */
+	rlwimi	r7,r6,0,20,31
+	mtspr	SPRN_MAS2,r7
+	mtspr	SPRN_MAS3,r8
+	tlbwe
+
+	xori	r6,r4,1
+	slwi	r6,r6,5		/* setup new context with other address space */
+	bl	1f		/* Find our address */
+1:	mflr	r9
+	rlwimi	r7,r9,0,20,31
+	addi	r7,r7,(2f - 1b)
+	mtspr	SPRN_SRR0,r7
+	mtspr	SPRN_SRR1,r6
+	rfi
+2:
+/* 4. Clear out PIDs & Search info */
+	li	r6,0
+	mtspr   SPRN_MAS6,r6
+	mtspr	SPRN_PID0,r6
+
+	mfspr	r7,SPRN_MMUCFG
+	rlwinm	r7,r7,21,28,31			/* extract MMUCFG[NPIDS] */
+	cmpwi	r7,3
+	bne	2f				/* skip if NPIDS != 3 */
+
+	mtspr	SPRN_PID1,r6
+	mtspr	SPRN_PID2,r6
+
+/* 5. Invalidate mapping we started in */
+2:
+	lis	r7,0x1000	/* Set MAS0(TLBSEL) = 1 */
+	rlwimi	r7,r3,16,4,15	/* Setup MAS0 = TLBSEL | ESEL(r3) */
+	mtspr	SPRN_MAS0,r7
+	tlbre
+	mfspr	r6,SPRN_MAS1
+	rlwinm	r6,r6,0,2,0	/* clear IPROT */
+	mtspr	SPRN_MAS1,r6
+	tlbwe
+	/* Invalidate TLB1 */
+	li	r9,0x0c
+	tlbivax 0,r9
+	TLBSYNC
+
+/* The mapping only needs to be cache-coherent on SMP */
+#ifdef CONFIG_SMP
+#define M_IF_SMP	MAS2_M
+#else
+#define M_IF_SMP	0
+#endif
+
+/* 6. Setup KERNELBASE mapping in TLB1[0] */
+	lis	r6,0x1000		/* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
+	mtspr	SPRN_MAS0,r6
+	lis	r6,(MAS1_VALID|MAS1_IPROT)@h
+	ori	r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
+	mtspr	SPRN_MAS1,r6
+	lis	r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
+	ori	r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
+	mtspr	SPRN_MAS2,r6
+	mtspr	SPRN_MAS3,r8
+	tlbwe
+
+/* 7. Jump to KERNELBASE mapping */
+	lis	r6,(KERNELBASE & ~0xfff)@h
+	ori	r6,r6,(KERNELBASE & ~0xfff)@l
+	lis	r7,MSR_KERNEL@h
+	ori	r7,r7,MSR_KERNEL@l
+	bl	1f			/* Find our address */
+1:	mflr	r9
+	rlwimi	r6,r9,0,20,31
+	addi	r6,r6,(2f - 1b)
+	add	r6, r6, r25
+	mtspr	SPRN_SRR0,r6
+	mtspr	SPRN_SRR1,r7
+	rfi				/* start execution out of TLB1[0] entry */
+
+/* 8. Clear out the temp mapping */
+2:
+	/* Invalidate TLB0 */
+	li	r9,0x04
+	tlbivax 0,r9
+	TLBSYNC
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 445eddd..4de9bc5 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -94,195 +94,8 @@ _ENTRY(_start);
  */
 
 _ENTRY(__early_start)
-/* 1. Find the index of the entry we're executing in */
-	bl	invstr				/* Find our address */
-invstr:	mflr	r6				/* Make it accessible */
-	mfmsr	r7
-	rlwinm	r4,r7,27,31,31			/* extract MSR[IS] */
-	mfspr	r7, SPRN_PID0
-	slwi	r7,r7,16
-	or	r7,r7,r4
-	mtspr	SPRN_MAS6,r7
-	tlbsx	0,r6				/* search MSR[IS], SPID=PID0 */
-	mfspr	r7,SPRN_MAS1
-	andis.	r7,r7,MAS1_VALID@h
-	bne	match_TLB
-
-	mfspr	r7,SPRN_MMUCFG
-	rlwinm	r7,r7,21,28,31			/* extract MMUCFG[NPIDS] */
-	cmpwi	r7,3
-	bne	match_TLB			/* skip if NPIDS != 3 */
-
-	mfspr	r7,SPRN_PID1
-	slwi	r7,r7,16
-	or	r7,r7,r4
-	mtspr	SPRN_MAS6,r7
-	tlbsx	0,r6				/* search MSR[IS], SPID=PID1 */
-	mfspr	r7,SPRN_MAS1
-	andis.	r7,r7,MAS1_VALID@h
-	bne	match_TLB
-	mfspr	r7, SPRN_PID2
-	slwi	r7,r7,16
-	or	r7,r7,r4
-	mtspr	SPRN_MAS6,r7
-	tlbsx	0,r6				/* Fall through, we had to match */
-
-match_TLB:
-	mfspr	r7,SPRN_MAS0
-	rlwinm	r3,r7,16,20,31			/* Extract MAS0(Entry) */
-
-	mfspr	r7,SPRN_MAS1			/* Insure IPROT set */
-	oris	r7,r7,MAS1_IPROT@h
-	mtspr	SPRN_MAS1,r7
-	tlbwe
-
-/* 2. Invalidate all entries except the entry we're executing in */
-	mfspr	r9,SPRN_TLB1CFG
-	andi.	r9,r9,0xfff
-	li	r6,0				/* Set Entry counter to 0 */
-1:	lis	r7,0x1000			/* Set MAS0(TLBSEL) = 1 */
-	rlwimi	r7,r6,16,4,15			/* Setup MAS0 = TLBSEL | ESEL(r6) */
-	mtspr	SPRN_MAS0,r7
-	tlbre
-	mfspr	r7,SPRN_MAS1
-	rlwinm	r7,r7,0,2,31			/* Clear MAS1 Valid and IPROT */
-	cmpw	r3,r6
-	beq	skpinv				/* Dont update the current execution TLB */
-	mtspr	SPRN_MAS1,r7
-	tlbwe
-	isync
-skpinv:	addi	r6,r6,1				/* Increment */
-	cmpw	r6,r9				/* Are we done? */
-	bne	1b				/* If not, repeat */
-
-	/* Invalidate TLB0 */
-	li	r6,0x04
-	tlbivax 0,r6
-	TLBSYNC
-	/* Invalidate TLB1 */
-	li	r6,0x0c
-	tlbivax 0,r6
-	TLBSYNC
-
-/* 3. Setup a temp mapping and jump to it */
-	lis	r7,0x1000	/* Set MAS0(TLBSEL) = 1 */
-	rlwimi	r7,r3,16,4,15	/* Setup MAS0 = TLBSEL | ESEL(r3) */
-	mtspr	SPRN_MAS0,r7
-	tlbre
-
-	/* grab and fixup the RPN */
-	mfspr	r6,SPRN_MAS1	/* extract MAS1[SIZE] */
-	rlwinm	r6,r6,25,27,31
-	li	r8,-1
-	addi	r6,r6,10
-	slw	r6,r8,r6	/* convert to mask */
-
-	bl	1f		/* Find our address */
-1:	mflr	r7
-
-	mfspr	r8,SPRN_MAS3
-#ifdef CONFIG_PHYS_64BIT
-	mfspr	r23,SPRN_MAS7
-#endif
-	and	r8,r6,r8
-	subfic	r9,r6,-4096
-	and	r9,r9,r7
-
-	or	r25,r8,r9
-	ori	r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
-
-	/* Just modify the entry ID and EPN for the temp mapping */
-	li	r7, 0		/* Set MAS0(TLBSEL) = 0 | ESEL(0) */
-	mtspr	SPRN_MAS0,r7
-	xori	r6,r4,1		/* Setup TMP mapping in the other Address space */
-	slwi	r6,r6,12
-	oris	r6,r6,(MAS1_VALID)@h
-	ori	r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
-	mtspr	SPRN_MAS1,r6
-	mfspr	r6,SPRN_MAS2
-	li	r7,0		/* temp EPN = 0 */
-	rlwimi	r7,r6,0,20,31
-	mtspr	SPRN_MAS2,r7
-	mtspr	SPRN_MAS3,r8
-	tlbwe
-
-	xori	r6,r4,1
-	slwi	r6,r6,5		/* setup new context with other address space */
-	bl	1f		/* Find our address */
-1:	mflr	r9
-	rlwimi	r7,r9,0,20,31
-	addi	r7,r7,(2f - 1b)
-	mtspr	SPRN_SRR0,r7
-	mtspr	SPRN_SRR1,r6
-	rfi
-2:
-/* 4. Clear out PIDs & Search info */
-	li	r6,0
-	mtspr   SPRN_MAS6,r6
-	mtspr	SPRN_PID0,r6
-
-	mfspr	r7,SPRN_MMUCFG
-	rlwinm	r7,r7,21,28,31			/* extract MMUCFG[NPIDS] */
-	cmpwi	r7,3
-	bne	2f				/* skip if NPIDS != 3 */
 
-	mtspr	SPRN_PID1,r6
-	mtspr	SPRN_PID2,r6
-
-/* 5. Invalidate mapping we started in */
-2:
-	lis	r7,0x1000	/* Set MAS0(TLBSEL) = 1 */
-	rlwimi	r7,r3,16,4,15	/* Setup MAS0 = TLBSEL | ESEL(r3) */
-	mtspr	SPRN_MAS0,r7
-	tlbre
-	mfspr	r6,SPRN_MAS1
-	rlwinm	r6,r6,0,2,0	/* clear IPROT */
-	mtspr	SPRN_MAS1,r6
-	tlbwe
-	/* Invalidate TLB1 */
-	li	r9,0x0c
-	tlbivax 0,r9
-	TLBSYNC
-
-/* The mapping only needs to be cache-coherent on SMP */
-#ifdef CONFIG_SMP
-#define M_IF_SMP	MAS2_M
-#else
-#define M_IF_SMP	0
-#endif
-
-/* 6. Setup KERNELBASE mapping in TLB1[0] */
-	lis	r6,0x1000		/* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
-	mtspr	SPRN_MAS0,r6
-	lis	r6,(MAS1_VALID|MAS1_IPROT)@h
-	ori	r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
-	mtspr	SPRN_MAS1,r6
-	lis	r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
-	ori	r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
-	mtspr	SPRN_MAS2,r6
-	mtspr	SPRN_MAS3,r8
-	tlbwe
-
-/* 7. Jump to KERNELBASE mapping */
-	lis	r6,(KERNELBASE & ~0xfff)@h
-	ori	r6,r6,(KERNELBASE & ~0xfff)@l
-	lis	r7,MSR_KERNEL@h
-	ori	r7,r7,MSR_KERNEL@l
-	bl	1f			/* Find our address */
-1:	mflr	r9
-	rlwimi	r6,r9,0,20,31
-	addi	r6,r6,(2f - 1b)
-	add	r6, r6, r25
-	mtspr	SPRN_SRR0,r6
-	mtspr	SPRN_SRR1,r7
-	rfi				/* start execution out of TLB1[0] entry */
-
-/* 8. Clear out the temp mapping */
-2:
-	/* Invalidate TLB0 */
-	li	r9,0x04
-	tlbivax 0,r9
-	TLBSYNC
+#include "fsl_booke_entry_mapping.S"
 
 	/* Establish the interrupt vector offsets */
 	SET_IVOR(0,  CriticalInput);
-- 
1.6.2.5

[PATCH 5/5] powerpc/kexec: Add support for FSL-BookE

[Sebastian Andrzej Siewior]

From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

This adds support kexec on FSL-BookE where the MMU can not be simply
switched off. The code borrows the initial MMU-setup code to create the
identical mapping mapping. The only difference to the original boot code
is the size of the mapping(s) and the executeable address.
The kexec code maps the first 2 GiB of memory in 256 MiB steps. This
should work also on e500v1 boxes.
SMP support is still not available.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
 arch/powerpc/Kconfig                          |    2 +-
 arch/powerpc/include/asm/kexec.h              |   13 +++++++++
 arch/powerpc/kernel/fsl_booke_entry_mapping.S |   34 +++++++++++++++++++++++++
 arch/powerpc/kernel/head_fsl_booke.S          |    2 +
 arch/powerpc/kernel/misc_32.S                 |   17 ++++++++++++
 5 files changed, 67 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index ba3948c..788a154 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -335,7 +335,7 @@ config ARCH_ENABLE_MEMORY_HOTREMOVE
 
 config KEXEC
 	bool "kexec system call (EXPERIMENTAL)"
-	depends on PPC_BOOK3S && EXPERIMENTAL
+	depends on (PPC_BOOK3S || (FSL_BOOKE && !SMP)) && EXPERIMENTAL
 	help
 	  kexec is a system call that implements the ability to shutdown your
 	  current kernel, and to start another kernel.  It is like a reboot
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
index 7e06b43..83f6481 100644
--- a/arch/powerpc/include/asm/kexec.h
+++ b/arch/powerpc/include/asm/kexec.h
@@ -2,6 +2,18 @@
 #define _ASM_POWERPC_KEXEC_H
 #ifdef __KERNEL__
 
+#ifdef CONFIG_FSL_BOOKE
+
+/*
+ * On FSL-BookE we setup a 1:1 mapping which covers the first 2GiB of memory
+ * and therefore we can only deal with memory within this range
+ */
+#define KEXEC_SOURCE_MEMORY_LIMIT	(2 * 1024 * 1024 * 1024UL)
+#define KEXEC_DESTINATION_MEMORY_LIMIT	(2 * 1024 * 1024 * 1024UL)
+#define KEXEC_CONTROL_MEMORY_LIMIT	(2 * 1024 * 1024 * 1024UL)
+
+#else
+
 /*
  * Maximum page that is mapped directly into kernel memory.
  * XXX: Since we copy virt we can use any page we allocate
@@ -21,6 +33,7 @@
 /* TASK_SIZE, probably left over from use_mm ?? */
 #define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
 #endif
+#endif
 
 #define KEXEC_CONTROL_PAGE_SIZE 4096
 
diff --git a/arch/powerpc/kernel/fsl_booke_entry_mapping.S b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
index d629618..1fc283a 100644
--- a/arch/powerpc/kernel/fsl_booke_entry_mapping.S
+++ b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
@@ -155,6 +155,8 @@ skpinv:	addi	r6,r6,1				/* Increment */
 #define M_IF_SMP	0
 #endif
 
+#if defined(ENTRY_MAPPING_BOOT_SETUP)
+
 /* 6. Setup KERNELBASE mapping in TLB1[0] */
 	lis	r6,0x1000		/* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
 	mtspr	SPRN_MAS0,r6
@@ -170,6 +172,38 @@ skpinv:	addi	r6,r6,1				/* Increment */
 /* 7. Jump to KERNELBASE mapping */
 	lis	r6,(KERNELBASE & ~0xfff)@h
 	ori	r6,r6,(KERNELBASE & ~0xfff)@l
+
+#elif defined(ENTRY_MAPPING_KEXEC_SETUP)
+/*
+ * 6. Setup 1:1 mapping TLB1[0 - 8]. We start 0 and map in 256 MiB steps the
+ * first 2GiB of memory.
+ */
+	lis	r10, (MAS1_VALID|MAS1_IPROT)@h
+	ori	r10,r10, (MAS1_TSIZE(BOOK3E_PAGESZ_256M))@l
+	li	r11, 0		// We use 16 esel slots and map 4 GiB
+	li	r0, 8		// of mem 1:1 from 0 to 4 GiB - 1 in
+	mtctr	r0		// 256 MiB mem steps
+
+next_tlb_setup:
+	rlwinm	r0, r11, 16, 4, 15	// Compute esel
+	rlwinm	r9, r11, 28, 0, 3	// Compute [ER]PN
+	oris	r0, r0, (MAS0_TLBSEL(1))@h
+	mtspr	SPRN_MAS0,r0
+	mtspr	SPRN_MAS1,r10
+	mtspr	SPRN_MAS2,r9
+	ori	r9, r9, (MAS3_SX|MAS3_SW|MAS3_SR)
+	mtspr	SPRN_MAS3,r9
+	tlbwe
+	addi	r11, r11, 1
+	bdnz+	next_tlb_setup
+
+/* 7. Jump to KERNELBASE mapping */
+	li	r6, 0
+
+#else
+	#error You need to specify the mapping or not use this at all.
+#endif
+
 	lis	r7,MSR_KERNEL@h
 	ori	r7,r7,MSR_KERNEL@l
 	bl	1f			/* Find our address */
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 4de9bc5..fcace7b 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -95,7 +95,9 @@ _ENTRY(_start);
 
 _ENTRY(__early_start)
 
+#define ENTRY_MAPPING_BOOT_SETUP
 #include "fsl_booke_entry_mapping.S"
+#undef ENTRY_MAPPING_BOOT_SETUP
 
 	/* Establish the interrupt vector offsets */
 	SET_IVOR(0,  CriticalInput);
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 8649f53..99bc652 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -706,6 +706,22 @@ relocate_new_kernel:
 	/* r4 = reboot_code_buffer */
 	/* r5 = start_address      */
 
+#ifdef CONFIG_FSL_BOOKE
+
+	mr	r29, r3
+	mr	r30, r4
+	mr	r31, r5
+
+#define ENTRY_MAPPING_KEXEC_SETUP
+#include "fsl_booke_entry_mapping.S"
+#undef ENTRY_MAPPING_KEXEC_SETUP
+
+	mr      r3, r29
+	mr      r4, r30
+	mr      r5, r31
+
+	li	r0, 0
+#else
 	li	r0, 0
 
 	/*
@@ -722,6 +738,7 @@ relocate_new_kernel:
 	rfi
 
 1:
+#endif
 	/* from this point address translation is turned off */
 	/* and interrupts are disabled */
 
-- 
1.6.2.5

Re: Kexec support for FSL-BookE, take two

[Kumar Gala]

On Jan 15, 2010, at 10:41 AM, Sebastian Andrzej Siewior wrote:

> This is take two :)
> SMP support did not work in the first one and due to the lack of a =
working
> SMP machine it is still absent. I took the e500v1 problem into account =
and
> the result is that I now use multiple 256MiB mappings.
> The final mapping covers the first 2GiB so the part of the highmem =
should
> be also covered and not just kernel memory.
>=20
> The first three patches prepare the entry code to work outside of the
> first page. Patch 4 simply moves code and finally patch 5 implements =
the
> kexec functionality.

What do you think we need for SMP support? I'm happy to test out on SMP =
HW (8572)

- k=

Re: Kexec support for FSL-BookE, take two

[Sebastian Andrzej Siewior]

* Kumar Gala | 2010-01-15 11:53:13 [-0600]:

>On Jan 15, 2010, at 10:41 AM, Sebastian Andrzej Siewior wrote:
>
>> This is take two :)
>> SMP support did not work in the first one and due to the lack of a working
>> SMP machine it is still absent. I took the e500v1 problem into account and
>> the result is that I now use multiple 256MiB mappings.
>> The final mapping covers the first 2GiB so the part of the highmem should
>> be also covered and not just kernel memory.
>> 
>> The first three patches prepare the entry code to work outside of the
>> first page. Patch 4 simply moves code and finally patch 5 implements the
>> kexec functionality.
>
>What do you think we need for SMP support? I'm happy to test out on SMP HW (8572)
Depends on how we want to do it :)
X86 for instance disables all "other" CPUs in machine_shutdown().
Therefore during machine_kexec() they are off and are bootstraped again
during system boot.
PPC64 doesn't do this that way. They call smp_call_function() witch puts
the CPU into real mode and let them spin in a "save" state until they
get released them from this state.

If we are able to disable the CPU and bootstrap it from scratch than I
guess we could do the way x86 does it.
If the CPU keeps the TLB/MMU data after reactivated (what I assume) than we
have to do the same thing that ppc64 does:
- let the other CPU have the also the identical mapping
- spin in a save state in kernel, then purgatory. I guess I should
  revisit ppc64 code for details :)
- update the device tree so kernel can kick the other CPU during boot.

>
>- k

Sebastian

Re: Kexec support for FSL-BookE, take two

[Sebastian Andrzej Siewior]

* Kumar Gala | 2010-01-15 11:53:13 [-0600]:

>On Jan 15, 2010, at 10:41 AM, Sebastian Andrzej Siewior wrote:
>
>> This is take two :)
>What do you think we need for SMP support? I'm happy to test out on SMP HW (8572)

I've updated a comment in the last patch which was wrong. I've pushed
the updated patch to my git tree at [0]. I can post the whole patch if
you want :)
Do you have any idea when you will be able to take a look at this
series?

[0] http://git.breakpoint.cc/cgi-bin/gitweb.cgi?p=bigeasy/linux.git;a=shortlog;h=refs/heads/kexec_booke

>- k

Sebastian

Re: Kexec support for FSL-BookE, take two

[wilbur.chan]

2010/1/16 Sebastian Andrzej Siewior <linuxppc-dev@ml.breakpoint.cc>:
> This is take two :)
> SMP support did not work in the first one and due to the lack of a working
> SMP machine it is still absent. I took the e500v1 problem into account and
> the result is that I now use multiple 256MiB mappings.
> The final mapping covers the first 2GiB so the part of the highmem should
> be also covered and not just kernel memory.
>
> The first three patches prepare the entry code to work outside of the
> first page. Patch 4 simply moves code and finally patch 5 implements the
> kexec functionality.


Hi, sebastian

Is it possible to  avoid setting up  the 1:1 mapping  but to convert
physical address into virt before relocate , like mips do?

2010/1/16 Kumar Gala <galak@kernel.crashing.org>:

>
> What do you think we need for SMP support? I'm happy to test out on SMP HW (8572)
>

I'm happy to test it too   :D

Re: Kexec support for FSL-BookE, take two

[Sebastian Andrzej Siewior]

* wilbur.chan | 2010-01-16 20:35:50 [+0800]:

>Is it possible to  avoid setting up  the 1:1 mapping  but to convert
>physical address into virt before relocate , like mips do?
No.

>2010/1/16 Kumar Gala <galak@kernel.crashing.org>:
>
>>
>> What do you think we need for SMP support? I'm happy to test out on SMP HW (8572)
>>
>
>I'm happy to test it too   :D

I have a 8572 myself but it is not working reliably right now. I will
try to merge the userland pieces and then I will probably look at SMP.

Sebastian